From nobody Sun Feb 8 15:30:56 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2F58524168D for ; Tue, 21 Oct 2025 05:20:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761024037; cv=none; b=ZP4prb9vtKILlUmATNC5KufXnFIyN7IVBSnRXNU08vfOHu/AYfX3U0w4gFjMcGL5FL100rk41bnMG0JQVgY8NQv1wbnOQYfO+M2HN798BGvRJLNyDeZRQydIot7WsrbDW1NRlNKJRq/bZUwmEQs3EEm9riTPVrTWvKr8OLszyX0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761024037; c=relaxed/simple; bh=anFenXs5SSmIQDDFcAAXj+497BeD1hkVlrd+XbtHMbM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nPlTGT5mbmOVp/A4X4/M7CRraWCMVL3ruccl6zIW2acCuZO46x+OAtZ/HWc2PJMBR1kUtXfLLD3hdR2XBK6WSJD//qIt29EE3ewE99CiGjUi7EhUsUJ+7qfmgvxkvBfkrXdqwdD/fOjoyGhjAP+L9H1N0sYzh+IWPRiy6wHFZJA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AA446175D; Mon, 20 Oct 2025 22:20:26 -0700 (PDT) Received: from ergosum.cambridge.arm.com (ergosum.cambridge.arm.com [10.1.196.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7D9943F59E; Mon, 20 Oct 2025 22:20:33 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org Subject: [PATCH 1/2] arm64/mm: Drop redundant 'level' range trimming in __tlbi_level() Date: Tue, 21 Oct 2025 06:20:21 +0100 Message-Id: <20251021052022.2898275-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20251021052022.2898275-1-anshuman.khandual@arm.com> References: <20251021052022.2898275-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Page table level value has already known to be in the range [0..3] before entering inside the conditional 'if' loop. Hence any subsequent trimming is just redundant and can be dropped off. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/tlbflush.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlb= flush.h index 18a5dc0c9a54..131096094f5b 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -110,7 +110,7 @@ static inline unsigned long get_trans_granule(void) \ if (alternative_has_cap_unlikely(ARM64_HAS_ARMv8_4_TTL) && \ level >=3D 0 && level <=3D 3) { \ - u64 ttl =3D level & 3; \ + u64 ttl =3D level; \ ttl |=3D get_trans_granule() << 2; \ arg &=3D ~TLBI_TTL_MASK; \ arg |=3D FIELD_PREP(TLBI_TTL_MASK, ttl); \ --=20 2.30.2 From nobody Sun Feb 8 15:30:56 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B1577246BD7 for ; Tue, 21 Oct 2025 05:20:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761024038; cv=none; b=gXNanVeWVlU6aF+L75WRyebPf191K1yqDedfj5AzrSe6WwEhKuNkm2lAcmzpFPxPEavmbblTjYR6PACJ82ihM19zyznPBLVsBXop3RBOvXzAGAo2HlOA1XEdBt5d1W7m9la9ontDAPIRobhyEz5zfw6m0B2THOtCofdWWZeYreA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761024038; c=relaxed/simple; bh=GaVG21qFGL5Wv3M+puZKLzXL3wwihN2P/oPJ2RoSpRo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cWpTVcyqLPe/gmZg9GEmAZLEfguNVDtSTEn6tsVdpYr7CJWWIKQ3UPSASNu/Ic0O1aPbyWvzJXl505QtHugy0T1/0zYTas/JGmEZN5TRlrSp37Lj6C1mKr+wgfNZjbQi+l8aKPQBZ+UXIbvnM7I13f00DfseHXSeV1aPPu2VnB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 045AD19F0; Mon, 20 Oct 2025 22:20:28 -0700 (PDT) Received: from ergosum.cambridge.arm.com (ergosum.cambridge.arm.com [10.1.196.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D754D3F59E; Mon, 20 Oct 2025 22:20:34 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org Subject: [PATCH 2/2] arm64/mm: Add remaining TLBI_XXX_MASK macros Date: Tue, 21 Oct 2025 06:20:22 +0100 Message-Id: <20251021052022.2898275-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20251021052022.2898275-1-anshuman.khandual@arm.com> References: <20251021052022.2898275-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add remaining TLBI_XXX_MASK macros and replace current open encoded fields. While here replace hard coded page size based shifts but with derived ones via ilog2() thus adding some required context. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/tlbflush.h | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlb= flush.h index 131096094f5b..cf75fc2a06c3 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -57,9 +57,10 @@ /* This macro creates a properly formatted VA operand for the TLBI */ #define __TLBI_VADDR(addr, asid) \ ({ \ - unsigned long __ta =3D (addr) >> 12; \ - __ta &=3D GENMASK_ULL(43, 0); \ - __ta |=3D (unsigned long)(asid) << 48; \ + unsigned long __ta =3D (addr) >> ilog2(SZ_4K); \ + __ta &=3D TLBI_BADDR_MASK; \ + __ta &=3D ~TLBI_ASID_MASK; \ + __ta |=3D FIELD_PREP(TLBI_ASID_MASK, asid); \ __ta; \ }) =20 @@ -100,8 +101,17 @@ static inline unsigned long get_trans_granule(void) * * For Stage-2 invalidation, use the level values provided to that effect * in asm/stage2_pgtable.h. + * + * +----------+------+-------+--------------------------------------+ + * | ASID | TG | TTL | BADDR | + * +-----------------+-------+--------------------------------------+ + * |63 48|47 46|45 44|43 0| + * +----------+------+-------+--------------------------------------+ */ -#define TLBI_TTL_MASK GENMASK_ULL(47, 44) +#define TLBI_ASID_MASK GENMASK_ULL(63, 48) +#define TLBI_TG_MASK GENMASK_ULL(47, 46) +#define TLBI_TTL_MASK GENMASK_ULL(45, 44) +#define TLBI_BADDR_MASK GENMASK_ULL(43, 0) =20 #define TLBI_TTL_UNKNOWN INT_MAX =20 @@ -110,10 +120,10 @@ static inline unsigned long get_trans_granule(void) \ if (alternative_has_cap_unlikely(ARM64_HAS_ARMv8_4_TTL) && \ level >=3D 0 && level <=3D 3) { \ - u64 ttl =3D level; \ - ttl |=3D get_trans_granule() << 2; \ + arg &=3D ~TLBI_TG_MASK; \ + arg |=3D FIELD_PREP(TLBI_TG_MASK, get_trans_granule()); \ arg &=3D ~TLBI_TTL_MASK; \ - arg |=3D FIELD_PREP(TLBI_TTL_MASK, ttl); \ + arg |=3D FIELD_PREP(TLBI_TTL_MASK, level); \ } \ \ __tlbi(op, arg); \ @@ -383,7 +393,7 @@ do { \ typeof(pages) __flush_pages =3D pages; \ int num =3D 0; \ int scale =3D 3; \ - int shift =3D lpa2 ? 16 : PAGE_SHIFT; \ + int shift =3D lpa2 ? ilog2(SZ_64K) : PAGE_SHIFT; \ unsigned long addr; \ \ while (__flush_pages > 0) { \ --=20 2.30.2