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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b6a76673a86sm8855787a12.10.2025.10.20.19.59.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 19:59:41 -0700 (PDT) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, kernel@oss.qualcomm.com, mike.leach@linaro.org, suzuki.poulose@arm.com Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org Subject: [RESEND RFC PATCH 7/7] qcom-tgu: Add reset node to initialize Date: Mon, 20 Oct 2025 19:59:09 -0700 Message-Id: <20251021025909.3627254-8-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251021025909.3627254-1-songwei.chai@oss.qualcomm.com> References: <20251021025909.3627254-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAwMCBTYWx0ZWRfX72heVYsPuMQq w6tlWinNelRAprF7EawH6LGvSMXVP5u44L2S2/9ykvKrT7ewVLNFbE26YfsuSskHuu6f6PNmjDb xMphoaR4QkTAtdOpSrqLQTmvBCGgVujFgm4s930cb/bmzbUO/grm2o7a5hvFJCmaVEjy22mpI3P uDDcAUqNP5jFSUBSQTGvAI+BLd1uTuvCrrHEtgAbiiUzz5DK9rLR074pvDjGDloJZGutA55BdXn gCeuU4udLgvVq6V38brBsaQ/jsmarQr+2l1+Bo6hIE5dc47Ws9nP19/nwCrcFWSEXI5JHfV5Kw0 WTXlpabBkAv+nuo5dxEr3JHeNSzpSvY3401osK+HK7+iqC5sohxEj5U+RQLz+Kk+OR2JFbQIBPp LzZw/PHcsEA+chgnNm/mEkcfrX6f5A== X-Proofpoint-GUID: lsZxODvz7wIPjhF4F7-dWMngyoctj2Nl X-Authority-Analysis: v=2.4 cv=Up1u9uwB c=1 sm=1 tr=0 ts=68f6f71f cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=IgPCHI2mAnvcCQI4J_AA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: lsZxODvz7wIPjhF4F7-dWMngyoctj2Nl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-20_07,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 suspectscore=0 malwarescore=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180000 Content-Type: text/plain; charset="utf-8" Add reset node to initialize the value of priority/condition_decode/condition_select/timer/counter nodes. Signed-off-by: Songwei Chai --- .../testing/sysfs-bus-coresight-devices-tgu | 7 ++ drivers/hwtracing/qcom/tgu.c | 75 +++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu b/Do= cumentation/ABI/testing/sysfs-bus-coresight-devices-tgu index a57bf9783641..c9e12b298b23 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu @@ -42,3 +42,10 @@ KernelVersion 6.18 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the counter value with specific step for TGU. + +What: /sys/bus/coresight/devices//reset_tgu +Date: October 2025 +KernelVersion 6.18 +Contact: Jinlong Mao , Songwei Chai +Description: + (Write) Write 1 to reset the dataset for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index c4ae1f27d9ff..9bef9d8b4690 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -434,6 +434,80 @@ static ssize_t enable_tgu_store(struct device *dev, } static DEVICE_ATTR_RW(enable_tgu); =20 +/* reset_tgu_store - Reset Trace and Gating Unit (TGU) configuration. */ +static ssize_t reset_tgu_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t size) +{ + unsigned long value; + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + int i, j, ret; + + if (kstrtoul(buf, 0, &value) || value =3D=3D 0) + return -EINVAL; + + if (!drvdata->enable) { + ret =3D pm_runtime_get_sync(drvdata->dev); + if (ret < 0) { + pm_runtime_put(drvdata->dev); + return ret; + } + } + + spin_lock(&drvdata->spinlock); + CS_UNLOCK(drvdata->base); + + writel(0, drvdata->base + TGU_CONTROL); + + if (drvdata->value_table->priority) + memset(drvdata->value_table->priority, 0, + MAX_PRIORITY * drvdata->max_step * + drvdata->max_reg * sizeof(unsigned int)); + + if (drvdata->value_table->condition_decode) + memset(drvdata->value_table->condition_decode, 0, + drvdata->max_condition_decode * drvdata->max_step * + sizeof(unsigned int)); + + /* Initialize all condition registers to NOT(value=3D0x1000000) */ + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_condition_decode; j++) { + drvdata->value_table + ->condition_decode[calculate_array_location( + drvdata, i, TGU_CONDITION_DECODE, j)] =3D + 0x1000000; + } + } + + if (drvdata->value_table->condition_select) + memset(drvdata->value_table->condition_select, 0, + drvdata->max_condition_select * drvdata->max_step * + sizeof(unsigned int)); + + if (drvdata->value_table->timer) + memset(drvdata->value_table->timer, 0, + (drvdata->max_step) * + (drvdata->max_timer) * + sizeof(unsigned int)); + + if (drvdata->value_table->counter) + memset(drvdata->value_table->counter, 0, + (drvdata->max_step) * + (drvdata->max_counter) * + sizeof(unsigned int)); + + dev_dbg(dev, "Coresight-TGU reset complete\n"); + + CS_LOCK(drvdata->base); + + drvdata->enable =3D false; + spin_unlock(&drvdata->spinlock); + pm_runtime_put(drvdata->dev); + + return size; +} +static DEVICE_ATTR_WO(reset_tgu); + static const struct coresight_ops_helper tgu_helper_ops =3D { .enable =3D tgu_enable, .disable =3D tgu_disable, @@ -445,6 +519,7 @@ static const struct coresight_ops tgu_ops =3D { =20 static struct attribute *tgu_common_attrs[] =3D { &dev_attr_enable_tgu.attr, + &dev_attr_reset_tgu.attr, NULL, };