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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b6a76673a86sm8855787a12.10.2025.10.20.19.59.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 19:59:37 -0700 (PDT) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, kernel@oss.qualcomm.com, mike.leach@linaro.org, suzuki.poulose@arm.com Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org Subject: [RESEND RFC PATCH 5/7] qcom-tgu: Add support to configure next action Date: Mon, 20 Oct 2025 19:59:07 -0700 Message-Id: <20251021025909.3627254-6-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251021025909.3627254-1-songwei.chai@oss.qualcomm.com> References: <20251021025909.3627254-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAyMCBTYWx0ZWRfXxy8exK/h4mj2 dj/YEe3Oz/tkkIMoitOjIVmijBB2Ntp7fpWiflPecwrmrvF1YFevqRsmyQU3e+OR1TS0McWBrW+ bZfP4ru+ZuR2oYG4mOtTW6Dq97TGg+zzF4WklTvwl0+rl1SI1QNc1Hz7/mkMnnPTXzSMkjiUMp6 wE8cJp1ru01hm/ewGF8OUxI201WW+9KvRlf1Lk+JkvduwwS9SKur01+X/VcwamHZwMxEroxgZUA Q3f5RgmhBAAdra9qNlR6+YoIGvZyZgjm1YQyrx5Nbi9j8LluHju99WHKKOvvSByLHHrhGNSf9aa liYCSxbW0/J1D3/2+95YWgWlwTekF8I6rZiBlNa/gPkuzKAlQtIQtrx1tz3oNg8pPcr/6qQF5HF 2jY03NT8j/mcQHdf4CmrU8NPg+N9vA== X-Authority-Analysis: v=2.4 cv=KqFAGGWN c=1 sm=1 tr=0 ts=68f6f71b cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=xi9iTe-FYOb_EUe3slkA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: 8tB0IeVJJ_gHjEj-oODUm_5-1SmdfEfi X-Proofpoint-ORIG-GUID: 8tB0IeVJJ_gHjEj-oODUm_5-1SmdfEfi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-20_07,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 phishscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180020 Content-Type: text/plain; charset="utf-8" Add "select" node for each step to determine if another step is taken, trigger(s) are generated, counters/timers incremented/decremented, etc. Signed-off-by: Songwei Chai --- .../testing/sysfs-bus-coresight-devices-tgu | 7 +++ drivers/hwtracing/qcom/tgu.c | 52 +++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 27 ++++++++++ 3 files changed, 86 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu b/Do= cumentation/ABI/testing/sysfs-bus-coresight-devices-tgu index 5034df7d52a4..ea05b1b3301d 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu @@ -21,3 +21,10 @@ KernelVersion 6.18 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the decode mode with specific step for TGU. + +What: /sys/bus/coresight/devices//step[0:7]_condition_select/re= g[0:3] +Date: October 2025 +KernelVersion 6.18 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the next action with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index 70675e19176b..ccb1144e7562 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -36,6 +36,10 @@ static int calculate_array_location(struct tgu_drvdata *= drvdata, ret =3D step_index * (drvdata->max_condition_decode) + reg_index; break; + case TGU_CONDITION_SELECT: + ret =3D step_index * (drvdata->max_condition_select) + + reg_index; + break; default: break; } @@ -81,6 +85,9 @@ static ssize_t tgu_dataset_show(struct device *dev, case TGU_CONDITION_DECODE: return sysfs_emit(buf, "0x%x\n", drvdata->value_table->condition_decode[index]); + case TGU_CONDITION_SELECT: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->condition_select[index]); default: break; } @@ -122,6 +129,10 @@ static ssize_t tgu_dataset_store(struct device *dev, tgu_drvdata->value_table->condition_decode[index] =3D val; ret =3D size; break; + case TGU_CONDITION_SELECT: + tgu_drvdata->value_table->condition_select[index] =3D val; + ret =3D size; + break; default: break; } @@ -155,6 +166,15 @@ static umode_t tgu_node_visible(struct kobject *kobjec= t, drvdata->max_condition_decode) ? attr->mode : 0; break; + case TGU_CONDITION_SELECT: + /* 'default' register is at the end of 'select' region */ + if (tgu_attr->reg_num =3D=3D + drvdata->max_condition_select - 1) + attr->name =3D "default"; + ret =3D (tgu_attr->reg_num < + drvdata->max_condition_select) ? + attr->mode : 0; + break; default: break; } @@ -193,6 +213,19 @@ static ssize_t tgu_write_all_hw_regs(struct tgu_drvdat= a *drvdata) drvdata->base + CONDITION_DECODE_STEP(i, j)); } } + + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_condition_select; j++) { + index =3D check_array_location(drvdata, i, + TGU_CONDITION_SELECT, j); + + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->condition_select[index], + drvdata->base + CONDITION_SELECT_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); exit: @@ -231,6 +264,8 @@ static void tgu_set_conditions(struct tgu_drvdata *drvd= ata) =20 devid =3D readl(drvdata->base + CORESIGHT_DEVID); drvdata->max_condition_decode =3D TGU_DEVID_CONDITIONS(devid); + /* select region has an additional 'default' register */ + drvdata->max_condition_select =3D TGU_DEVID_CONDITIONS(devid) + 1; } =20 static int tgu_enable(struct coresight_device *csdev, enum cs_mode mode, @@ -375,6 +410,14 @@ static const struct attribute_group *tgu_attr_groups[]= =3D { CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(5), CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(6), CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(7), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(0), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(1), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(2), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(3), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(4), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(5), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(6), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(7), NULL, }; =20 @@ -436,6 +479,15 @@ static int tgu_probe(struct amba_device *adev, const s= truct amba_id *id) if (!drvdata->value_table->condition_decode) return -ENOMEM; =20 + drvdata->value_table->condition_select =3D devm_kzalloc( + dev, + drvdata->max_condition_select * drvdata->max_step * + sizeof(*(drvdata->value_table->condition_select)), + GFP_KERNEL); + + if (!drvdata->value_table->condition_select) + return -ENOMEM; + drvdata->enable =3D false; desc.type =3D CORESIGHT_DEV_TYPE_HELPER; desc.pdata =3D adev->dev.platform_data; diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index 3974d8e6ab04..ced10b3daaa2 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -46,6 +46,7 @@ #define STEP_OFFSET 0x1D8 #define PRIORITY_START_OFFSET 0x0074 #define CONDITION_DECODE_OFFSET 0x0050 +#define CONDITION_SELECT_OFFSET 0x0060 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 =20 @@ -57,6 +58,9 @@ #define CONDITION_DECODE_STEP(step, decode) \ (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step) =20 +#define CONDITION_SELECT_STEP(step, select) \ + (CONDITION_SELECT_OFFSET + REG_OFFSET * select + STEP_OFFSET * step) + #define tgu_dataset_rw(name, step_index, type, reg_num) \ (&((struct tgu_attribute[]){ { \ __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ @@ -72,6 +76,9 @@ #define STEP_DECODE(step_index, reg_num) \ tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_DECODE, reg_num) =20 +#define STEP_SELECT(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_SELECT, reg_num) + #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ STEP_PRIORITY(step_index, 1, priority), \ @@ -102,6 +109,15 @@ NULL \ } =20 +#define STEP_SELECT_LIST(n) \ + {STEP_SELECT(n, 0), \ + STEP_SELECT(n, 1), \ + STEP_SELECT(n, 2), \ + STEP_SELECT(n, 3), \ + STEP_SELECT(n, 4), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -116,12 +132,20 @@ .name =3D "step" #step "_condition_decode" \ }) =20 +#define CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_SELECT_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_condition_select" \ + }) + enum operation_index { TGU_PRIORITY0, TGU_PRIORITY1, TGU_PRIORITY2, TGU_PRIORITY3, TGU_CONDITION_DECODE, + TGU_CONDITION_SELECT, }; =20 /* Maximum priority that TGU supports */ @@ -137,6 +161,7 @@ struct tgu_attribute { struct value_table { unsigned int *priority; unsigned int *condition_decode; + unsigned int *condition_select; }; =20 /** @@ -150,6 +175,7 @@ struct value_table { * @max_reg: Maximum number of registers * @max_step: Maximum step size * @max_condition_decode: Maximum number of condition_decode + * @max_condition_select: Maximum number of condition_select * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -166,6 +192,7 @@ struct tgu_drvdata { int max_reg; int max_step; int max_condition_decode; + int max_condition_select; }; =20 #endif