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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b6a76673a86sm8855787a12.10.2025.10.20.19.59.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 19:59:29 -0700 (PDT) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, kernel@oss.qualcomm.com, mike.leach@linaro.org, suzuki.poulose@arm.com Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org Subject: [RESEND RFC PATCH 2/7] qcom-tgu: Add TGU driver Date: Mon, 20 Oct 2025 19:59:04 -0700 Message-Id: <20251021025909.3627254-3-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251021025909.3627254-1-songwei.chai@oss.qualcomm.com> References: <20251021025909.3627254-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAxNSBTYWx0ZWRfX+h2rfKJ88YUo agwR7wzSxBe1wxTvJY/5pz0ALLMzKoTtOT/ps89pqgKte8+cUXhMDh4TG440YM5xiZbrLfYBDbj 0Vx4i+isZ0SfyXWpEMd6IGraebf+n/poCOEAmOExGvz45SkkCQ0ZjDs9E+5Lg6NIwQjUCrDVt72 7Fag8bf4u7x2kwst2gqStFxCEsZAnqJ1OqWKZ6W+GybQOkweforRaeLMTxzlFTjnbYm0MmtCfLX ltLiu7Y+91kT7Dpzypwm4mN4IUXF7hbKLUNVsGN0VEcq+Wfqi/zsCdhQT2Fdk4Qtn0YBYcdkctF N49HDyxGR3+Rp1vydhHj7cQpTqCu+yR+0teRw+KU9a1Bn9EVIe956/LFM3EEES/NdVrql044+CX XXY2URb+t6yQZeA0mXPglZ5tyAtS4g== X-Authority-Analysis: v=2.4 cv=bNUb4f+Z c=1 sm=1 tr=0 ts=68f6f714 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=h99DN6MNysFgGb7_OMAA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: F6C6ojdaoLVLnnj7oMZacmUUg1aPYnDj X-Proofpoint-ORIG-GUID: F6C6ojdaoLVLnnj7oMZacmUUg1aPYnDj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-20_07,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1011 priorityscore=1501 suspectscore=0 adultscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180015 Content-Type: text/plain; charset="utf-8" Add driver to support device TGU (Trigger Generation Unit). TGU is a Data Engine which can be utilized to sense a plurality of signals and create a trigger into the CTI or generate interrupts to processors. Add probe/enable/disable functions for tgu. Signed-off-by: Songwei Chai --- .../testing/sysfs-bus-coresight-devices-tgu | 9 + drivers/Makefile | 1 + drivers/hwtracing/Kconfig | 2 + drivers/hwtracing/qcom/Kconfig | 18 ++ drivers/hwtracing/qcom/Makefile | 3 + drivers/hwtracing/qcom/tgu.c | 210 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 33 +++ 7 files changed, 276 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-t= gu create mode 100644 drivers/hwtracing/qcom/Kconfig create mode 100644 drivers/hwtracing/qcom/Makefile create mode 100644 drivers/hwtracing/qcom/tgu.c create mode 100644 drivers/hwtracing/qcom/tgu.h diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu b/Do= cumentation/ABI/testing/sysfs-bus-coresight-devices-tgu new file mode 100644 index 000000000000..353961e7b61c --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu @@ -0,0 +1,9 @@ +What: /sys/bus/coresight/devices//enable_tgu +Date: October 2025 +KernelVersion 6.18 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the enable/disable status of TGU + Accepts only one of the 2 values - 0 or 1. + 0 : disable TGU. + 1 : enable TGU. diff --git a/drivers/Makefile b/drivers/Makefile index 8e1ffa4358d5..acade03f5942 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -176,6 +176,7 @@ obj-$(CONFIG_RAS) +=3D ras/ obj-$(CONFIG_USB4) +=3D thunderbolt/ obj-$(CONFIG_CORESIGHT) +=3D hwtracing/coresight/ obj-y +=3D hwtracing/intel_th/ +obj-y +=3D hwtracing/qcom/ obj-$(CONFIG_STM) +=3D hwtracing/stm/ obj-$(CONFIG_HISI_PTT) +=3D hwtracing/ptt/ obj-y +=3D android/ diff --git a/drivers/hwtracing/Kconfig b/drivers/hwtracing/Kconfig index 911ee977103c..8a640218eed8 100644 --- a/drivers/hwtracing/Kconfig +++ b/drivers/hwtracing/Kconfig @@ -7,4 +7,6 @@ source "drivers/hwtracing/intel_th/Kconfig" =20 source "drivers/hwtracing/ptt/Kconfig" =20 +source "drivers/hwtracing/qcom/Kconfig" + endmenu diff --git a/drivers/hwtracing/qcom/Kconfig b/drivers/hwtracing/qcom/Kconfig new file mode 100644 index 000000000000..d6f6d4b0f28e --- /dev/null +++ b/drivers/hwtracing/qcom/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# QCOM specific hwtracing drivers +# +menu "Qualcomm specific hwtracing drivers" + +config QCOM_TGU + tristate "QCOM Trigger Generation Unit driver" + help + This driver provides support for Trigger Generation Unit that is + used to detect patterns or sequences on a given set of signals. + TGU is used to monitor a particular bus within a given region to + detect illegal transaction sequences or slave responses. It is also + used to monitor a data stream to detect protocol violations and to + provide a trigger point for centering data around a specific event + within the trace data buffer. + +endmenu diff --git a/drivers/hwtracing/qcom/Makefile b/drivers/hwtracing/qcom/Makef= ile new file mode 100644 index 000000000000..5a0a868c1ea0 --- /dev/null +++ b/drivers/hwtracing/qcom/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_QCOM_TGU) +=3D tgu.o diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c new file mode 100644 index 000000000000..0d3c62f2d5e6 --- /dev/null +++ b/drivers/hwtracing/qcom/tgu.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../coresight/coresight-priv.h" +#include "tgu.h" + +DEFINE_CORESIGHT_DEVLIST(tgu_devs, "tgu"); + +static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + /* Enable TGU to program the triggers */ + writel(1, drvdata->base + TGU_CONTROL); + CS_LOCK(drvdata->base); +} + +static int tgu_enable(struct coresight_device *csdev, enum cs_mode mode, + void *data) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + guard(spinlock)(&drvdata->spinlock); + if (drvdata->enable) + return -EBUSY; + + tgu_write_all_hw_regs(drvdata); + drvdata->enable =3D true; + + return 0; +} + +static int tgu_disable(struct coresight_device *csdev, void *data) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (drvdata->enable) { + CS_UNLOCK(drvdata->base); + writel(0, drvdata->base + TGU_CONTROL); + CS_LOCK(drvdata->base); + + drvdata->enable =3D false; + } + spin_unlock(&drvdata->spinlock); + return 0; +} + +static ssize_t enable_tgu_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + bool enabled; + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + enabled =3D drvdata->enable; + spin_unlock(&drvdata->spinlock); + + return sysfs_emit(buf, "%d\n", enabled); +} + +/* enable_tgu_store - Configure Trace and Gating Unit (TGU) triggers. */ +static ssize_t enable_tgu_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + int ret =3D 0; + unsigned long val; + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + ret =3D kstrtoul(buf, 0, &val); + if (ret) + return ret; + + if (val) { + ret =3D pm_runtime_resume_and_get(dev->parent); + if (ret) + return ret; + ret =3D tgu_enable(drvdata->csdev, CS_MODE_SYSFS, NULL); + if (ret) + pm_runtime_put(dev->parent); + } else { + ret =3D tgu_disable(drvdata->csdev, NULL); + pm_runtime_put(dev->parent); + } + + if (ret) + return ret; + return size; +} +static DEVICE_ATTR_RW(enable_tgu); + +static const struct coresight_ops_helper tgu_helper_ops =3D { + .enable =3D tgu_enable, + .disable =3D tgu_disable, +}; + +static const struct coresight_ops tgu_ops =3D { + .helper_ops =3D &tgu_helper_ops, +}; + +static struct attribute *tgu_common_attrs[] =3D { + &dev_attr_enable_tgu.attr, + NULL, +}; + +static const struct attribute_group tgu_common_grp =3D { + .attrs =3D tgu_common_attrs, + NULL, +}; + +static const struct attribute_group *tgu_attr_groups[] =3D { + &tgu_common_grp, + NULL, +}; + +static int tgu_probe(struct amba_device *adev, const struct amba_id *id) +{ + int ret =3D 0; + struct device *dev =3D &adev->dev; + struct coresight_desc desc =3D { 0 }; + struct coresight_platform_data *pdata; + struct tgu_drvdata *drvdata; + + desc.name =3D coresight_alloc_device_name(&tgu_devs, dev); + if (!desc.name) + return -ENOMEM; + + pdata =3D coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + + adev->dev.platform_data =3D pdata; + + drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev =3D &adev->dev; + dev_set_drvdata(dev, drvdata); + + drvdata->base =3D devm_ioremap_resource(dev, &adev->res); + if (!drvdata->base) + return -ENOMEM; + + spin_lock_init(&drvdata->spinlock); + + drvdata->enable =3D false; + desc.type =3D CORESIGHT_DEV_TYPE_HELPER; + desc.pdata =3D adev->dev.platform_data; + desc.dev =3D &adev->dev; + desc.ops =3D &tgu_ops; + desc.groups =3D tgu_attr_groups; + + drvdata->csdev =3D coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) { + ret =3D PTR_ERR(drvdata->csdev); + goto err; + } + + pm_runtime_put(&adev->dev); + return 0; +err: + pm_runtime_put(&adev->dev); + return ret; +} + +static void tgu_remove(struct amba_device *adev) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); +} + +static const struct amba_id tgu_ids[] =3D { + { + .id =3D 0x000f0e00, + .mask =3D 0x000fffff, + .data =3D "TGU", + }, + { 0, 0, NULL }, +}; + +MODULE_DEVICE_TABLE(amba, tgu_ids); + +static struct amba_driver tgu_driver =3D { + .drv =3D { + .name =3D "qcom-tgu", + .suppress_bind_attrs =3D true, + }, + .probe =3D tgu_probe, + .remove =3D tgu_remove, + .id_table =3D tgu_ids, +}; + +module_amba_driver(tgu_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm TGU driver"); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h new file mode 100644 index 000000000000..b60ac0f3bda1 --- /dev/null +++ b/drivers/hwtracing/qcom/tgu.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#ifndef _QCOM_TGU_H +#define _QCOM_TGU_H + +/* Register addresses */ +#define TGU_CONTROL 0x0000 + +/** + * struct tgu_drvdata - Data structure for a TGU (Trigger Generator Unit) + * @base: Memory-mapped base address of the TGU device + * @dev: Pointer to the associated device structure + * @csdev: Pointer to the associated coresight device + * @spinlock: Spinlock for handling concurrent access + * @enable: Flag indicating whether the TGU device is enabled + * + * This structure defines the data associated with a TGU device, + * including its base address, device pointers, clock, spinlock for + * synchronization, trigger data pointers, maximum limits for various + * trigger-related parameters, and enable status. + */ +struct tgu_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + spinlock_t spinlock; + bool enable; +}; + +#endif