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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2025 01:45:31.5536 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36b9ccd5-0a0c-4178-e68c-08de10438526 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B072.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPF634736581 Content-Type: text/plain; charset="utf-8" Introduce the set_dte_v1() helper function to configure IOMMU host (v1) page table into DTE. There is no functional change. Suggested-by: Jason Gunthorpe Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 3 ++ drivers/iommu/amd/iommu.c | 57 ++++++++++++++++++++--------------- 2 files changed, 35 insertions(+), 25 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index cfb63de7732a..5e61fdb2c6c0 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -190,6 +190,9 @@ struct iommu_dev_data *search_dev_data(struct amd_iommu= *iommu, u16 devid); int amd_iommu_completion_wait(struct amd_iommu *iommu); =20 /* DTE */ +void amd_iommu_set_dte_v1(struct iommu_dev_data *dev_data, + struct protection_domain *domain, + struct dev_table_entry *new); int amd_iommu_device_flush_dte(struct iommu_dev_data *dev_data); void amd_iommu_update_dte256(struct amd_iommu *iommu, struct iommu_dev_data *dev_data, diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index e3330f3b8c14..428008cff06a 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2041,16 +2041,12 @@ int amd_iommu_clear_gcr3(struct iommu_dev_data *dev= _data, ioasid_t pasid) * Note: * The old value for GCR3 table and GPT have been cleared from caller. */ -static void set_dte_gcr3_table(struct amd_iommu *iommu, - struct iommu_dev_data *dev_data, +static void set_dte_gcr3_table(struct iommu_dev_data *dev_data, struct dev_table_entry *target) { struct gcr3_tbl_info *gcr3_info =3D &dev_data->gcr3_info; u64 gcr3; =20 - if (!gcr3_info->gcr3_tbl) - return; - pr_debug("%s: devid=3D%#x, glx=3D%#x, gcr3_tbl=3D%#llx\n", __func__, dev_data->devid, gcr3_info->glx, (unsigned long long)gcr3_info->gcr3_tbl); @@ -2071,6 +2067,26 @@ static void set_dte_gcr3_table(struct amd_iommu *iom= mu, target->data[2] |=3D FIELD_PREP(DTE_GPT_LEVEL_MASK, GUEST_PGTABLE_5_LEVE= L); else target->data[2] |=3D FIELD_PREP(DTE_GPT_LEVEL_MASK, GUEST_PGTABLE_4_LEVE= L); + + /* Note: PRI is only supported w/ GCR3 table */ + if (dev_data->ppr) + target->data[0] |=3D 1ULL << DEV_ENTRY_PPR; +} + +void amd_iommu_set_dte_v1(struct iommu_dev_data *dev_data, + struct protection_domain *domain, + struct dev_table_entry *new) +{ + u64 htrp; + + new->data[0] |=3D FIELD_PREP(DTE_MODE_MASK, domain->iop.mode); + + htrp =3D FIELD_GET(GENMASK_ULL(51, 12), iommu_virt_to_phys(domain->iop.ro= ot)); + new->data[0] |=3D FIELD_PREP(DTE_HOST_TRP, htrp); + + /* Note Dirty tracking is used for v1 table only for now */ + if (domain->dirty_tracking) + new->data[0] |=3D DTE_FLAG_HAD; } =20 static void set_dte_entry(struct amd_iommu *iommu, @@ -2088,37 +2104,28 @@ static void set_dte_entry(struct amd_iommu *iommu, else domid =3D domain->id; =20 - amd_iommu_make_clear_dte(dev_data, &new); - - if (domain->iop.mode !=3D PAGE_MODE_NONE) - new.data[0] |=3D iommu_virt_to_phys(domain->iop.root); - - new.data[0] |=3D (domain->iop.mode & DEV_ENTRY_MODE_MASK) - << DEV_ENTRY_MODE_SHIFT; - - new.data[0] |=3D DTE_FLAG_IR | DTE_FLAG_IW; - /* * When SNP is enabled, we can only support TV=3D1 with non-zero domain I= D. * This is prevented by the SNP-enable and IOMMU_DOMAIN_IDENTITY check in * do_iommu_domain_alloc(). */ WARN_ON(amd_iommu_snp_en && (domid =3D=3D 0)); - new.data[0] |=3D DTE_FLAG_TV; =20 - if (dev_data->ppr) - new.data[0] |=3D 1ULL << DEV_ENTRY_PPR; + amd_iommu_make_clear_dte(dev_data, &new); =20 - if (domain->dirty_tracking) - new.data[0] |=3D DTE_FLAG_HAD; + old_domid =3D READ_ONCE(dte->data[1]) & DTE_DOMID_MASK; =20 - if (dev_data->ats_enabled) - new.data[1] |=3D DTE_FLAG_IOTLB; + if (gcr3_info && gcr3_info->gcr3_tbl) + set_dte_gcr3_table(dev_data, &new); + else if (domain->iop.mode !=3D PAGE_MODE_NONE) + amd_iommu_set_dte_v1(dev_data, domain, &new); =20 - old_domid =3D READ_ONCE(dte->data[1]) & DTE_DOMID_MASK; - new.data[1] |=3D domid; + /* Note: The IR, IW, TV, DOMID are needed for both v1 and gcr3 table */ + new.data[0] |=3D DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_TV; + new.data[1] |=3D FIELD_PREP(DTE_DOMID_MASK, domid); =20 - set_dte_gcr3_table(iommu, dev_data, &new); + if (dev_data->ats_enabled) + new.data[1] |=3D DTE_FLAG_IOTLB; =20 amd_iommu_update_dte256(iommu, dev_data, &new); =20 --=20 2.34.1