From nobody Mon Feb 9 01:06:50 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 923643370F5 for ; Tue, 21 Oct 2025 13:23:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761053019; cv=none; b=HM01EuA6MEof7z8LhzgMmcF9/IblVH+1o3sLtXLY70yw2Yg9g9F0h99Y9+W4OowBAJrQqgPp4GeQv1zatNUZFHS20x/Z9wPWC4YYMtHykUZrs8T2iFmSSkQxnGvs1KblkXmDdVqmI0XY8qVDWcE51BfcLTFOzpHgeGZs66oAW0E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761053019; c=relaxed/simple; bh=nWvFAvD5AGlGEC9yWkEHzmj/BzvIaks9Klnp2gFRims=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=deRiBPoT+ZuYbHvvbGqioaTyvJ+XoxEdJQDKIGcH2kKo3+Dk9vgpDTR/SDq9I2cFZ0RstYENkG+rOBEkSr6HxgK9xSNgR+IVtAiz1OI3avh8XduK7FOLh7EWZbEdnOBnAQkvcjqZfBZcYcko03vsjOdwuIo/2TkGt+LK0DgvpE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=SEc0ncK/; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="SEc0ncK/" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id D6202E01; Tue, 21 Oct 2025 15:21:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1761052907; bh=nWvFAvD5AGlGEC9yWkEHzmj/BzvIaks9Klnp2gFRims=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SEc0ncK/Px7LHKPRC5HjahiOZMnp2UOUsW1WNPFmHW1eOin2P5o28QPCwJsRAaHqr B5aCJ7cjBUSvuE+mtNxrmIc6L7YAS526nAz+PTtdVO4W1Xn8WNK5gycqOrv+4lRz/c uReVOVDZuMGzuYczMpkh8G0DCs7VADVlLpHNX4Dw= From: Tomi Valkeinen Date: Tue, 21 Oct 2025 16:22:57 +0300 Subject: [PATCH 1/7] drm/bridge: tc358768: Fix typo in TC358768_DSI_CONTROL_DIS_MODE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-tc358768-v1-1-d590dc6a1a0c@ideasonboard.com> References: <20251021-tc358768-v1-0-d590dc6a1a0c@ideasonboard.com> In-Reply-To: <20251021-tc358768-v1-0-d590dc6a1a0c@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Parth Pancholi , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1173; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=nWvFAvD5AGlGEC9yWkEHzmj/BzvIaks9Klnp2gFRims=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBo94lOIXJCeonjgsKVvaBnTwx2Cc0C7I40fThUk XMNkOKzkhiJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCaPeJTgAKCRD6PaqMvJYe 9dHzD/97oSLT/UXJrVYdPSI3Hoaoe61ujacfWK8E3/xKu5I2sKN0Ib6VhaqUZU6h30ci5UqsVEl 9aULxfmlH3zWv0pHfW41M5TNL70/gpmUw4NS/Oh9cfrs5JiKwZbiFdtLcuUD1gCKSPwhmBEDKsm ps95iHNUtcsvqp5G0srxD3zEZD0Qg28h187PDiO0AjHCL1kRKlm5Pu/t4cDmuBf5GMVln2DB71V /Jof5V5YouGa7WyFCtUqHYq3tDAduljJMzio5Zd+IYFE0jR3wXf40lO/Lp1mMAbly4aKfDvmY4C 2ji43XpGvmYTzYI3OlA3+wj7eULBEGH9uuQaOCVGLOA1mbj967ZNJ0pJa5bNMf2WQuCGhItxH8j xD4SDAUor5ALJay+xuLuu02XWyeAdPQW2SiQB9qqwk8B2Om22WmcYlOsFNTZGyU9ZqVCNd6SegB SeiZxwVeQLP58+Ar+au4H6gKUPG6307oJ++/yukmlxNNq9VGTtyaouX5Ngz24/rO1mJgAR9crpR H6hkBjkZBPrvUOjYwpFq3Mc5XKpOAHBjnVczYYSV3XC2fMHOOIXQcvubXmhMKc28oFJERtUFQcz rICQY6btAQMUZdXf03jHvUQLmlqU+DCgukv7P7yNX2GdwRXNxR+ZbookwZbHmUX5aExuwGdE+Od tZErzWCg7TCbrjA== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 It's "DSI_MODE", not "DIS_MODE". Signed-off-by: Tomi Valkeinen Reviewed-by: Francesco Dolcini Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 --- drivers/gpu/drm/bridge/tc358768.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index fbdc44e16229..c95d164bd3a0 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -115,7 +115,7 @@ #define TC358768_DSI_HACT 0x062C =20 /* TC358768_DSI_CONTROL (0x040C) register */ -#define TC358768_DSI_CONTROL_DIS_MODE BIT(15) +#define TC358768_DSI_CONTROL_DSI_MODE BIT(15) #define TC358768_DSI_CONTROL_TXMD BIT(7) #define TC358768_DSI_CONTROL_HSCKMD BIT(5) #define TC358768_DSI_CONTROL_EOTDIS BIT(0) @@ -1082,7 +1082,7 @@ static void tc358768_bridge_atomic_pre_enable(struct = drm_bridge *bridge, tc358768_write(priv, TC358768_DSI_CONFW, val); =20 val =3D TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; - val |=3D TC358768_DSI_CONTROL_DIS_MODE; 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Tue, 21 Oct 2025 15:21:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1761052908; bh=dH31mK/qVs+VbRMYQArF1ov23OSFhjFl1Q1EyISUIjA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Z3mUP3tDnZx1pupv/dYu/vk2kXUaOUhfEw+KBKy4ziVLfoFZKKcoWk57ob9bHKwuX ZeNqRL7J/m7scPlgMzFM2md3vKXLq4Uo6v8PnGRsynog01Ym/bWcIC21o+YPKFOP7k z9DQQAWNXXoZ/yYV6+WmK1aboagVKR5AWdewP5Bc= From: Tomi Valkeinen Date: Tue, 21 Oct 2025 16:22:58 +0300 Subject: [PATCH 2/7] drm/bridge: tc358768: Set pre_enable_prev_first for reverse order Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-tc358768-v1-2-d590dc6a1a0c@ideasonboard.com> References: <20251021-tc358768-v1-0-d590dc6a1a0c@ideasonboard.com> In-Reply-To: <20251021-tc358768-v1-0-d590dc6a1a0c@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Parth Pancholi , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 From: Parth Pancholi Enable the pre_enable_prev_first flag on the tc358768 bridge to reverse the pre-enable order, calling bridge pre_enable before panel prepare. This ensures the bridge is ready before sending panel init commands in the case of panels sending init commands in panel prepare function. Signed-off-by: Parth Pancholi Signed-off-by: Tomi Valkeinen Reviewed-by: Francesco Dolcini Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 --- drivers/gpu/drm/bridge/tc358768.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index c95d164bd3a0..dab9cdf5cb98 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -448,6 +448,8 @@ static int tc358768_dsi_host_attach(struct mipi_dsi_hos= t *host, DRM_MODE_CONNECTOR_DSI); if (IS_ERR(bridge)) return PTR_ERR(bridge); + + bridge->pre_enable_prev_first =3D true; } =20 priv->output.dev =3D dev; --=20 2.43.0 From nobody Mon Feb 9 01:06:50 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD77B337B86 for ; Tue, 21 Oct 2025 13:23:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Some registers can only be written indirectly, using DSI_CONFW register. We don't have many uses for those registers (in fact, only DSI_CONTROL is currently written), but the code to do those writes inline is a bit confusing. Add a new function, tc358768_confw_update_bits() which can be used to write the bits indirectly. Only DSI_CONTROL is currently supported. Signed-off-by: Tomi Valkeinen Reviewed-by: Francesco Dolcini Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 --- drivers/gpu/drm/bridge/tc358768.c | 52 +++++++++++++++++++++++++++++------= ---- 1 file changed, 39 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index dab9cdf5cb98..755ed6483b2e 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -123,7 +123,7 @@ /* TC358768_DSI_CONFW (0x0500) register */ #define TC358768_DSI_CONFW_MODE_SET (5 << 29) #define TC358768_DSI_CONFW_MODE_CLR (6 << 29) -#define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24) +#define TC358768_DSI_CONFW_ADDR(x) ((x) << 24) =20 /* TC358768_DSICMD_TX (0x0600) register */ #define TC358768_DSI_CMDTX_DC_START BIT(0) @@ -232,6 +232,36 @@ static void tc358768_update_bits(struct tc358768_priv = *priv, u32 reg, u32 mask, tc358768_write(priv, reg, tmp); } =20 +static void tc358768_confw_update_bits(struct tc358768_priv *priv, u16 reg, + u16 mask, u16 val) +{ + u8 confw_addr; + u32 confw_val; + + switch (reg) { + case TC358768_DSI_CONTROL: + confw_addr =3D 0x3; + break; + default: + priv->error =3D -EINVAL; + return; + } + + if (mask !=3D val) { + confw_val =3D TC358768_DSI_CONFW_MODE_CLR | + TC358768_DSI_CONFW_ADDR(confw_addr) | + mask; + tc358768_write(priv, TC358768_DSI_CONFW, confw_val); + } + + if (val & mask) { + confw_val =3D TC358768_DSI_CONFW_MODE_SET | + TC358768_DSI_CONFW_ADDR(confw_addr) | + (val & mask); + tc358768_write(priv, TC358768_DSI_CONFW, confw_val); + } +} + static void tc358768_dsicmd_tx(struct tc358768_priv *priv) { u32 val; @@ -693,7 +723,7 @@ static void tc358768_bridge_atomic_pre_enable(struct dr= m_bridge *bridge, struct tc358768_priv *priv =3D bridge_to_tc358768(bridge); struct mipi_dsi_device *dsi_dev =3D priv->output.dev; unsigned long mode_flags =3D dsi_dev->mode_flags; - u32 val, val2, lptxcnt, hact, data_type; + u32 val, mask, val2, lptxcnt, hact, data_type; s32 raw_val; struct drm_crtc_state *crtc_state; struct drm_connector_state *conn_state; @@ -1065,13 +1095,7 @@ static void tc358768_bridge_atomic_pre_enable(struct= drm_bridge *bridge, tc358768_write(priv, TC358768_DSI_START, 0x1); =20 /* Configure DSI_Control register */ - val =3D TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; - val |=3D TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | - 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; - tc358768_write(priv, TC358768_DSI_CONFW, val); - - val =3D TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; - val |=3D (dsi_dev->lanes - 1) << 1; + val =3D (dsi_dev->lanes - 1) << 1; =20 val |=3D TC358768_DSI_CONTROL_TXMD; =20 @@ -1081,11 +1105,13 @@ static void tc358768_bridge_atomic_pre_enable(struc= t drm_bridge *bridge, if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) val |=3D TC358768_DSI_CONTROL_EOTDIS; =20 - tc358768_write(priv, TC358768_DSI_CONFW, val); + mask =3D TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | + 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; + + tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, mask, val); =20 - val =3D TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; - val |=3D TC358768_DSI_CONTROL_DSI_MODE; - tc358768_write(priv, TC358768_DSI_CONFW, val); + tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, + TC358768_DSI_CONTROL_DSI_MODE, 0); =20 ret =3D tc358768_clear_error(priv); if (ret) --=20 2.43.0 From nobody Mon Feb 9 01:06:50 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A1173370F5 for ; Tue, 21 Oct 2025 13:23:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761053024; cv=none; b=M9qj+Ue7lAMY58Pm1XPFEisVJIf5LrXnepbD4q0NAe/7Awrz2CojvbMWOayGWQkO/da5HVaiXwMN/xFjCBprypya35MpDTZ9IMQfqu3PVIF8JPsbLrnVxvRUrSwKDPzOh5XR12A7x4CWZziDLMZVqgfppEyHkndp9LTvGQYkCps= ARC-Message-Signature: i=1; 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Tue, 21 Oct 2025 15:21:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1761052910; bh=txbD4T+DyxHYi9Le0uXTyexEykDWbpT/xM9Z418ot5I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EMh6QoKoFbalDjgXm1SJ05yR1ZFiN2TnTGL5Q9WcX2wdDCnnl2JNft79SYuANq9IE hny5DB8LCMnWtmT86Ju2HBTDkDifRXkXpgMPX3PEFtMK1cUlu/Uwu2A37aF9Yqrqvk 71zsvXDKVsK6sLT3VntNlEuGTg8auTKS2o4wUgcs= From: Tomi Valkeinen Date: Tue, 21 Oct 2025 16:23:00 +0300 Subject: [PATCH 4/7] drm/bridge: tc358768: Support non-continuous clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-tc358768-v1-4-d590dc6a1a0c@ideasonboard.com> References: <20251021-tc358768-v1-0-d590dc6a1a0c@ideasonboard.com> In-Reply-To: <20251021-tc358768-v1-0-d590dc6a1a0c@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Parth Pancholi , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomi Valkeinen , Dmitry Osipenko X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 The driver prints a warning if MIPI_DSI_CLOCK_NON_CONTINUOUS is set, and falls back to continuous clock mode. This was added in commit fbc5a90e82c1 ("drm/bridge: tc358768: Disable non-continuous clock mode"). However, there have been multiple changes to the driver since then, and at least in my setup, non-continuous clock mode works: I can see an image on the panel, and I can see the clock lanes being non-continuous with an oscilloscope. So, let's enable MIPI_DSI_CLOCK_NON_CONTINUOUS support. Signed-off-by: Tomi Valkeinen Cc: Dmitry Osipenko Reviewed-by: Francesco Dolcini Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 --- drivers/gpu/drm/bridge/tc358768.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 755ed6483b2e..a276fbc75dde 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -722,7 +722,6 @@ static void tc358768_bridge_atomic_pre_enable(struct dr= m_bridge *bridge, { struct tc358768_priv *priv =3D bridge_to_tc358768(bridge); struct mipi_dsi_device *dsi_dev =3D priv->output.dev; - unsigned long mode_flags =3D dsi_dev->mode_flags; u32 val, mask, val2, lptxcnt, hact, data_type; s32 raw_val; struct drm_crtc_state *crtc_state; @@ -744,11 +743,6 @@ static void tc358768_bridge_atomic_pre_enable(struct d= rm_bridge *bridge, u32 dsi_vsdly; const u32 internal_dly =3D 40; =20 - if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { - dev_warn_once(dev, "Non-continuous mode unimplemented, falling back to c= ontinuous\n"); - mode_flags &=3D ~MIPI_DSI_CLOCK_NON_CONTINUOUS; - } - tc358768_hw_enable(priv); =20 ret =3D tc358768_sw_reset(priv); @@ -1032,7 +1026,7 @@ static void tc358768_bridge_atomic_pre_enable(struct = drm_bridge *bridge, tc358768_write(priv, TC358768_HSTXVREGEN, val); =20 tc358768_write(priv, TC358768_TXOPTIONCNTRL, - (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); + (dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0= )); =20 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ val =3D tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4); @@ -1099,7 +1093,7 @@ static void tc358768_bridge_atomic_pre_enable(struct = drm_bridge *bridge, =20 val |=3D TC358768_DSI_CONTROL_TXMD; =20 - if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) + if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) val |=3D TC358768_DSI_CONTROL_HSCKMD; =20 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) --=20 2.43.0 From nobody Mon Feb 9 01:06:50 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF8CA33711B for ; Tue, 21 Oct 2025 13:23:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761053025; cv=none; b=Qdl5IbXAwuEnEU/fVgSPlNjEmSnbz7tolV9xZwj8PeXwZzyYtOZmndHh5AzclfitvLszhI7i7379hWPzwQsuBf7R21Ym1eRz6jhjURemOF4eWuwN6U+IY3QEP2y7/aWF4iCSLFmmOYPINTuybYopJCVFVy+I2CghelqE28kb1oI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761053025; c=relaxed/simple; bh=XaG+d9fyiObtuju/o63OkE/MbTOIX8VL9vbdw30zwBg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=B1l77AE90hzaGY13uHg/kNy++JXh1RhrRev/ijkZv8bDxB0XuUW0e0Lprx7nPKzjoxTxqfXkVHJDe1ezkirm0BZaMKSjiTGMn2+TbSWhn5UFOp1ak/MdMAkaklAgyZ4FBDgRwuBnkgOlH+TkWA05daIga0lVoC9ldraEum8ZvVQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=FUQkomKk; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="FUQkomKk" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id C1E31134C; Tue, 21 Oct 2025 15:21:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1761052911; bh=XaG+d9fyiObtuju/o63OkE/MbTOIX8VL9vbdw30zwBg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FUQkomKkkzInbOxkR6auwFwdH3RDJjEGfkKgDTbh2CgAhJZVXgvfgBb5RFo4NAp+v zqRgxzXFQlgMhfvlm4kb44rE3LFc72vwTn2i74EBB5l0Dv023/kitvXxOap/TDqNMM FSKjoUI68dIN5bLnkWN1GRR8XeL0DNNGTgoVpfqI= From: Tomi Valkeinen Date: Tue, 21 Oct 2025 16:23:01 +0300 Subject: [PATCH 5/7] drm/bridge: tc358768: Add LP mode command support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-tc358768-v1-5-d590dc6a1a0c@ideasonboard.com> References: <20251021-tc358768-v1-0-d590dc6a1a0c@ideasonboard.com> In-Reply-To: <20251021-tc358768-v1-0-d590dc6a1a0c@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Parth Pancholi , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1403; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=XaG+d9fyiObtuju/o63OkE/MbTOIX8VL9vbdw30zwBg=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBo94lPpZjx7puBa7b/dTW+Lp6esax/BZQXma3ol dKK2bsJAnKJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCaPeJTwAKCRD6PaqMvJYe 9V5vD/4ugHbVnRj7DUD1toPiJp2291oLERPBL55aAUV+Vb9TG2lFog+92wvQdscY2CBTOM+j0lr 5usGlAkhjvja3HxcVa3FKh1knl2WEi1t8TvoNjPzAqVvcYuT+Hpqpewr6dOqO5VcgdQHUXB0rDB Mo0X8bGeGpLcSE412cw3resvs1pusq/TkJ9LxRTuO2bAcP3rcgXQNZLDbGprblAwazNu7j/Nshd dtHHfEU6m5YoIXZWEeW+0M49ZgRj9mwIfkVqeseHGtntp2ksoHsFlQsalBqyXkKSYDDFc+n7KY7 XlfJzCHl5uLApEyat48ajlNfZYXNKZV1jWU8nUbSby+NtrBaTV/gpA8wdKRzj8Re9bx3W3bgfE8 s+vVMBMzmqM91n5/KLBnPE866vTCaMzFoyRUAd76ccFie0JFZfUXbxwFpSZra7mOoWTYuGXCmnB /lscnrMmbwD1sAZJoLR2YXiQ8NKheD/Gdaq+Mx8pQWGp3T3LrjO2uNcJY5f8UfYdqO/J9KGlrWf uFxzBZO6MNqCauvF3BeeXjbrcxb2R8/PljtGG8iEusnWxpU/uMMf+xw40ONlCZq/mIBXxWxvr6O Uddkr1Sm2NFJXTF/WNCtSkJVVVzXi4FjKpAqGqcnRvskDcfKckrRrz5aPQKzxqd0+pgIUbidiKX fPbmARBuGR0W8Pw== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Currently the driver ignores MIPI_DSI_MODE_LPM and always uses HS mode. Add code to enable HS mode in pre_enable() only if MIPI_DSI_MODE_LPM is not set, and always enable HS mode in enable() for video transmission. Signed-off-by: Tomi Valkeinen Reviewed-by: Francesco Dolcini Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 --- drivers/gpu/drm/bridge/tc358768.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index a276fbc75dde..a7a14c125ac4 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -1091,7 +1091,8 @@ static void tc358768_bridge_atomic_pre_enable(struct = drm_bridge *bridge, /* Configure DSI_Control register */ val =3D (dsi_dev->lanes - 1) << 1; =20 - val |=3D TC358768_DSI_CONTROL_TXMD; + if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM)) + val |=3D TC358768_DSI_CONTROL_TXMD; =20 if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) val |=3D TC358768_DSI_CONTROL_HSCKMD; @@ -1123,6 +1124,11 @@ static void tc358768_bridge_atomic_enable(struct drm= _bridge *bridge, return; } =20 + /* Enable HS mode for video TX */ + tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, + TC358768_DSI_CONTROL_TXMD, + TC358768_DSI_CONTROL_TXMD); + /* clear FrmStop and RstPtr */ tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0); =20 --=20 2.43.0 From nobody Mon Feb 9 01:06:50 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82432338583 for ; Tue, 21 Oct 2025 13:23:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761053027; cv=none; b=rvj67ZxWgTUALsszfRQNpb/jn7oxQLc+fHfZrlV9NZDeHthbU8ZYio/FugaOimoz/x6EpRxZuilbZaabYxg5hojQIlas6r+y/oFkX7H8IPlYX8CaY/5u6ENWyxwV8mZhHHSmjdj+HEif4ur/Mu6Jjc2XsUAIDq8lBnff05aC0Dk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761053027; c=relaxed/simple; bh=xl8LY50t1nFK7zo4QzL7OcSdYgLXevi6DdqZ8vAxkZc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Sending long commands using the video buffer (to be implemented in following patches) requires setting TC358768_DATAFMT and TC358768_DSITX_DT registers for command transfer. The same registers also need to be configured properly for video transfer. The long commands will be sent between the bridge's pre_enable() and enable(), and currently we configure the registers for video transfer in pre_enable(). Thus, they would be overwritten by the long command transfer code. To prevent that from happening, set those registers for video transfer in enable(), not in pre_enable(). Based on code from Parth Pancholi Signed-off-by: Tomi Valkeinen Reviewed-by: Francesco Dolcini Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 --- drivers/gpu/drm/bridge/tc358768.c | 51 ++++++++++++++++++++++++++++-------= ---- 1 file changed, 37 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index a7a14c125ac4..e1ed4003b3c5 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -722,7 +722,7 @@ static void tc358768_bridge_atomic_pre_enable(struct dr= m_bridge *bridge, { struct tc358768_priv *priv =3D bridge_to_tc358768(bridge); struct mipi_dsi_device *dsi_dev =3D priv->output.dev; - u32 val, mask, val2, lptxcnt, hact, data_type; + u32 val, mask, val2, lptxcnt, hact; s32 raw_val; struct drm_crtc_state *crtc_state; struct drm_connector_state *conn_state; @@ -768,30 +768,20 @@ static void tc358768_bridge_atomic_pre_enable(struct = drm_bridge *bridge, dsiclk =3D priv->dsiclk; hsbyteclk =3D dsiclk / 4; =20 - /* Data Format Control Register */ - val =3D BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ switch (dsi_dev->format) { case MIPI_DSI_FMT_RGB888: - val |=3D (0x3 << 4); hact =3D vm.hactive * 3; - data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_24; break; case MIPI_DSI_FMT_RGB666: - val |=3D (0x4 << 4); hact =3D vm.hactive * 3; - data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_18; break; =20 case MIPI_DSI_FMT_RGB666_PACKED: - val |=3D (0x4 << 4) | BIT(3); hact =3D vm.hactive * 18 / 8; - data_type =3D MIPI_DSI_PIXEL_STREAM_3BYTE_18; break; =20 case MIPI_DSI_FMT_RGB565: - val |=3D (0x5 << 4); hact =3D vm.hactive * 2; - data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default: dev_err(dev, "Invalid data format (%u)\n", @@ -947,9 +937,6 @@ static void tc358768_bridge_atomic_pre_enable(struct dr= m_bridge *bridge, /* VSDly[9:0] */ tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly); =20 - tc358768_write(priv, TC358768_DATAFMT, val); - tc358768_write(priv, TC358768_DSITX_DT, data_type); - /* Enable D-PHY (HiZ->LP11) */ tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000); /* Enable lanes */ @@ -1113,6 +1100,39 @@ static void tc358768_bridge_atomic_pre_enable(struct= drm_bridge *bridge, dev_err(dev, "Bridge pre_enable failed: %d\n", ret); } =20 +static void tc358768_config_video_format(struct tc358768_priv *priv) +{ + struct mipi_dsi_device *dsi_dev =3D priv->output.dev; + u32 val, data_type; + + /* Data Format Control Register */ + val =3D BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ + switch (dsi_dev->format) { + case MIPI_DSI_FMT_RGB888: + val |=3D (0x3 << 4); + data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_24; + break; + case MIPI_DSI_FMT_RGB666: + val |=3D (0x4 << 4); + data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_18; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + val |=3D (0x4 << 4) | BIT(3); + data_type =3D MIPI_DSI_PIXEL_STREAM_3BYTE_18; + break; + case MIPI_DSI_FMT_RGB565: + val |=3D (0x5 << 4); + data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; + break; + default: + dev_err(priv->dev, "Invalid data format (%u)\n", dsi_dev->format); + return; + } + + tc358768_write(priv, TC358768_DATAFMT, val); + tc358768_write(priv, TC358768_DSITX_DT, data_type); +} + static void tc358768_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_atomic_state *state) { @@ -1124,6 +1144,9 @@ static void tc358768_bridge_atomic_enable(struct drm_= bridge *bridge, return; } =20 + /* Configure video format registers */ + tc358768_config_video_format(priv); + /* Enable HS mode for video TX */ tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, TC358768_DSI_CONTROL_TXMD, --=20 2.43.0 From nobody Mon Feb 9 01:06:50 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 079C13385BB for ; Tue, 21 Oct 2025 13:23:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 TC358768 has two ways to send DSI commands: 1) buffer the payload data into registers (DSICMD_WDx), which supports up to 8 bytes of payload, 2) buffer the payload data into the video buffer, which supports up to 1024 bytes of payload. The driver currently supports method 1). Add support for transmitting long DSI commands (more than 8 bytes, up to 1024 bytes) using the video buffer. This mode can only be used before the actual video transmission is enabled, i.e. the initial configuration. Original version from Parth Pancholi Signed-off-by: Tomi Valkeinen Reviewed-by: Francesco Dolcini Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 --- drivers/gpu/drm/bridge/tc358768.c | 79 ++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 70 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index e1ed4003b3c5..e0b5a4b5abbe 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -45,6 +45,9 @@ =20 /* Debug (16-bit addressable) */ #define TC358768_VBUFCTRL 0x00E0 +#define TC358768_VBUFCTRL_VBUF_EN BIT(15) +#define TC358768_VBUFCTRL_TX_EN BIT(14) +#define TC358768_VBUFCTRL_MASK BIT(13) #define TC358768_DBG_WIDTH 0x00E2 #define TC358768_DBG_VBLANK 0x00E4 #define TC358768_DBG_DATA 0x00E8 @@ -537,9 +540,21 @@ static ssize_t tc358768_dsi_host_transfer(struct mipi_= dsi_host *host, return -ENOTSUPP; } =20 + if (msg->tx_len > 1024) { + dev_warn(priv->dev, "Maximum 1024 byte MIPI tx is supported\n"); + return -EINVAL; + } + if (msg->tx_len > 8) { - dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n"); - return -ENOTSUPP; + u32 confctl; + + tc358768_read(priv, TC358768_CONFCTL, &confctl); + + if (confctl & BIT(6)) { + dev_warn(priv->dev, + "Video is currently active. Unable to transmit long command\n"); + return -EBUSY; + } } =20 ret =3D mipi_dsi_create_packet(&packet, msg); @@ -552,23 +567,66 @@ static ssize_t tc358768_dsi_host_transfer(struct mipi= _dsi_host *host, tc358768_write(priv, TC358768_DSICMD_WC, 0); tc358768_write(priv, TC358768_DSICMD_WD0, (packet.header[2] << 8) | packet.header[1]); - } else { - int i; - + tc358768_dsicmd_tx(priv); + } else if (packet.payload_length <=3D 8) { tc358768_write(priv, TC358768_DSICMD_TYPE, (0x40 << 8) | (packet.header[0] & 0x3f)); tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length); - for (i =3D 0; i < packet.payload_length; i +=3D 2) { + + for (int i =3D 0; i < packet.payload_length; i +=3D 2) { u16 val =3D packet.payload[i]; =20 if (i + 1 < packet.payload_length) val |=3D packet.payload[i + 1] << 8; - tc358768_write(priv, TC358768_DSICMD_WD0 + i, val); } - } =20 - tc358768_dsicmd_tx(priv); + tc358768_dsicmd_tx(priv); + } else { + unsigned long tx_sleep_us; + size_t len; + + /* For packets over 8 bytes we need to use the video buffer */ + tc358768_write(priv, TC358768_DATAFMT, BIT(0)); /* txdt_en */ + tc358768_write(priv, TC358768_DSITX_DT, packet.header[0] & 0x3f); + tc358768_write(priv, TC358768_CMDBYTE, packet.payload_length); + tc358768_write(priv, TC358768_VBUFCTRL, TC358768_VBUFCTRL_VBUF_EN); + + /* + * Write the payload in 2-byte chunks, and pad with zeroes to + * align to 4 bytes. + */ + len =3D ALIGN(packet.payload_length, 4); + + for (int i =3D 0; i < len; i +=3D 2) { + u16 val =3D 0; + + if (i < packet.payload_length) + val |=3D packet.payload[i]; + if (i + 1 < packet.payload_length) + val |=3D packet.payload[i + 1] << 8; + + tc358768_write(priv, TC358768_DBG_DATA, val); + } + + /* Start transmission */ + tc358768_write(priv, TC358768_VBUFCTRL, + TC358768_VBUFCTRL_VBUF_EN | + TC358768_VBUFCTRL_TX_EN | + TC358768_VBUFCTRL_MASK); + + /* + * The TC358768 spec says to wait until the transmission has + * been finished, estimating the sleep time based on the payload + * and clock rates. We use a simple safe estimate of 2us per + * byte (LP mode transmission). + */ + tx_sleep_us =3D packet.payload_length * 2; + usleep_range(tx_sleep_us, tx_sleep_us * 2); + + tc358768_write(priv, TC358768_VBUFCTRL, TC358768_VBUFCTRL_MASK); + tc358768_write(priv, TC358768_VBUFCTRL, 0); /* Stop transmission */ + } =20 ret =3D tc358768_clear_error(priv); if (ret) @@ -752,6 +810,9 @@ static void tc358768_bridge_atomic_pre_enable(struct dr= m_bridge *bridge, return; } =20 + /* Release RstPtr so that the video buffer can be used for DSI commands */ + tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), 0); + connector =3D drm_atomic_get_new_connector_for_encoder(state, bridge->enc= oder); conn_state =3D drm_atomic_get_new_connector_state(state, connector); crtc_state =3D drm_atomic_get_new_crtc_state(state, conn_state->crtc); --=20 2.43.0