From nobody Wed Dec 17 13:03:32 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE12632B9B8 for ; Tue, 21 Oct 2025 10:19:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761041981; cv=none; b=XNBEgCRR31f2ygb7HT1VKJI+sF5J2ATnqqVoljIonrGTOyvNaDarHcCyaFtETu9mVxkc6U3SraR6aUQtTkt5zvLql7tBr5cxLUVkMLYYnlSFGHAeH0DRcBPbaMEHzMPXCG+UtzPBAnJPi/WgG1+cVkckAFbHdVq+skh4PX5jHGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761041981; c=relaxed/simple; bh=waDB8vYtdQBNKPeuHj9GmNwB3+DzA3ILMPqCkgoY4QU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EO/1Vm+u1xp5rmQM/gyQLJawSdM52Csi48mbCO9SihQ9W8dkn2eihH55T31JbfdTHOrxxq9mDDxeL+mrhVOlP/oq1JooqVHibj32ZeqJc7lWiRLkBePAbzKw9ENAAcBSZ2fJtw4sszPJd3gnqEKVmNgLtRZTPJ+0LCAS+Nub9lc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=N5dMcJEB; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="N5dMcJEB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1761041971; bh=waDB8vYtdQBNKPeuHj9GmNwB3+DzA3ILMPqCkgoY4QU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=N5dMcJEBWenjFfMhSfSW05POUd4QU56PtqoDPzIPxpqgfYVuw5ijoN4kMY1sKUbLy wW8XfMjHPjnAV4FPWTK5uwbcULd9EzgzlyurJJFw+Ru67WcwfHWzC4adaczraBGO1j BuJ33aQYscsfQ59/AnuGoCdYt16VR4NfRIoEorKEH1pzsYvBM8T14KEUY6UmL6Vc2Z gay3qBmQ3NxqTE+ncCjRSgtSOVlYwM/sGenapLuXH91E072VcSXQyImC5JlNwIBvBL 8/O+tyaQKj+KDF79x6fmDJUBNw5xjh4hRn9XmPccdAvo8D9Ht4HeGa9rTSAJHwFpsD wr8ruxA1So9IQ== Received: from localhost (unknown [82.79.138.145]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 6B52F17E1413; Tue, 21 Oct 2025 12:19:31 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 21 Oct 2025 13:19:17 +0300 Subject: [PATCH v3 4/5] drm/rockchip: dw_hdmi_qp: Use bit macros for RK3576 regs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-rk3588-10bpc-v3-4-3d3eed00a6db@collabora.com> References: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> In-Reply-To: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Stone X-Mailer: b4 0.14.3 For consistency and improved readability, redefine a few RK3576 specific register configurations by relying on GENMASK() and unshifted values for color depth and output format. Those are not used at the moment, but will be needed soon to support the related features. While at it, drop a few other defines which are unlikely to be ever required. Acked-by: Daniel Stone Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 04e18dd9102a..ac5ec697b9a2 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -39,21 +39,16 @@ #define RK3576_HDMI_HDCP14_MEM_EN BIT(15) =20 #define RK3576_VO0_GRF_SOC_CON8 0x0020 -#define RK3576_COLOR_FORMAT_MASK (0xf << 4) -#define RK3576_COLOR_DEPTH_MASK (0xf << 8) -#define RK3576_RGB (0 << 4) -#define RK3576_YUV422 (0x1 << 4) -#define RK3576_YUV444 (0x2 << 4) -#define RK3576_YUV420 (0x3 << 4) -#define RK3576_8BPC (0x0 << 8) -#define RK3576_10BPC (0x6 << 8) +#define RK3576_COLOR_DEPTH_MASK GENMASK(11, 8) +#define RK3576_8BPC 0x0 +#define RK3576_10BPC 0x6 +#define RK3576_COLOR_FORMAT_MASK GENMASK(7, 4) +#define RK3576_RGB 0x9 +#define RK3576_YUV422 0x1 +#define RK3576_YUV444 0x2 +#define RK3576_YUV420 0x3 #define RK3576_CECIN_MASK BIT(3) =20 -#define RK3576_VO0_GRF_SOC_CON12 0x0030 -#define RK3576_GRF_OSDA_DLYN (0xf << 12) -#define RK3576_GRF_OSDA_DIV (0x7f << 1) -#define RK3576_GRF_OSDA_DLY_EN BIT(0) - #define RK3576_VO0_GRF_SOC_CON14 0x0038 #define RK3576_I2S_SEL_MASK BIT(0) #define RK3576_SPDIF_SEL_MASK BIT(1) --=20 2.51.0