From nobody Wed Dec 17 13:03:31 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3437332B980 for ; Tue, 21 Oct 2025 10:19:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761041981; cv=none; b=R42nlXo0Pagx6ZHc9R1o7lst2Nuf6tZYKyhURQjTspMWi16X//oDy5yOUwWqFa2q2p140ZE4c8MBPzeGIcvb/6flYsFN6gbZ/19GXPMaICKC3/ScTkXdcc2gH1hq6oquwORqIYltLXbCGwAN20Z7iUGh+FuvqyCrpWZIhnm9cQE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761041981; c=relaxed/simple; bh=s3C57jE/RyRY0ojZyNVm3JP0AqGDocSnepbywENMmxA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LMla3cr1epTctxw5YuDBzvVBismubkFgGwYuv5ImKvgIL6jT0d1CkvQV5tvOsM4Wl/BkKAUzvTIaCw/AS/lQbLSq7bpsqE6LPV29COdKrCGgwSpqyDA0ZsiZX/iNUEdz1Fio5PVeLksPKv7W8B8OBsbI4wfQEto3BUqbR7A/iX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=J2MW1bF2; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="J2MW1bF2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1761041970; bh=s3C57jE/RyRY0ojZyNVm3JP0AqGDocSnepbywENMmxA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=J2MW1bF2jnDtDz2TXt69m4xCKV49c0rajPIZ/8IoOPaw7/xzDGcbrBDJI3AH7hYNW m4Skcc48Omg5ucJNp67+TljntOI5e5Lxx0a7ZKea/w6mv21leIQmLvE7WEeKOD4Vhk xAmTtsutwq9Q6UInX1mLLXYsvGQtvV0anLs2K1gQYanFqRKgfty7G2d8NoAwYdstaO NXHowjCKF6HBAeaMm43a8opDWYyN1nSaiz7xG7DFgZZfLhHSqm/jvAQwQF5B3svM9n gT87s9ZxxauaxNRifVctU43DiS6q+05dy1sNkoQaEviSbGKqJD0mU7nLDm+qkhxS4k Lb2Oo6y7EvAHQ== Received: from localhost (unknown [82.79.138.145]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id A147017E1407; Tue, 21 Oct 2025 12:19:30 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 21 Oct 2025 13:19:16 +0300 Subject: [PATCH v3 3/5] drm/rockchip: dw_hdmi_qp: Switch to phy_configure() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-rk3588-10bpc-v3-3-3d3eed00a6db@collabora.com> References: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> In-Reply-To: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Stone X-Mailer: b4 0.14.3 Stop relying on phy_set_bus_width() based workaround to setup the TMDS character rate and, instead, use the recently introduced HDMI PHY configuration API. This is also a prerequisite to enable high color depth and FRL support. Additionally, move the logic to ->atomic_check() callback where the current mode rate is already provided by the connector state. As a matter of fact this is actually necessary to ensure the link rate is configured before VOP2 attempts to use the PHY PLL as a DCLK source in vop2_crtc_atomic_enable(). The rationale is to restrict any changes of the PHY rate via CCF and, instead, prefer the PHY configuration API for this purpose. Acked-by: Daniel Stone Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 37 +++++++++++++---------= ---- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 931343b072ad..04e18dd9102a 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include =20 @@ -96,6 +97,7 @@ struct rockchip_hdmi_qp { struct delayed_work hpd_work; int port_id; const struct rockchip_hdmi_qp_ctrl_ops *ctrl_ops; + unsigned long long tmds_char_rate; }; =20 struct rockchip_hdmi_qp_ctrl_ops { @@ -114,24 +116,9 @@ static struct rockchip_hdmi_qp *to_rockchip_hdmi_qp(st= ruct drm_encoder *encoder) static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder) { struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); - struct drm_crtc *crtc =3D encoder->crtc; - unsigned long long rate; =20 /* Unconditionally switch to TMDS as FRL is not yet supported */ gpiod_set_value(hdmi->enable_gpio, 1); - - if (crtc && crtc->state) { - rate =3D drm_hdmi_compute_mode_clock(&crtc->state->adjusted_mode, - 8, HDMI_COLORSPACE_RGB); - /* - * FIXME: Temporary workaround to pass pixel clock rate - * to the PHY driver until phy_configure_opts_hdmi - * becomes available in the PHY API. See also the related - * comment in rk_hdptx_phy_power_on() from - * drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c - */ - phy_set_bus_width(hdmi->phy, div_u64(rate, 100)); - } } =20 static int @@ -139,12 +126,26 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_e= ncoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); struct rockchip_crtc_state *s =3D to_rockchip_crtc_state(crtc_state); + union phy_configure_opts phy_cfg =3D {}; + int ret; =20 - s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; - s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; + if (hdmi->tmds_char_rate =3D=3D conn_state->hdmi.tmds_char_rate) + return 0; =20 - return 0; + phy_cfg.hdmi.tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; + + ret =3D phy_configure(hdmi->phy, &phy_cfg); + if (!ret) { + hdmi->tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; + s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; + s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; + } else { + dev_err(hdmi->dev, "Failed to configure phy: %d\n", ret); + } + + return ret; } =20 static const struct --=20 2.51.0