From nobody Wed Dec 17 12:47:23 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67E8D26B2DA for ; Tue, 21 Oct 2025 10:19:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761041978; cv=none; b=Yig70nCdYIFppDnAeDM5lnuzUEQ/HLsJU7NyybO/jjUMXLTZwX5UeWTJ117PHjKwcjj4j7tT7PWqa0+U1p6+SgURtQiLa1hlnWC9a+Xb8Kx8fpQavVJHKS55INYDeCPddg+dCh74QaOGB6V0Qa7s1Ywrjei4yuP6YXRJpMirfRY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761041978; c=relaxed/simple; bh=y/xlBmCmud/5CWpIujKGb7vl0OQ2W7IHrhHnGXT37Ek=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=P/EIY19KqojZ7OBwHFZgqiph0tbS4IUYUBoWXBC51QBLdO0oSA03d8VYVoZ7XXc4aP+OhUi7XYBJ2ZWRxw5ZnhBOTBxlNqxnuE1nZqtBWaCmFCsUH1cMXQ5InhsBQ8rSL34ttTTdOl4DK9cGFkHDNRI6VsCs15H2cKiZ0eDRYnk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=TGUFXqDR; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="TGUFXqDR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1761041969; bh=y/xlBmCmud/5CWpIujKGb7vl0OQ2W7IHrhHnGXT37Ek=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TGUFXqDRSCsxPLa4XyRqdMDeh3Fh17vn1mJqvDSwrNR0XHN1RRcg3X7seVsrywUVB Jw57bObsYYG9fyvwKf+lWZmhFZH0ymbABmeticfeZR31rR9+FV153ZmUtUPoJ+AhkB mPLy+EC4M9wzM1w3vmr8vxRPCLqpHSFpG8K7at9FRwLic1oI3QLc6YSjVqKv4mSEMM iY9eD0dfJw2NV6hFyh/kRUSOCJRp1tyAB9y+BVSChgCRvFgFqKOk7XqUFDkj5ViqVI RjT9zHGzsEczhgd1sW7xUmEHf9mFxaK6TpfkX5uRuiVBv27FuRFm0+pwkaTdmRdABV hbXu2BNhAoFyg== Received: from localhost (unknown [82.79.138.145]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 1BB4417E131B; Tue, 21 Oct 2025 12:19:29 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 21 Oct 2025 13:19:14 +0300 Subject: [PATCH v3 1/5] drm/rockchip: vop2: Check bpc before switching DCLK source Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-rk3588-10bpc-v3-1-3d3eed00a6db@collabora.com> References: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> In-Reply-To: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Stone X-Mailer: b4 0.14.3 When making use of the HDMI PHY PLL as a VOP2 DCLK source, it's output rate does normally match the mode clock. But this is only applicable for default color depth of 8 bpc. For higher depths, the output clock is further divided by the hardware according to the formula: output rate =3D PHY PLL rate * 8 / bpc Hence there is no need for VOP2 to compensate for bpc when adjusting DCLK, but it is required to do so when computing its maximum operating frequency. Take color depth into consideration before deciding to switch DCLK source. Reviewed-by: Daniel Stone Acked-by: Daniel Stone Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 58 +++++++++++++++---------= ---- 1 file changed, 32 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 284c8a048034..54176298a53b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -101,7 +101,7 @@ enum vop2_afbc_format { VOP2_AFBC_FMT_INVALID =3D -1, }; =20 -#define VOP2_MAX_DCLK_RATE 600000000 +#define VOP2_MAX_DCLK_RATE 600000000UL =20 /* * bus-format types. @@ -1742,36 +1742,42 @@ static void vop2_crtc_atomic_enable(struct drm_crtc= *crtc, * Switch to HDMI PHY PLL as DCLK source for display modes up * to 4K@60Hz, if available, otherwise keep using the system CRU. */ - if ((vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) && clock <=3D VOP2_MAX_DCL= K_RATE) { - drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { - struct rockchip_encoder *rkencoder =3D to_rockchip_encoder(encoder); - - if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI0) { - if (!vop2->pll_hdmiphy0) + if (vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) { + unsigned long max_dclk =3D DIV_ROUND_CLOSEST_ULL(VOP2_MAX_DCLK_RATE * 8, + vcstate->output_bpc); + if (clock <=3D max_dclk) { + drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask)= { + struct rockchip_encoder *rkencoder =3D to_rockchip_encoder(encoder); + + if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI0) { + if (!vop2->pll_hdmiphy0) + break; + + if (!vp->dclk_src) + vp->dclk_src =3D clk_get_parent(vp->dclk); + + ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); + if (ret < 0) + drm_warn(vop2->drm, + "Could not switch to HDMI0 PHY PLL: %d\n", + ret); break; + } =20 - if (!vp->dclk_src) - vp->dclk_src =3D clk_get_parent(vp->dclk); + if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI1) { + if (!vop2->pll_hdmiphy1) + break; =20 - ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); - if (ret < 0) - drm_warn(vop2->drm, - "Could not switch to HDMI0 PHY PLL: %d\n", ret); - break; - } + if (!vp->dclk_src) + vp->dclk_src =3D clk_get_parent(vp->dclk); =20 - if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI1) { - if (!vop2->pll_hdmiphy1) + ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); + if (ret < 0) + drm_warn(vop2->drm, + "Could not switch to HDMI1 PHY PLL: %d\n", + ret); break; - - if (!vp->dclk_src) - vp->dclk_src =3D clk_get_parent(vp->dclk); - - ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); - if (ret < 0) - drm_warn(vop2->drm, - "Could not switch to HDMI1 PHY PLL: %d\n", ret); - break; + } } } } --=20 2.51.0