From nobody Wed Dec 17 11:05:30 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67E8D26B2DA for ; Tue, 21 Oct 2025 10:19:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761041978; cv=none; b=Yig70nCdYIFppDnAeDM5lnuzUEQ/HLsJU7NyybO/jjUMXLTZwX5UeWTJ117PHjKwcjj4j7tT7PWqa0+U1p6+SgURtQiLa1hlnWC9a+Xb8Kx8fpQavVJHKS55INYDeCPddg+dCh74QaOGB6V0Qa7s1Ywrjei4yuP6YXRJpMirfRY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761041978; c=relaxed/simple; bh=y/xlBmCmud/5CWpIujKGb7vl0OQ2W7IHrhHnGXT37Ek=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=P/EIY19KqojZ7OBwHFZgqiph0tbS4IUYUBoWXBC51QBLdO0oSA03d8VYVoZ7XXc4aP+OhUi7XYBJ2ZWRxw5ZnhBOTBxlNqxnuE1nZqtBWaCmFCsUH1cMXQ5InhsBQ8rSL34ttTTdOl4DK9cGFkHDNRI6VsCs15H2cKiZ0eDRYnk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=TGUFXqDR; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="TGUFXqDR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1761041969; bh=y/xlBmCmud/5CWpIujKGb7vl0OQ2W7IHrhHnGXT37Ek=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TGUFXqDRSCsxPLa4XyRqdMDeh3Fh17vn1mJqvDSwrNR0XHN1RRcg3X7seVsrywUVB Jw57bObsYYG9fyvwKf+lWZmhFZH0ymbABmeticfeZR31rR9+FV153ZmUtUPoJ+AhkB mPLy+EC4M9wzM1w3vmr8vxRPCLqpHSFpG8K7at9FRwLic1oI3QLc6YSjVqKv4mSEMM iY9eD0dfJw2NV6hFyh/kRUSOCJRp1tyAB9y+BVSChgCRvFgFqKOk7XqUFDkj5ViqVI RjT9zHGzsEczhgd1sW7xUmEHf9mFxaK6TpfkX5uRuiVBv27FuRFm0+pwkaTdmRdABV hbXu2BNhAoFyg== Received: from localhost (unknown [82.79.138.145]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 1BB4417E131B; Tue, 21 Oct 2025 12:19:29 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 21 Oct 2025 13:19:14 +0300 Subject: [PATCH v3 1/5] drm/rockchip: vop2: Check bpc before switching DCLK source Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-rk3588-10bpc-v3-1-3d3eed00a6db@collabora.com> References: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> In-Reply-To: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Stone X-Mailer: b4 0.14.3 When making use of the HDMI PHY PLL as a VOP2 DCLK source, it's output rate does normally match the mode clock. But this is only applicable for default color depth of 8 bpc. For higher depths, the output clock is further divided by the hardware according to the formula: output rate =3D PHY PLL rate * 8 / bpc Hence there is no need for VOP2 to compensate for bpc when adjusting DCLK, but it is required to do so when computing its maximum operating frequency. Take color depth into consideration before deciding to switch DCLK source. Reviewed-by: Daniel Stone Acked-by: Daniel Stone Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 58 +++++++++++++++---------= ---- 1 file changed, 32 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 284c8a048034..54176298a53b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -101,7 +101,7 @@ enum vop2_afbc_format { VOP2_AFBC_FMT_INVALID =3D -1, }; =20 -#define VOP2_MAX_DCLK_RATE 600000000 +#define VOP2_MAX_DCLK_RATE 600000000UL =20 /* * bus-format types. @@ -1742,36 +1742,42 @@ static void vop2_crtc_atomic_enable(struct drm_crtc= *crtc, * Switch to HDMI PHY PLL as DCLK source for display modes up * to 4K@60Hz, if available, otherwise keep using the system CRU. */ - if ((vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) && clock <=3D VOP2_MAX_DCL= K_RATE) { - drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { - struct rockchip_encoder *rkencoder =3D to_rockchip_encoder(encoder); - - if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI0) { - if (!vop2->pll_hdmiphy0) + if (vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) { + unsigned long max_dclk =3D DIV_ROUND_CLOSEST_ULL(VOP2_MAX_DCLK_RATE * 8, + vcstate->output_bpc); + if (clock <=3D max_dclk) { + drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask)= { + struct rockchip_encoder *rkencoder =3D to_rockchip_encoder(encoder); + + if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI0) { + if (!vop2->pll_hdmiphy0) + break; + + if (!vp->dclk_src) + vp->dclk_src =3D clk_get_parent(vp->dclk); + + ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); + if (ret < 0) + drm_warn(vop2->drm, + "Could not switch to HDMI0 PHY PLL: %d\n", + ret); break; + } =20 - if (!vp->dclk_src) - vp->dclk_src =3D clk_get_parent(vp->dclk); + if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI1) { + if (!vop2->pll_hdmiphy1) + break; =20 - ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); - if (ret < 0) - drm_warn(vop2->drm, - "Could not switch to HDMI0 PHY PLL: %d\n", ret); - break; - } + if (!vp->dclk_src) + vp->dclk_src =3D clk_get_parent(vp->dclk); =20 - if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI1) { - if (!vop2->pll_hdmiphy1) + ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); + if (ret < 0) + drm_warn(vop2->drm, + "Could not switch to HDMI1 PHY PLL: %d\n", + ret); break; - - if (!vp->dclk_src) - vp->dclk_src =3D clk_get_parent(vp->dclk); - - ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); - if (ret < 0) - drm_warn(vop2->drm, - "Could not switch to HDMI1 PHY PLL: %d\n", ret); - break; + } } } } --=20 2.51.0 From nobody Wed Dec 17 11:05:30 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 473222EA17D for ; Tue, 21 Oct 2025 10:19:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; 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Tue, 21 Oct 2025 12:19:29 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 21 Oct 2025 13:19:15 +0300 Subject: [PATCH v3 2/5] drm/bridge: dw-hdmi-qp: Handle platform supported formats and color depth Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-rk3588-10bpc-v3-2-3d3eed00a6db@collabora.com> References: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> In-Reply-To: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Stone X-Mailer: b4 0.14.3 Extend struct dw_hdmi_qp_plat_data to include the supported display output formats and maximum bits per color channel. When provided by the platform driver, use them to setup the HDMI bridge accordingly. Additionally, improve debug logging in dw_hdmi_qp_bridge_atomic_enable() to also show the current HDMI output format and bpc. Acked-by: Daniel Stone Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 11 +++++++++-- include/drm/bridge/dw_hdmi_qp.h | 4 ++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.c index 4ba7b339eff6..fe4c026280f0 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -868,8 +868,9 @@ static void dw_hdmi_qp_bridge_atomic_enable(struct drm_= bridge *bridge, return; =20 if (connector->display_info.is_hdmi) { - dev_dbg(hdmi->dev, "%s mode=3DHDMI rate=3D%llu\n", - __func__, conn_state->hdmi.tmds_char_rate); + dev_dbg(hdmi->dev, "%s mode=3DHDMI %s rate=3D%llu bpc=3D%u\n", __func__, + drm_hdmi_connector_get_output_format_name(conn_state->hdmi.output_forma= t), + conn_state->hdmi.tmds_char_rate, conn_state->hdmi.output_bpc); op_mode =3D 0; hdmi->tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; } else { @@ -1287,6 +1288,12 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_d= evice *pdev, hdmi->bridge.vendor =3D "Synopsys"; hdmi->bridge.product =3D "DW HDMI QP TX"; =20 + if (plat_data->supported_formats) + hdmi->bridge.supported_formats =3D plat_data->supported_formats; + + if (plat_data->max_bpc) + hdmi->bridge.max_bpc =3D plat_data->max_bpc; + hdmi->bridge.ddc =3D dw_hdmi_qp_i2c_adapter(hdmi); if (IS_ERR(hdmi->bridge.ddc)) return ERR_CAST(hdmi->bridge.ddc); diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_q= p.h index 76ecf3130199..3f461f6b9bbf 100644 --- a/include/drm/bridge/dw_hdmi_qp.h +++ b/include/drm/bridge/dw_hdmi_qp.h @@ -25,6 +25,10 @@ struct dw_hdmi_qp_plat_data { int main_irq; int cec_irq; unsigned long ref_clk_rate; + /* Supported output formats: bitmask of @hdmi_colorspace */ + unsigned int supported_formats; + /* Maximum bits per color channel: 8, 10 or 12 */ + unsigned int max_bpc; }; =20 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, --=20 2.51.0 From nobody Wed Dec 17 11:05:30 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3437332B980 for ; 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Tue, 21 Oct 2025 12:19:30 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 21 Oct 2025 13:19:16 +0300 Subject: [PATCH v3 3/5] drm/rockchip: dw_hdmi_qp: Switch to phy_configure() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-rk3588-10bpc-v3-3-3d3eed00a6db@collabora.com> References: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> In-Reply-To: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Stone X-Mailer: b4 0.14.3 Stop relying on phy_set_bus_width() based workaround to setup the TMDS character rate and, instead, use the recently introduced HDMI PHY configuration API. This is also a prerequisite to enable high color depth and FRL support. Additionally, move the logic to ->atomic_check() callback where the current mode rate is already provided by the connector state. As a matter of fact this is actually necessary to ensure the link rate is configured before VOP2 attempts to use the PHY PLL as a DCLK source in vop2_crtc_atomic_enable(). The rationale is to restrict any changes of the PHY rate via CCF and, instead, prefer the PHY configuration API for this purpose. Acked-by: Daniel Stone Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 37 +++++++++++++---------= ---- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 931343b072ad..04e18dd9102a 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include =20 @@ -96,6 +97,7 @@ struct rockchip_hdmi_qp { struct delayed_work hpd_work; int port_id; const struct rockchip_hdmi_qp_ctrl_ops *ctrl_ops; + unsigned long long tmds_char_rate; }; =20 struct rockchip_hdmi_qp_ctrl_ops { @@ -114,24 +116,9 @@ static struct rockchip_hdmi_qp *to_rockchip_hdmi_qp(st= ruct drm_encoder *encoder) static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder) { struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); - struct drm_crtc *crtc =3D encoder->crtc; - unsigned long long rate; =20 /* Unconditionally switch to TMDS as FRL is not yet supported */ gpiod_set_value(hdmi->enable_gpio, 1); - - if (crtc && crtc->state) { - rate =3D drm_hdmi_compute_mode_clock(&crtc->state->adjusted_mode, - 8, HDMI_COLORSPACE_RGB); - /* - * FIXME: Temporary workaround to pass pixel clock rate - * to the PHY driver until phy_configure_opts_hdmi - * becomes available in the PHY API. See also the related - * comment in rk_hdptx_phy_power_on() from - * drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c - */ - phy_set_bus_width(hdmi->phy, div_u64(rate, 100)); - } } =20 static int @@ -139,12 +126,26 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_e= ncoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); struct rockchip_crtc_state *s =3D to_rockchip_crtc_state(crtc_state); + union phy_configure_opts phy_cfg =3D {}; + int ret; =20 - s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; - s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; + if (hdmi->tmds_char_rate =3D=3D conn_state->hdmi.tmds_char_rate) + return 0; =20 - return 0; + phy_cfg.hdmi.tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; + + ret =3D phy_configure(hdmi->phy, &phy_cfg); + if (!ret) { + hdmi->tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; + s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; + s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; + } else { + dev_err(hdmi->dev, "Failed to configure phy: %d\n", ret); + } + + return ret; } =20 static const struct --=20 2.51.0 From nobody Wed Dec 17 11:05:30 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE12632B9B8 for ; Tue, 21 Oct 2025 10:19:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761041981; cv=none; b=XNBEgCRR31f2ygb7HT1VKJI+sF5J2ATnqqVoljIonrGTOyvNaDarHcCyaFtETu9mVxkc6U3SraR6aUQtTkt5zvLql7tBr5cxLUVkMLYYnlSFGHAeH0DRcBPbaMEHzMPXCG+UtzPBAnJPi/WgG1+cVkckAFbHdVq+skh4PX5jHGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761041981; c=relaxed/simple; bh=waDB8vYtdQBNKPeuHj9GmNwB3+DzA3ILMPqCkgoY4QU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Tue, 21 Oct 2025 12:19:31 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 21 Oct 2025 13:19:17 +0300 Subject: [PATCH v3 4/5] drm/rockchip: dw_hdmi_qp: Use bit macros for RK3576 regs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-rk3588-10bpc-v3-4-3d3eed00a6db@collabora.com> References: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> In-Reply-To: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Stone X-Mailer: b4 0.14.3 For consistency and improved readability, redefine a few RK3576 specific register configurations by relying on GENMASK() and unshifted values for color depth and output format. Those are not used at the moment, but will be needed soon to support the related features. While at it, drop a few other defines which are unlikely to be ever required. Acked-by: Daniel Stone Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 04e18dd9102a..ac5ec697b9a2 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -39,21 +39,16 @@ #define RK3576_HDMI_HDCP14_MEM_EN BIT(15) =20 #define RK3576_VO0_GRF_SOC_CON8 0x0020 -#define RK3576_COLOR_FORMAT_MASK (0xf << 4) -#define RK3576_COLOR_DEPTH_MASK (0xf << 8) -#define RK3576_RGB (0 << 4) -#define RK3576_YUV422 (0x1 << 4) -#define RK3576_YUV444 (0x2 << 4) -#define RK3576_YUV420 (0x3 << 4) -#define RK3576_8BPC (0x0 << 8) -#define RK3576_10BPC (0x6 << 8) +#define RK3576_COLOR_DEPTH_MASK GENMASK(11, 8) +#define RK3576_8BPC 0x0 +#define RK3576_10BPC 0x6 +#define RK3576_COLOR_FORMAT_MASK GENMASK(7, 4) +#define RK3576_RGB 0x9 +#define RK3576_YUV422 0x1 +#define RK3576_YUV444 0x2 +#define RK3576_YUV420 0x3 #define RK3576_CECIN_MASK BIT(3) =20 -#define RK3576_VO0_GRF_SOC_CON12 0x0030 -#define RK3576_GRF_OSDA_DLYN (0xf << 12) -#define RK3576_GRF_OSDA_DIV (0x7f << 1) -#define RK3576_GRF_OSDA_DLY_EN BIT(0) - #define RK3576_VO0_GRF_SOC_CON14 0x0038 #define RK3576_I2S_SEL_MASK BIT(0) #define RK3576_SPDIF_SEL_MASK BIT(1) --=20 2.51.0 From nobody Wed Dec 17 11:05:30 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F22C032B9BB for ; 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Tue, 21 Oct 2025 12:19:32 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 21 Oct 2025 13:19:18 +0300 Subject: [PATCH v3 5/5] drm/rockchip: dw_hdmi_qp: Add high color depth support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-rk3588-10bpc-v3-5-3d3eed00a6db@collabora.com> References: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> In-Reply-To: <20251021-rk3588-10bpc-v3-0-3d3eed00a6db@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Stone X-Mailer: b4 0.14.3 Since both RK3576 and RK3588 SoCs are capable of handling 10 bpc color depth, introduce a pair of new helpers to program the necessary registers, as well as passing bpc at PHY configuration level. Note max_bpc is unconditionally set to 10 before initializing the QP bridge library, as there is no need to adjust it dynamically, i.e. per SoC variant, for now. While setting up .enc_init() callbacks of rockchip_hdmi_qp_ctrl_ops, also replace the unnecessary whitespace chars before .irq_callback() assignments. Acked-by: Daniel Stone Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 54 ++++++++++++++++++++++= ++-- 1 file changed, 51 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index ac5ec697b9a2..ca3fa3965302 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -70,6 +70,12 @@ #define RK3588_HDMI1_LEVEL_INT BIT(24) #define RK3588_GRF_VO1_CON3 0x000c #define RK3588_GRF_VO1_CON6 0x0018 +#define RK3588_COLOR_DEPTH_MASK GENMASK(7, 4) +#define RK3588_8BPC 0x0 +#define RK3588_10BPC 0x6 +#define RK3588_COLOR_FORMAT_MASK GENMASK(3, 0) +#define RK3588_RGB 0x0 +#define RK3588_YUV420 0x3 #define RK3588_SCLIN_MASK BIT(9) #define RK3588_SDAIN_MASK BIT(10) #define RK3588_MODE_MASK BIT(11) @@ -97,6 +103,7 @@ struct rockchip_hdmi_qp { =20 struct rockchip_hdmi_qp_ctrl_ops { void (*io_init)(struct rockchip_hdmi_qp *hdmi); + void (*enc_init)(struct rockchip_hdmi_qp *hdmi, struct rockchip_crtc_stat= e *state); irqreturn_t (*irq_callback)(int irq, void *dev_id); irqreturn_t (*hardirq_callback)(int irq, void *dev_id); }; @@ -111,9 +118,16 @@ static struct rockchip_hdmi_qp *to_rockchip_hdmi_qp(st= ruct drm_encoder *encoder) static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder) { struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); + struct drm_crtc *crtc =3D encoder->crtc; =20 /* Unconditionally switch to TMDS as FRL is not yet supported */ gpiod_set_value(hdmi->enable_gpio, 1); + + if (!crtc || !crtc->state) + return; + + if (hdmi->ctrl_ops->enc_init) + hdmi->ctrl_ops->enc_init(hdmi, to_rockchip_crtc_state(crtc->state)); } =20 static int @@ -126,16 +140,19 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_e= ncoder *encoder, union phy_configure_opts phy_cfg =3D {}; int ret; =20 - if (hdmi->tmds_char_rate =3D=3D conn_state->hdmi.tmds_char_rate) + if (hdmi->tmds_char_rate =3D=3D conn_state->hdmi.tmds_char_rate && + s->output_bpc =3D=3D conn_state->hdmi.output_bpc) return 0; =20 phy_cfg.hdmi.tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; + phy_cfg.hdmi.bpc =3D conn_state->hdmi.output_bpc; =20 ret =3D phy_configure(hdmi->phy, &phy_cfg); if (!ret) { hdmi->tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; + s->output_bpc =3D conn_state->hdmi.output_bpc; } else { dev_err(hdmi->dev, "Failed to configure phy: %d\n", ret); } @@ -371,15 +388,45 @@ static void dw_hdmi_qp_rk3588_io_init(struct rockchip= _hdmi_qp *hdmi) regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); } =20 +static void dw_hdmi_qp_rk3576_enc_init(struct rockchip_hdmi_qp *hdmi, + struct rockchip_crtc_state *state) +{ + u32 val; + + if (state->output_bpc =3D=3D 10) + val =3D FIELD_PREP_WM16(RK3576_COLOR_DEPTH_MASK, RK3576_10BPC); + else + val =3D FIELD_PREP_WM16(RK3576_COLOR_DEPTH_MASK, RK3576_8BPC); + + regmap_write(hdmi->vo_regmap, RK3576_VO0_GRF_SOC_CON8, val); +} + +static void dw_hdmi_qp_rk3588_enc_init(struct rockchip_hdmi_qp *hdmi, + struct rockchip_crtc_state *state) +{ + u32 val; + + if (state->output_bpc =3D=3D 10) + val =3D FIELD_PREP_WM16(RK3588_COLOR_DEPTH_MASK, RK3588_10BPC); + else + val =3D FIELD_PREP_WM16(RK3588_COLOR_DEPTH_MASK, RK3588_8BPC); + + regmap_write(hdmi->vo_regmap, + hdmi->port_id ? RK3588_GRF_VO1_CON6 : RK3588_GRF_VO1_CON3, + val); +} + static const struct rockchip_hdmi_qp_ctrl_ops rk3576_hdmi_ctrl_ops =3D { .io_init =3D dw_hdmi_qp_rk3576_io_init, - .irq_callback =3D dw_hdmi_qp_rk3576_irq, + .enc_init =3D dw_hdmi_qp_rk3576_enc_init, + .irq_callback =3D dw_hdmi_qp_rk3576_irq, .hardirq_callback =3D dw_hdmi_qp_rk3576_hardirq, }; =20 static const struct rockchip_hdmi_qp_ctrl_ops rk3588_hdmi_ctrl_ops =3D { .io_init =3D dw_hdmi_qp_rk3588_io_init, - .irq_callback =3D dw_hdmi_qp_rk3588_irq, + .enc_init =3D dw_hdmi_qp_rk3588_enc_init, + .irq_callback =3D dw_hdmi_qp_rk3588_irq, .hardirq_callback =3D dw_hdmi_qp_rk3588_hardirq, }; =20 @@ -472,6 +519,7 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev,= struct device *master, =20 plat_data.phy_ops =3D cfg->phy_ops; plat_data.phy_data =3D hdmi; + plat_data.max_bpc =3D 10; =20 encoder =3D &hdmi->encoder.encoder; encoder->possible_crtcs =3D drm_of_find_possible_crtcs(drm, dev->of_node); --=20 2.51.0