From nobody Mon Feb 9 12:10:08 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D012393DE6; Tue, 21 Oct 2025 16:33:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761064411; cv=none; b=lSZM37fkodeKZAVnl4y1lR2XBeHa+bXmNcPg+HW2vsedAyERsb3nO4R9viQr2//KdRVO0g3RIwpr2NSEuiDCUb6JqKycaayTz2PyK3iEYC6hELlJFZL81Hewp2DdfB73aWX/2qHhQXrwGrGrAYxRxhpxXtQm9OUwTxJA0Qg1Z/E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761064411; c=relaxed/simple; bh=xV60f3TtPvPBOIFwVX8eX6hNiPNHrPFaLwFfddy15oE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k52iQaSfLhJ+dlt9+f2Jyp8AtcsnoHrWV/FQ9rHxWUl27oi0XDwHUB/30HNWG9hF3Du3/X6lKWh72Ht2iIh7/GRB2SG1Cq7jdHJoSEL/ud8zWIqK28IA6GLolbG8Qhnw7zP3p9b0KD7W0yNxXVoRMfWDA6vxpLe0y7oCsV9W8M4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=aW7jfsdE; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="aW7jfsdE" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id E67EA4E41244; Tue, 21 Oct 2025 16:33:27 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id A7207606DC; Tue, 21 Oct 2025 16:33:27 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 969A9102F241B; Tue, 21 Oct 2025 18:33:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761064406; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=UkWINqjsktsmgYG+Rct1tziwvmjmpVHnO11D//uy5lU=; b=aW7jfsdEfLiIZ1s1wMu/DjmPZCLQHbqRs17oyRXcxOEOuvvlWOliw7dinPqEsJXfxv7SXg yacBUF0hOfXhmwehBH1vJ/zWSYAXZ4zMRlOd5vxqt891vFc0uzKdfvqlq42cPzu2K1OF+A s4dGpmqZV5wurg+nz7AwIlULZiVyffIfMlMyzYu2xiuSN1Y+QFBc5WtcyWiA4T0zImZbNO PY7tctF10o4JoFnnHpC6ygTUnwF7pfR2U0akqSjYvA1SjT0KklKenNibiUp9mqwpoCG5jM Kn9kPdF5lTfc3Q/6fLX54iKWFRg214v9O8QJ0FS+r/IVcQTlo7Vc+kRDNAHqJg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 21 Oct 2025 18:32:48 +0200 Subject: [PATCH net-next 07/12] phy: Add driver for EyeQ5 Ethernet PHY wrapper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-macb-eyeq5-v1-7-3b0b5a9d2f85@bootlin.com> References: <20251021-macb-eyeq5-v1-0-3b0b5a9d2f85@bootlin.com> In-Reply-To: <20251021-macb-eyeq5-v1-0-3b0b5a9d2f85@bootlin.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Vladimir Kondratiev , =?utf-8?q?Gr=C3=A9gory_Clement?= , Russell King , Vinod Koul , Kishon Vijay Abraham I , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer , Philipp Zabel Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Thomas Petazzoni , =?utf-8?q?Beno=C3=AEt_Monin?= , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 EyeQ5 embeds a system-controller called OLB. It features many unrelated registers, and some of those are registers used to configure the integration of the RGMII/SGMII Cadence PHY used by MACB/GEM instances. Wrap in a neat generic PHY provider, exposing two PHYs with standard phy_init() / phy_set_mode() / phy_power_on() operations. Signed-off-by: Th=C3=A9o Lebrun --- MAINTAINERS | 1 + drivers/phy/Kconfig | 13 +++ drivers/phy/Makefile | 1 + drivers/phy/phy-eyeq5-eth.c | 254 ++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 269 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4faa7719bf86..0ff4d9ce57e8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17382,6 +17382,7 @@ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S F: drivers/clk/clk-eyeq.c +F: drivers/phy/phy-eyeq5-eth.c F: drivers/pinctrl/pinctrl-eyeq5.c F: drivers/reset/reset-eyeq.c F: include/dt-bindings/clock/mobileye,eyeq5-clk.h diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 678dd0452f0a..1aa6eff12dbc 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -101,6 +101,19 @@ config PHY_NXP_PTN3222 schemes. It supports all three USB 2.0 data rates: Low Speed, Full Speed and High Speed. =20 +config PHY_EYEQ5_ETH + tristate "Ethernet PHY Driver on EyeQ5" + depends on OF + depends on MACH_EYEQ5 || COMPILE_TEST + select AUXILIARY_BUS + select GENERIC_PHY + default MACH_EYEQ5 + help + Enable this to support the Ethernet PHY integrated on EyeQ5. + It supports both RGMII and SGMII. Registers are located in a + shared register region called OLB. If M is selected, the + module will be called phy-eyeq5-eth. + source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index bfb27fb5a494..8289497ece55 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) +=3D phy-snps-eusb2.o obj-$(CONFIG_USB_LGM_PHY) +=3D phy-lgm-usb.o obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o +obj-$(CONFIG_PHY_EYEQ5_ETH) +=3D phy-eyeq5-eth.o obj-y +=3D allwinner/ \ amlogic/ \ broadcom/ \ diff --git a/drivers/phy/phy-eyeq5-eth.c b/drivers/phy/phy-eyeq5-eth.c new file mode 100644 index 000000000000..b65c3d733f6c --- /dev/null +++ b/drivers/phy/phy-eyeq5-eth.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EQ5_PHY_COUNT 2 + +#define EQ5_PHY0_GP 0x128 +#define EQ5_PHY1_GP 0x12c +#define EQ5_PHY0_SGMII 0x134 +#define EQ5_PHY1_SGMII 0x138 + +#define EQ5_GP_TX_SWRST_DIS BIT(0) // Tx SW reset +#define EQ5_GP_TX_M_CLKE BIT(1) // Tx M clock enable +#define EQ5_GP_SYS_SWRST_DIS BIT(2) // Sys SW reset +#define EQ5_GP_SYS_M_CLKE BIT(3) // Sys clock enable +#define EQ5_GP_SGMII_MODE BIT(4) // SGMII mode +#define EQ5_GP_RGMII_DRV GENMASK(8, 5) // RGMII drive strength + +#define EQ5_SGMII_PWR_EN BIT(0) +#define EQ5_SGMII_RST_DIS BIT(1) +#define EQ5_SGMII_PLL_EN BIT(2) +#define EQ5_SGMII_SIG_DET_SW BIT(3) +#define EQ5_SGMII_PWR_STATE BIT(4) +#define EQ5_SGMII_PLL_ACK BIT(18) +#define EQ5_SGMII_PWR_STATE_ACK GENMASK(24, 20) + +struct eq5_phy_inst { + struct eq5_phy_private *priv; + struct phy *phy; + void __iomem *gp, *sgmii; + phy_interface_t phy_interface; +}; + +struct eq5_phy_private { + struct device *dev; + struct eq5_phy_inst phys[EQ5_PHY_COUNT]; +}; + +static int eq5_phy_init(struct phy *phy) +{ + struct eq5_phy_inst *inst =3D phy_get_drvdata(phy); + struct eq5_phy_private *priv =3D inst->priv; + struct device *dev =3D priv->dev; + u32 reg; + + dev_dbg(dev, "phy_init(inst=3D%ld)\n", inst - priv->phys); + + writel(0, inst->gp); + writel(0, inst->sgmii); + + udelay(5); + + reg =3D readl(inst->gp) | EQ5_GP_TX_SWRST_DIS | EQ5_GP_TX_M_CLKE | + EQ5_GP_SYS_SWRST_DIS | EQ5_GP_SYS_M_CLKE | + FIELD_PREP(EQ5_GP_RGMII_DRV, 0x9); + writel(reg, inst->gp); + + return 0; +} + +static int eq5_phy_exit(struct phy *phy) +{ + struct eq5_phy_inst *inst =3D phy_get_drvdata(phy); + struct eq5_phy_private *priv =3D inst->priv; + struct device *dev =3D priv->dev; + + dev_dbg(dev, "phy_exit(inst=3D%ld)\n", inst - priv->phys); + + writel(0, inst->gp); + writel(0, inst->sgmii); + udelay(5); + + return 0; +} + +static int eq5_phy_set_mode(struct phy *phy, enum phy_mode mode, int submo= de) +{ + struct eq5_phy_inst *inst =3D phy_get_drvdata(phy); + struct eq5_phy_private *priv =3D inst->priv; + struct device *dev =3D priv->dev; + + dev_dbg(dev, "phy_set_mode(inst=3D%ld, mode=3D%d, submode=3D%d)\n", + inst - priv->phys, mode, submode); + + if (mode !=3D PHY_MODE_ETHERNET) + return -EOPNOTSUPP; + + if (!phy_interface_mode_is_rgmii(submode) && + submode !=3D PHY_INTERFACE_MODE_SGMII) + return -EOPNOTSUPP; + + inst->phy_interface =3D submode; + return 0; +} + +static int eq5_phy_power_on(struct phy *phy) +{ + struct eq5_phy_inst *inst =3D phy_get_drvdata(phy); + struct eq5_phy_private *priv =3D inst->priv; + struct device *dev =3D priv->dev; + u32 reg; + + dev_dbg(dev, "phy_power_on(inst=3D%ld)\n", inst - priv->phys); + + if (inst->phy_interface =3D=3D PHY_INTERFACE_MODE_SGMII) { + writel(readl(inst->gp) | EQ5_GP_SGMII_MODE, inst->gp); + + reg =3D EQ5_SGMII_PWR_EN | EQ5_SGMII_RST_DIS | EQ5_SGMII_PLL_EN; + writel(reg, inst->sgmii); + + if (readl_poll_timeout(inst->sgmii, reg, + reg & EQ5_SGMII_PLL_ACK, 1, 100)) { + dev_err(dev, "PLL timeout\n"); + return -ETIMEDOUT; + } + + reg =3D readl(inst->sgmii); + reg |=3D EQ5_SGMII_PWR_STATE | EQ5_SGMII_SIG_DET_SW; + writel(reg, inst->sgmii); + } else { + writel(readl(inst->gp) & ~EQ5_GP_SGMII_MODE, inst->gp); + writel(0, inst->sgmii); + } + + return 0; +} + +static int eq5_phy_power_off(struct phy *phy) +{ + struct eq5_phy_inst *inst =3D phy_get_drvdata(phy); + struct eq5_phy_private *priv =3D inst->priv; + struct device *dev =3D priv->dev; + + dev_dbg(dev, "phy_power_off(inst=3D%ld)\n", inst - priv->phys); + + writel(readl(inst->gp) & ~EQ5_GP_SGMII_MODE, inst->gp); + writel(0, inst->sgmii); + + return 0; +} + +static const struct phy_ops eq5_phy_ops =3D { + .init =3D eq5_phy_init, + .exit =3D eq5_phy_exit, + .set_mode =3D eq5_phy_set_mode, + .power_on =3D eq5_phy_power_on, + .power_off =3D eq5_phy_power_off, +}; + +static struct phy *eq5_phy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct eq5_phy_private *priv =3D dev_get_drvdata(dev); + + if (args->args_count !=3D 1 || args->args[0] > 1) + return ERR_PTR(-EINVAL); + + return priv->phys[args->args[0]].phy; +} + +static int eq5_phy_probe_phy(struct eq5_phy_private *priv, unsigned int in= dex, + void __iomem *base, unsigned int gp, + unsigned int sgmii) +{ + struct eq5_phy_inst *inst =3D &priv->phys[index]; + struct device *dev =3D priv->dev; + struct phy *phy; + + phy =3D devm_phy_create(dev, dev->of_node, &eq5_phy_ops); + if (IS_ERR(phy)) { + dev_err(dev, "failed to create PHY %u\n", index); + return PTR_ERR(phy); + } + + inst->priv =3D priv; + inst->phy =3D phy; + inst->gp =3D base + gp; + inst->sgmii =3D base + sgmii; + inst->phy_interface =3D PHY_INTERFACE_MODE_NA; + phy_set_drvdata(phy, inst); + + return 0; +} + +static int eq5_phy_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev =3D &adev->dev; + struct phy_provider *provider; + struct eq5_phy_private *priv; + void __iomem *base; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + dev_set_drvdata(dev, priv); + + base =3D (void __iomem *)dev_get_platdata(dev); + + ret =3D eq5_phy_probe_phy(priv, 0, base, EQ5_PHY0_GP, EQ5_PHY0_SGMII); + if (ret) + return ret; + + ret =3D eq5_phy_probe_phy(priv, 1, base, EQ5_PHY1_GP, EQ5_PHY1_SGMII); + if (ret) + return ret; + + provider =3D devm_of_phy_provider_register(dev, eq5_phy_xlate); + if (IS_ERR(provider)) { + dev_err(dev, "registering provider failed\n"); + return PTR_ERR(provider); + } + + return 0; +} + +static const struct auxiliary_device_id eq5_phy_id_table[] =3D { + { .name =3D "clk_eyeq.phy" }, + {} +}; +MODULE_DEVICE_TABLE(auxiliary, eq5_phy_id_table); + +static struct auxiliary_driver eq5_phy_driver =3D { + .probe =3D eq5_phy_probe, + .id_table =3D eq5_phy_id_table, +}; +module_auxiliary_driver(eq5_phy_driver); + +MODULE_DESCRIPTION("EyeQ5 Ethernet PHY driver"); +MODULE_AUTHOR("Th=C3=A9o Lebrun "); +MODULE_LICENSE("GPL"); --=20 2.51.1