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These are required for describing the Milianke MLKPAI-FS01 board with DR1V90 SoC from Anlogic, which uses a processor core designed by Nuclei. Acked-by: Krzysztof Kozlowski Signed-off-by: Junhui Liu --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index f1d1882009ba9e80127bae0151af157879fe3070..23e74b96bfb78cff5cf5fc7e48d= e81092b81b9da 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -132,6 +132,8 @@ patternProperties: description: Anbernic "^andestech,.*": description: Andes Technology Corporation + "^anlogic,.*": + description: Shanghai Anlogic Infotech Co., Ltd. "^anvo,.*": description: Anvo-Systems Dresden GmbH "^aoly,.*": @@ -1023,6 +1025,8 @@ patternProperties: description: MikroElektronika d.o.o. "^mikrotik,.*": description: MikroTik + "^milianke,.*": + description: Changzhou Milianke Electronic Technology Co., Ltd "^milkv,.*": description: MilkV Technology Co., Ltd "^miniand,.*": @@ -1140,6 +1144,8 @@ patternProperties: description: Novatek "^novtech,.*": description: NovTech, Inc. + "^nuclei,.*": + description: Nuclei System Technology "^numonyx,.*": description: Numonyx (deprecated, use micron) deprecated: true --=20 2.51.1 From nobody Wed Dec 17 18:14:10 2025 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B092D2E8B75; Tue, 21 Oct 2025 09:45:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.16 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761039916; cv=pass; b=YZasB56axoQEPIEhd64cUXvUyGP4iYMtCRzRlZBvK8d4gscSX9zek/SBRtCW9yng1+qBf7p3dbj3gut/AG5GrcHAQmYJ2WLSKFbTCMM2w3FVoMRV5VmXsFI1IEx1aKSzMbNc/FrefoskJreWauf7VhCUSUcwejC7kYqoXPwTML4= ARC-Message-Signature: i=2; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=RilxgnaE6+nQcWx0vQ+3dyIGCcddcgCTt1jy8Noi5+4=; b=CVEgXSJeAfY820DC0XFAUZ+4RwBYYPZUbnrK+fTB8Zm9mk15kGZ23qqHtRjlvkaC auWVhNfeDHywwHXSex23iaieNsh5IHj66GJxJnp4KR7NGdAjj6AU39Yy/o+8/qGMZWn w4hHdECvgPkr+sOnAviANFb8xUf+moqy2mlann7o= Received: by mx.zohomail.com with SMTPS id 1761039877372806.2676973256036; Tue, 21 Oct 2025 02:44:37 -0700 (PDT) From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:37 +0800 Subject: [PATCH v3 02/13] dt-bindings: riscv: Add Nuclei UX900 compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-dr1v90-basic-dt-v3-2-5478db4f664a@pigmoral.tech> References: <20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech> In-Reply-To: <20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Junhui Liu , Thomas Gleixner , Samuel Holland , Chen Wang , Inochi Amaoto , Daniel Lezcano , Greg Kroah-Hartman , Jiri Slaby Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, Inochi Amaoto , sophgo@lists.linux.dev, linux-serial@vger.kernel.org, Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761039846; l=999; i=junhui.liu@pigmoral.tech; s=20250910; h=from:subject:message-id; bh=5OYq33h90o1+r7OH7UN8UF/BUb5PEB3MS3L1zmHF3vw=; b=H/b+n5Z2ErCQTJ9UpdLacCYN9dWlOcEXkm7NsiwvteVCpJkHVGwXRaCyO1AUN7qZntq4NrGxt 0X3AOAqG7u+A1GD5IEr4pNVPHr2eSMGcmNej/poUpbvaX31l1vju6K2 X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC. It features a 64-bit architecture and dual-issue, 9-stage pipeline, with lots of optional extensions including V, K, Zc, and more. Acked-by: Conor Dooley Signed-off-by: Junhui Liu --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 153d0dac57fb39d39219e138792f4cb831cb88dc..20b7c834559cb11d17dd4e41197= 87b88b85e19b0 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -48,6 +48,7 @@ properties: - amd,mbv64 - andestech,ax45mp - canaan,k210 + - nuclei,ux900 - sifive,bullet0 - sifive,e5 - sifive,e7 --=20 2.51.1 From nobody Wed Dec 17 18:14:10 2025 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C9FA2EBDDC; Tue, 21 Oct 2025 09:45:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.16 ARC-Seal: i=2; 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a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External Add Anlogic DR1V90 FPSoC, featuring a UX900 RISC-V core as the processing system (PS) and 94,464 LUTs programmable logic (PL). It is used by the Milianke MLKPAI-FS01 board, a SBC equipped with 512MB DDR3 memory, USB-C UART, 1GbE RJ45 Ethernet, USB-A 2.0 port, TF card slot, and 256Mbit Quad-SPI flash. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Junhui Liu --- .../devicetree/bindings/riscv/anlogic.yaml | 27 ++++++++++++++++++= ++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/anlogic.yaml b/Documen= tation/devicetree/bindings/riscv/anlogic.yaml new file mode 100644 index 0000000000000000000000000000000000000000..91b1526c99aa3ca9cc7b0e79788= 61408bd017049 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/anlogic.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/anlogic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Anlogic SoC-based boards + +maintainers: + - Junhui Liu + +description: + Anlogic SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - milianke,mlkpai-fs01 + - const: anlogic,dr1v90 + +additionalProperties: true + +... --=20 2.51.1 From nobody Wed Dec 17 18:14:10 2025 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 135B82E7637; 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Acked-by: Conor Dooley Signed-off-by: Junhui Liu --- .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index f683d696909b9da302c53a64f6332f6251705c0d..9ebc483a05abcfcb162d9a8e4ad= 181ffe4c8732a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -58,6 +58,7 @@ properties: - const: andestech,nceplic100 - items: - enum: + - anlogic,dr1v90-plic - canaan,k210-plic - eswin,eic7700-plic - sifive,fu540-c000-plic --=20 2.51.1 From nobody Wed Dec 17 18:14:10 2025 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 949A72DC78A; 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Signed-off-by: Junhui Liu Acked-by: Rob Herring (Arm) --- .../interrupt-controller/thead,c900-aclint-mswi.yaml | 17 +++++++++++--= ---- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c= 900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controll= er/thead,c900-aclint-mswi.yaml index d6fb08a54167f21d454e33a1992e19b358d42dbd..62fd220e126e650e3800d8eee2a= 749fdbbde6108 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-mswi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-mswi.yaml @@ -4,18 +4,23 @@ $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-= mswi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device +title: ACLINT Machine-level Software Interrupt Device =20 maintainers: - Inochi Amaoto =20 properties: compatible: - items: - - enum: - - sophgo,sg2042-aclint-mswi - - sophgo,sg2044-aclint-mswi - - const: thead,c900-aclint-mswi + oneOf: + - items: + - enum: + - sophgo,sg2042-aclint-mswi + - sophgo,sg2044-aclint-mswi + - const: thead,c900-aclint-mswi + - items: + - enum: + - anlogic,dr1v90-aclint-mswi + - const: nuclei,ux900-aclint-mswi =20 reg: maxItems: 1 --=20 2.51.1 From nobody Wed Dec 17 18:14:10 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F19882E7F0D; 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Signed-off-by: Junhui Liu Acked-by: Rob Herring (Arm) --- .../bindings/interrupt-controller/thead,c900-aclint-sswi.yaml | 4 = ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c= 900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controll= er/thead,c900-aclint-sswi.yaml index c1ab865fcd64f1347e7eda7f538c7669f55ff906..d02c6886283af790d75357f77a7= 14558f68bb7d1 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-sswi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-sswi.yaml @@ -30,6 +30,10 @@ properties: - const: thead,c900-aclint-sswi - items: - const: mips,p8700-aclint-sswi + - items: + - enum: + - anlogic,dr1v90-aclint-sswi + - const: nuclei,ux900-aclint-sswi =20 reg: maxItems: 1 --=20 2.51.1 From nobody Wed Dec 17 18:14:10 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1A922DC78A; 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a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External Add MTIMER support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a TIMER unit compliant with the ACLINT specification. Signed-off-by: Junhui Liu Acked-by: Rob Herring (Arm) --- .../bindings/timer/thead,c900-aclint-mtimer.yaml | 17 +++++++++++--= ---- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtim= er.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.= yaml index 4ed30efe40525f9e70b7f1b1dda1c833b0c3a40c..cf7c82e980f674afcf59fc72674= 2dc4f49c1a820 100644 --- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml +++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml @@ -4,18 +4,23 @@ $id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Sophgo CLINT Timer +title: ACLINT Machine-level Timer Device =20 maintainers: - Inochi Amaoto =20 properties: compatible: - items: - - enum: - - sophgo,sg2042-aclint-mtimer - - sophgo,sg2044-aclint-mtimer - - const: thead,c900-aclint-mtimer + oneOf: + - items: + - enum: + - sophgo,sg2042-aclint-mtimer + - sophgo,sg2044-aclint-mtimer + - const: thead,c900-aclint-mtimer + - items: + - enum: + - anlogic,dr1v90-aclint-mtimer + - const: nuclei,ux900-aclint-mtimer =20 reg: items: --=20 2.51.1 From nobody Wed Dec 17 18:14:10 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FBAD32D0F9; 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a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External The Anlogic DR1V90 SoC integrates a UART controller compatible with snps,dw-apb-uart, operating at a 50 MHz clock. Acked-by: Rob Herring (Arm) Signed-off-by: Junhui Liu --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index cb9da6c97afcfd27a315414959b2b17beb4454cf..691bd0bac6be449516e213b5504= 15acd37badad6 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -51,6 +51,7 @@ properties: - const: renesas,rzn1-uart - items: - enum: + - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart - rockchip,px30-uart --=20 2.51.1 From nobody Wed Dec 17 18:14:10 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7533F313539; 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a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External Reuse the generic ACLINT SSWI probe for Nuclei UX900 since it is compliant with the ACLINT specification. Signed-off-by: Junhui Liu --- drivers/irqchip/irq-aclint-sswi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-aclint-sswi.c b/drivers/irqchip/irq-aclint= -sswi.c index 93e28e9f281f64da4568be37dc57b414354c3f56..fee30f3bc5ac252b236078bf13d= f8c04e7327eaf 100644 --- a/drivers/irqchip/irq-aclint-sswi.c +++ b/drivers/irqchip/irq-aclint-sswi.c @@ -175,7 +175,8 @@ static int __init generic_aclint_sswi_early_probe(struc= t device_node *node, { return generic_aclint_sswi_probe(&node->fwnode); } -IRQCHIP_DECLARE(generic_aclint_sswi, "mips,p8700-aclint-sswi", generic_acl= int_sswi_early_probe); +IRQCHIP_DECLARE(mips_p8700_sswi, "mips,p8700-aclint-sswi", generic_aclint_= sswi_early_probe); +IRQCHIP_DECLARE(nuclei_ux900_sswi, "nuclei,ux900-aclint-sswi", generic_acl= int_sswi_early_probe); =20 /* THEAD variant */ #define THEAD_C9XX_CSR_SXSTATUS 0x5c0 --=20 2.51.1 From nobody Wed Dec 17 18:14:10 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5593C32B9AD; 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a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External The first SoC in the Anlogic series is DR1V90, which contains a RISC-V core from Nuclei. Acked-by: Conor Dooley Signed-off-by: Junhui Liu --- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 848e7149e4435ad3ca138b62bc3b3c8efb594a18..25f7e58cbf745a78b0e946749aa= 2a770dae3eb2b 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -7,6 +7,11 @@ config ARCH_ANDES help This enables support for Andes SoC platform hardware. =20 +config ARCH_ANLOGIC + bool "Anlogic SoCs" + help + This enables support for Anlogic SoC platform hardware. + config ARCH_ESWIN bool "ESWIN SoCs" help --=20 2.51.1 From nobody Wed Dec 17 18:14:10 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21EDE2E7637; Tue, 21 Oct 2025 09:48:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; 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a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External DR1V90 is a FPSoC from Anlogic, which features a RISC-V core as the PS part and 94,464 LUTs for the PL part. The PS part integrates a Nuclei UX900 RISC-V core with 32KB L1 icache and 32KB L1 dcache. It also provides two "snps,dw-apb-uart" compatible UART controllers. Some basic information of the processor can be obtained by running a simple application from nuclei-sdk [1]: Acked-by: Conor Dooley -----Nuclei RISC-V CPU Configuration Information----- MARCHID: 0xc900 MIMPID: 0x20300 ISA: RV64 A B C D F I M P S U MCFG: TEE ECC ECLIC PLIC PPI ILM DLM ICACHE DCACHE IREGION No-S= afety-Mechanism DLEN=3DVLEN/2 ILM: 256 KB has-ecc DLM: 256 KB has-ecc ICACHE: 32 KB(set=3D256,way=3D2,lsize=3D64,ecc=3D1) DCACHE: 32 KB(set=3D256,way=3D2,lsize=3D64,ecc=3D1) TLB: MainTLB(set=3D32,way=3D2,entry=3D1,ecc=3D1) ITLB(entry=3D= 8) DTLB(entry=3D8) IREGION: 0x68000000 128 MB Unit Size Address INFO 64KB 0x68000000 DEBUG 64KB 0x68010000 ECLIC 64KB 0x68020000 TIMER 64KB 0x68030000 PLIC 64MB 0x6c000000 INFO-Detail: mpasize : 0 PPI: 0xf8000000 128 MB -----End of Nuclei CPU INFO----- Link: https://github.com/Nuclei-Software/nuclei-sdk/blob/master/application= /baremetal/cpuinfo/main.c [1] Acked-by: Conor Dooley Signed-off-by: Junhui Liu --- arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 100 ++++++++++++++++++++++++++++= ++++ 1 file changed, 100 insertions(+) diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/= anlogic/dr1v90.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..a5d0765ade3231ece0afbe8835d= 95cd918a44ad9 --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Junhui Liu + */ + +/dts-v1/; +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "Anlogic DR1V90"; + compatible =3D "anlogic,dr1v90"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <800000000>; + + cpu@0 { + compatible =3D "nuclei,ux900", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <32768>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <32768>; + mmu-type =3D "riscv,sv39"; + reg =3D <0>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zba", "zbb", "z= bc", + "zbkc", "zbs", "zicntr", "zicsr", "zifencei", + "zihintpause", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + aclint_mswi: interrupt-controller@68031000 { + compatible =3D "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi"; + reg =3D <0x0 0x68031000 0x0 0x4000>; + interrupts-extended =3D <&cpu0_intc 3>; + }; + + aclint_mtimer: timer@68035000 { + compatible =3D "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mti= mer"; + reg =3D <0x0 0x68035000 0x0 0x8000>; + reg-names =3D "mtimecmp"; + interrupts-extended =3D <&cpu0_intc 7>; + }; + + aclint_sswi: interrupt-controller@6803d000 { + compatible =3D "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi"; + reg =3D <0x0 0x6803d000 0x0 0x3000>; + #interrupt-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 1>; + }; + + plic: interrupt-controller@6c000000 { + compatible =3D "anlogic,dr1v90-plic", "sifive,plic-1.0.0"; + reg =3D <0x0 0x6c000000 0x0 0x4000000>; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; + riscv,ndev =3D <150>; + }; + + uart0: serial@f8400000 { + compatible =3D "anlogic,dr1v90-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xf8400000 0x0 0x1000>; + clock-frequency =3D <50000000>; + interrupts =3D <71>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart1: serial@f8401000 { + compatible =3D "anlogic,dr1v90-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xf8401000 0x0 0x1000>; + clock-frequency =3D <50000000>; + interrupts =3D <72>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + }; +}; --=20 2.51.1 From nobody Wed Dec 17 18:14:10 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7191229B239; Tue, 21 Oct 2025 09:46:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761040002; cv=pass; b=BXXsYjQRhepHwten9TwabdTtA+Fst8wYKlBr0DFLc4lapyOFXXEQi0U4ohxu21j80TKqwpGG9bOsM3lmgOeVjSkuDkCp257Bi3ZOLeB0lHDn6Sjzjum43NRCxdAphe0WBtTmcWJNDqHEz+UBe8H/6RyuhjFzI/8P6qDgfYbKlA8= ARC-Message-Signature: i=2; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=H+eMBBkV2gpXvNgn8yFU/q7nZdubw5xRnI77G7gXhG4=; b=nb+f+Ys2uIC0fM1SMUWVlNvP47iOeuj14kSQBzpaockLbaV5Oc/kd/VwsmkmfNZq culKlyxfi8e7xdDEgpy7oLPgfa//2SQ5vQoTH1hk7WsqcWZJObRSsdbFqFTGmb7JIiu jGI9aDCFBEtAnj0GC71QAMxY1YnWnhgiwCcJxx6o= Received: by mx.zohomail.com with SMTPS id 1761039968011168.45824276802966; Tue, 21 Oct 2025 02:46:08 -0700 (PDT) From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:47 +0800 Subject: [PATCH v3 12/13] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-dr1v90-basic-dt-v3-12-5478db4f664a@pigmoral.tech> References: <20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech> In-Reply-To: <20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Junhui Liu , Thomas Gleixner , Samuel Holland , Chen Wang , Inochi Amaoto , Daniel Lezcano , Greg Kroah-Hartman , Jiri Slaby Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, Inochi Amaoto , sophgo@lists.linux.dev, linux-serial@vger.kernel.org, Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761039846; l=2327; i=junhui.liu@pigmoral.tech; s=20250910; h=from:subject:message-id; bh=BPu7PZHsmHBUMlie/QnSS8N1/X8qLG491ihCDKtsmOU=; b=7eR/LC6zMkMuMsDnYtWYrs2FTA9z8RVgINFgQaKWQS6fX4GyNI2yCGvrba/0PAwR2/FhS2PAI 7lEielyiC88AayBkypc6Aavjw1189HglswXCopzj7+s/I3wqYr9Q1/5 X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External Add support for the Milianke MLKPAI FS01 board based on the Anlogic DR1V90 SoC. The board features 512MB of onboard memory, USB-C UART, 1GbE RJ45 Ethernet, USB-A 2.0 port, TF card slot, and 256Mbit Quad-SPI flash. Currently, the board can boot to a console via UART1, which is connected to the onboard serial chip and routed to the Type-C interface. Acked-by: Conor Dooley Signed-off-by: Junhui Liu --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/anlogic/Makefile | 2 ++ arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 28 ++++++++++++++++++= ++++ 3 files changed, 31 insertions(+) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 3763d199c70ac659d00948241f4263dec62c548c..f99d38ee1aad255557ed6984f72= 5f15df791690e 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y +=3D allwinner subdir-y +=3D andes +subdir-y +=3D anlogic subdir-y +=3D canaan subdir-y +=3D eswin subdir-y +=3D microchip diff --git a/arch/riscv/boot/dts/anlogic/Makefile b/arch/riscv/boot/dts/anl= ogic/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..87f3b2f418cfa32012df5ae82d1= 7262a9610f90c --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ANLOGIC) +=3D dr1v90-mlkpai-fs01.dtb diff --git a/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts b/arch/risc= v/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts new file mode 100644 index 0000000000000000000000000000000000000000..597407655efd2e74608dabb4559= ab1239662cf41 --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Junhui Liu + */ + +#include "dr1v90.dtsi" + +/ { + model =3D "Milianke MLKPAI-FS01"; + compatible =3D "milianke,mlkpai-fs01", "anlogic,dr1v90"; + + aliases { + serial0 =3D &uart1; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x20000000>; + }; +}; + +&uart1 { + status =3D "okay"; +}; --=20 2.51.1 From nobody Wed Dec 17 18:14:10 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FEEB23BF9C; Tue, 21 Oct 2025 09:46:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761040004; cv=pass; b=dxR+BhQGkEjy4cc846K5QSIlvoeYKpt/UXfZONiROw6h0dmMf6GdK7xnFIQIPTFJsffFYr/nUUIvboQAUQZsSIpfgiBAUTcQ89xaqkgOovoLL571X7lB/jOR+j7IC1L53j2pwSRtDsUs5JcGd/luTj999z8zomkn8tCZNRk+Pes= ARC-Message-Signature: i=2; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=fM/OFmnj6so77IHYlA1fi4R93kba5pRm23lZo7zfC2g=; b=j/wRoNwRzVGbWhyuuP5wJ3+hG3OY9kc3SreZFpaBr4/jbGPhMn7jTBQ2y+3Hv+Cp 85XjVIultHSc8GviJdenuXONcPaoR2EgMkEZlQ3NQDYnFvHyvq2GjqLwcKgoWESueDv aiyk8lQaaJmxGr6YzuTNs8eftvSZUw4yR2e9RlO8= Received: by mx.zohomail.com with SMTPS id 176103997777640.235295843942595; Tue, 21 Oct 2025 02:46:17 -0700 (PDT) From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:48 +0800 Subject: [PATCH v3 13/13] riscv: defconfig: Enable Anlogic SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-dr1v90-basic-dt-v3-13-5478db4f664a@pigmoral.tech> References: <20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech> In-Reply-To: <20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Junhui Liu , Thomas Gleixner , Samuel Holland , Chen Wang , Inochi Amaoto , Daniel Lezcano , Greg Kroah-Hartman , Jiri Slaby Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, Inochi Amaoto , sophgo@lists.linux.dev, linux-serial@vger.kernel.org, Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761039846; l=773; i=junhui.liu@pigmoral.tech; s=20250910; h=from:subject:message-id; bh=BT1BbYf1Y5yXL3hJlz/v6ZRCueJkWknoQha5McKnBcs=; b=jcnGaIRVMmeBHgf8lPTP3BWGl5CDI1pC/z14YdPdQ5DLNGbyxSnAFXo+G1X3o/6cqyFe0nlOZ 6vuZFktycyWCCFp4fUDiPh/HVNOxMJAchZ3OH302AXEO3yUlN118mig X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External Enable Anlogic SoC config in defconfig to allow the default upstream kernel booting on Milianke MLKPAI-FS01 board. Acked-by: Conor Dooley Signed-off-by: Junhui Liu --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index fc2725cbca1879c181d179a3d59ac3a0ce206061..14b82f770efe1dc8abe1ef68b52= 3023d89d1f4e5 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -23,6 +23,7 @@ CONFIG_CHECKPOINT_RESTORE=3Dy CONFIG_BLK_DEV_INITRD=3Dy CONFIG_PROFILING=3Dy CONFIG_ARCH_ANDES=3Dy +CONFIG_ARCH_ANLOGIC=3Dy CONFIG_ARCH_MICROCHIP=3Dy CONFIG_ARCH_SIFIVE=3Dy CONFIG_ARCH_SOPHGO=3Dy --=20 2.51.1