From nobody Tue Feb 10 14:33:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A86E43B186; Tue, 21 Oct 2025 03:18:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761016708; cv=none; b=BcJzOFma2uYbsjOtQ0qy8jNTaGay/QVhyEu3NRP3WzYBtH76euNwBcv8pBJZx50/95cVLDuKYze+dBdB5fV0WAXHnKcG6ye62Zrk0zs8U8eBhe+rkMs1YEOsQYiyVj6Vm1KjO3xJWpsG696nGTGNHjY8WSoWxGkZO/itpTmH2oE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761016708; c=relaxed/simple; bh=UUY6EoYpN5OSQ7MrdJRUOxsyjYyRvZLH0j5SDnfFt2s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BBNuZsvpbrWZh2+N84k20yg2XdWrrgLtOZH+4WDQ6j/Y4by1ajmMWjd1+n1vfQC04hUayAFsBwsJhC7g5rEzQrw9c0/Mj734AzZuIT5Ow9XoPoxwXPCP/C4NgElJg1X3KGdTsKW7g0YCsiq4y+/teTNb/AOO0gN3rPt2IyKgYVk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Fzlyf6Wm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Fzlyf6Wm" Received: by smtp.kernel.org (Postfix) with ESMTPS id 45C40C116D0; Tue, 21 Oct 2025 03:18:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761016708; bh=UUY6EoYpN5OSQ7MrdJRUOxsyjYyRvZLH0j5SDnfFt2s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Fzlyf6Wm3D/CU/TN0E2LWk2ScQBAC5yCwdcR5WYBK3x7ZcKFJ0M1VXc+tMNjgacJo Q2j5aXihUZWPa6pnf0hw02HRREPtmKQMB9iWOOFm+ht4S7oUs1FkdqntlRxvRvdOAD XyD5oxGQR3wfDtOl4oB/Z1bKKU2j22hyyOlWKTMLrWr4Dva4xK5uXLar/lRoL6CKZA YHZlzFhZ2H3ZYexTW/bZV6BmbBgdkNEWYVAxt95H9wIVRbfY1VoWZ/iM+iB0bmOtTi osxThcisz3o+Tl1zDxIoI6g6agLzkSPAO2ARKNebnFcyQXoHhRRnG5RfyzN3qewUv3 5TUWE43qtTlyw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30B5ECCD1AB; Tue, 21 Oct 2025 03:18:28 +0000 (UTC) From: Xiangxu Yin via B4 Relay Date: Tue, 21 Oct 2025 11:18:08 +0800 Subject: [PATCH v5 2/3] arm64: dts: qcom: Add DisplayPort and QMP USB3DP PHY for SM6150 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251021-add-displayport-support-to-qcs615-devicetree-v5-2-92f0f3bf469f@oss.qualcomm.com> References: <20251021-add-displayport-support-to-qcs615-devicetree-v5-0-92f0f3bf469f@oss.qualcomm.com> In-Reply-To: <20251021-add-displayport-support-to-qcs615-devicetree-v5-0-92f0f3bf469f@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, Xiangxu Yin , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761016706; l=4863; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=3pSnnrGEXb0IZPs2HywPsZBSwVxQ7CaQz8jbYhQYYEU=; b=pMik0LlYG5czsdbF2UCnwWhBWlt9bnXJMnooakS3xAOXP/VB5b+nBIyhMJErfpoCv0Cjj63Oe XFHtWYFEW1gDAVEiu14sB5UmBgv9/uA+HPdyRZSPgCFZgrNo0ykU5/U X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Endpoint-Received: by B4 Relay for xiangxu.yin@oss.qualcomm.com/20241125 with auth_id=542 X-Original-From: Xiangxu Yin Reply-To: xiangxu.yin@oss.qualcomm.com From: Xiangxu Yin Introduce DisplayPort controller node and associated QMP USB3-DP PHY for SM6150 SoC. Add data-lanes property to the DP endpoint and update clock assignments for proper DP integration. Reviewed-by: Dmitry Baryshkov Signed-off-by: Xiangxu Yin Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 113 +++++++++++++++++++++++++++++++= +++- 1 file changed, 111 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qco= m/sm6150.dtsi index 6128d8c48f9c0807ac488ddac3b2377678e8f8c3..7ec80c5719f0d2c1cb75fd36bc3= 1f4e5eb7e7e24 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -3717,6 +3718,7 @@ port@0 { reg =3D <0>; =20 dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; }; }; =20 @@ -3749,6 +3751,87 @@ opp-307200000 { }; }; =20 + mdss_dp0: displayport-controller@ae90000 { + compatible =3D "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp"; + + reg =3D <0x0 0x0ae90000 0x0 0x200>, + <0x0 0x0ae90200 0x0 0x200>, + <0x0 0x0ae90400 0x0 0x600>, + <0x0 0x0ae90a00 0x0 0x600>, + <0x0 0x0ae91000 0x0 0x600>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <12>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys =3D <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dp0_out: endpoint { + data-lanes =3D <3 2 0 1>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible =3D "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg =3D <0x0 0x0ae94000 0x0 0x400>; @@ -3844,8 +3927,8 @@ dispcc: clock-controller@af00000 { <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, - <0>, - <0>; + <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; =20 #clock-cells =3D <1>; #reset-cells =3D <1>; @@ -4214,6 +4297,32 @@ usb_qmpphy: phy@88e6000 { status =3D "disabled"; }; =20 + usb_qmpphy_2: phy@88e8000 { + compatible =3D "qcom,qcs615-qmp-usb3-dp-phy"; + reg =3D <0x0 0x088e8000 0x0 0x2000>; + + clocks =3D <&gcc GCC_USB2_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>, + <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets =3D <&gcc GCC_USB3PHY_PHY_SEC_BCR >, + <&gcc GCC_USB3_DP_PHY_SEC_BCR>; + reset-names =3D "phy_phy", + "dp_phy"; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + qcom,tcsr-reg =3D <&tcsr 0xbff0 0xb24c>; + + status =3D "disabled"; + }; + usb_1: usb@a6f8800 { compatible =3D "qcom,qcs615-dwc3", "qcom,dwc3"; reg =3D <0x0 0x0a6f8800 0x0 0x400>; --=20 2.34.1