From nobody Sat Feb 7 18:55:36 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A90B333755; Mon, 20 Oct 2025 21:20:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760995230; cv=none; b=tMg/JXet+CJHClhkABPXK52eeCYPLnZx23rTWqZHB5eLRvH/AFS+YnPdyEdHRIfiNLqhM47qMdPdc+EsukesVFjD1om7Y3iETkYn/ACba3cb4LrU63WZNwOTS2fdWC1cqNCA2APGNvMr3pmhrRBUbnkk7GTz96BjzB+Cckzp29I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760995230; c=relaxed/simple; bh=7PC6JHtD5/xPy2Ey7TaucbPgSAi+lFZoa3bDhNA91IY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tlinefB1hRfm6IBHpEKITBtB1X0c5pqRDc12N1oY2uNDZ8Wy4e1n+54u0LZ0Hss8Yd61I2Xvcvr97LjD9tjvqmAcW4iN6YrShR1Ho/EJdiY5TljH2niYZKJu/wiQ2Ry1jB+WSOXw8iMpRrpQXrlboZnuu8n4s91aje23cguIO54= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=fnJ7Qxwu; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="fnJ7Qxwu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1760995226; bh=7PC6JHtD5/xPy2Ey7TaucbPgSAi+lFZoa3bDhNA91IY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fnJ7QxwuQI+5vZ3jGmQUj55/483QdNSBgF5l43Mi+EEwpDi2ZICQsgUilxUC7J6IM nbum5eWpUZyy/rlc2JsZ692YIfPnq45hiOYXIrrkKuXNJq+TIBDsqezToc78YhitIR ygTpmY2a1dvcH3mMdn2h9fh+tFwzjnXxiJfRdGMm/z1Qa+ujre3z1fuf12jhhhg5Zs fvDyPodwjKyyQbs9zlycAiw2CjbtZzuU3/yzte4i01R7xsMs9W6dXOgtk46GNeuoOD rBwIz6NRtmtR6f/B06Gai8UVSJ6IZe1aI29wlnQFWoEWzlIrl7AqOfnl6XH88VAMYj NOb3Tznv9Igcg== Received: from trenzalore (unknown [23.233.251.139]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by bali.collaboradmins.com (Postfix) with ESMTPSA id 732BC17E0456; Mon, 20 Oct 2025 23:20:23 +0200 (CEST) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Nicolas Frattaroli , Kever Yang , Detlev Casanova , Shawn Lin , Cristian Ciocaltea , Sebastian Reichel , Tomeu Vizoso , Dragan Simic , Damon Ding , Alexey Charkov , Chukun Pan , Patrick Wildt , Diederik de Haas , Chris Morgan , Alexander Shiyan , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com Subject: [PATCH v3 1/2] arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588 Date: Mon, 20 Oct 2025 17:20:08 -0400 Message-ID: <20251020212009.8852-2-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.51.1.dirty In-Reply-To: <20251020212009.8852-1-detlev.casanova@collabora.com> References: <20251020212009.8852-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vdpu381 Video Decoders to the rk3588-base devicetree. The RK3588 based SoCs all embed 2 vdpu381 decoders. This also adds the dedicated IOMMU controllers. Signed-off-by: Detlev Casanova --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index e2500e31c434..d076267a330b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1353,6 +1353,70 @@ vepu121_3_mmu: iommu@fdbac800 { #iommu-cells =3D <0>; }; =20 + vdec0: video-codec@fdc38000 { + compatible =3D "rockchip,rk3588-vdec"; + reg =3D <0x0 0xfdc38100 0x0 0x500>, + <0x0 0xfdc38000 0x0 0x100>, + <0x0 0xfdc38600 0x0 0x100>; + reg-names =3D "function", "link", "cache"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_C= A>, + <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; + clock-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks =3D <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, + <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; + assigned-clock-rates =3D <800000000>, <600000000>, + <600000000>, <1000000000>; + iommus =3D <&vdec0_mmu>; + power-domains =3D <&power RK3588_PD_RKVDEC0>; + resets =3D <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVD= EC0_CA>, + <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; + reset-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram =3D <&vdec0_sram>; + }; + + vdec0_mmu: iommu@fdc38700 { + compatible =3D "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; + clock-names =3D "aclk", "iface"; + power-domains =3D <&power RK3588_PD_RKVDEC0>; + #iommu-cells =3D <0>; + }; + + vdec1: video-codec@fdc40000 { + compatible =3D "rockchip,rk3588-vdec"; + reg =3D <0x0 0xfdc40100 0x0 0x500>, + <0x0 0xfdc40000 0x0 0x100>, + <0x0 0xfdc40600 0x0 0x100>; + reg-names =3D "function", "link", "cache"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_C= A>, + <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; + clock-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks =3D <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, + <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; + assigned-clock-rates =3D <800000000>, <600000000>, + <600000000>, <1000000000>; + iommus =3D <&vdec1_mmu>; + power-domains =3D <&power RK3588_PD_RKVDEC1>; + resets =3D <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVD= EC1_CA>, + <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; + reset-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram =3D <&vdec1_sram>; + }; + + vdec1_mmu: iommu@fdc40700 { + compatible =3D "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; + clock-names =3D "aclk", "iface"; + power-domains =3D <&power RK3588_PD_RKVDEC1>; + #iommu-cells =3D <0>; + }; + av1d: video-codec@fdc70000 { compatible =3D "rockchip,rk3588-av1-vpu"; reg =3D <0x0 0xfdc70000 0x0 0x800>; @@ -3248,6 +3312,16 @@ system_sram2: sram@ff001000 { ranges =3D <0x0 0x0 0xff001000 0xef000>; #address-cells =3D <1>; #size-cells =3D <1>; + + vdec0_sram: codec-sram@0 { + reg =3D <0x0 0x78000>; + pool; + }; + + vdec1_sram: codec-sram@78000 { + reg =3D <0x78000 0x77000>; + pool; + }; }; =20 pinctrl: pinctrl { --=20 2.51.1.dirty From nobody Sat Feb 7 18:55:36 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68923333748; Mon, 20 Oct 2025 21:20:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760995233; cv=none; b=aBNIArJ1ImeHgRrs7C4wqsIl/WglNk9IsNg8KIdOexxdj5E/S40UTO/lwHotRfONzWbRCTbLKb6ikUtzUMBr08E7qpt59nKA5+5BcQudabGBM7jSf3kiM95BjCSb4nh5LSHXDOXw9O5THIJQbKzfrGV83ohGup89We3riW+a3B4= ARC-Message-Signature: i=1; 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charset="utf-8" Add the vdpu383 Video Decoder variant to the RK3576 device tree. Also allow using the dedicated SRAM as a pool. Signed-off-by: Detlev Casanova --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index fc4e9e07f1cf..00999823746f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1289,6 +1289,41 @@ gpu: gpu@27800000 { status =3D "disabled"; }; =20 + vdec: video-codec@27b00000 { + compatible =3D "rockchip,rk3576-vdec"; + reg =3D <0x0 0x27b00100 0x0 0x500>, + <0x0 0x27b00000 0x0 0x100>, + <0x0 0x27b00600 0x0 0x100>; + reg-names =3D "function", "link", "cache"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, + <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_HEVC_CA>; + clock-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks =3D <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>, + <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates =3D <600000000>, <600000000>, + <500000000>, <1000000000>; + iommus =3D <&vdec_mmu>; + power-domains =3D <&power RK3576_PD_VDEC>; + resets =3D <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>, + <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>, + <&cru SRST_RKVDEC_HEVC_CA>; + reset-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram =3D <&rkvdec_sram>; + }; + + vdec_mmu: iommu@27b00800 { + compatible =3D "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>; + interrupts =3D ; + clocks =3D <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>; + clock-names =3D "aclk", "iface"; + power-domains =3D <&power RK3576_PD_VDEC>; + rockchip,disable-mmu-reset; + #iommu-cells =3D <0>; + }; + vop: vop@27d00000 { compatible =3D "rockchip,rk3576-vop"; reg =3D <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; @@ -2694,6 +2729,7 @@ sram: sram@3ff88000 { /* start address and size should be 4k align */ rkvdec_sram: rkvdec-sram@0 { reg =3D <0x0 0x78000>; + pool; }; }; =20 --=20 2.51.1.dirty