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charset="utf-8" Fix two grammatical errors in the Rust coding guidelines document. Signed-off-by: Joel Fernandes Reviewed-by: John Hubbard --- Documentation/rust/coding-guidelines.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/rust/coding-guidelines.rst b/Documentation/rust/= coding-guidelines.rst index 6ff9e754755d..d556f0db042b 100644 --- a/Documentation/rust/coding-guidelines.rst +++ b/Documentation/rust/coding-guidelines.rst @@ -97,7 +97,7 @@ should still be used. For instance: // TODO: ... fn f() {} =20 -One special kind of comments are the ``// SAFETY:`` comments. These must a= ppear +One special kind of comment is the ``// SAFETY:`` comment. These must appe= ar before every ``unsafe`` block, and they explain why the code inside the bl= ock is correct/sound, i.e. why it cannot trigger undefined behavior in any case, = e.g.: =20 @@ -166,7 +166,7 @@ in the kernel: - While not shown here, if a function may panic, the conditions under which that happens must be described under a ``# Panics`` section. =20 - Please note that panicking should be very rare and used only with a good + Please note that panicking should be very rare and used only for a good reason. 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charset="utf-8" To support the usecase where we read a register and write to another with identical bit layout, add support to convert bitfield to underlying ty= pe. Another way to do this, is to read individual fields, on the caller side, and write to the destination fields, but that is both cumbersome and error-prone as new bits added in hardware may be missed. Signed-off-by: Joel Fernandes Reviewed-by: John Hubbard --- drivers/gpu/nova-core/bitfield.rs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/nova-core/bitfield.rs b/drivers/gpu/nova-core/bitf= ield.rs index 0994505393dd..2266abc3f7ab 100644 --- a/drivers/gpu/nova-core/bitfield.rs +++ b/drivers/gpu/nova-core/bitfield.rs @@ -72,6 +72,7 @@ /// - Field setters: `set_mode()`, `set_state()`, etc. (supports chaining = with builder pattern). /// Note that the compiler will error out if the size of the setter's ar= g exceeds the /// struct's storage size. +/// - Conversion from the underlying storage type (e.g., `From`). /// - Debug and Default implementations. /// /// Note: Field accessors and setters inherit the same visibility as the s= truct itself. @@ -117,6 +118,12 @@ fn from(val: $name) -> $storage { } } =20 + impl ::core::convert::From<$storage> for $name { + fn from(val: $storage) -> $name { + $name(val) + } + } + bitfield!(@fields_dispatcher $vis $name $storage { $($fields)* }); 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charset="utf-8" Document the GSP RPC message queue architecture in detail. Signed-off-by: Joel Fernandes --- Documentation/gpu/nova/core/msgq.rst | 159 +++++++++++++++++++++++++++ Documentation/gpu/nova/index.rst | 1 + 2 files changed, 160 insertions(+) create mode 100644 Documentation/gpu/nova/core/msgq.rst diff --git a/Documentation/gpu/nova/core/msgq.rst b/Documentation/gpu/nova/= core/msgq.rst new file mode 100644 index 000000000000..84e25be69cd6 --- /dev/null +++ b/Documentation/gpu/nova/core/msgq.rst @@ -0,0 +1,159 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Nova GPU RPC Message Passing Architecture +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +.. note:: + The following description is approximate and current as of the Ampere f= amily. + It may change for future generations and is intended to assist in under= standing + the driver code. + +Overview +=3D=3D=3D=3D=3D=3D=3D=3D + +The Nova GPU driver communicates with the GSP (GPU System Processor) firmw= are +using an RPC (Remote Procedure Call) mechanism built on top of circular me= ssage +queues in shared memory. This document describes the structure of RPC mess= ages +and the mechanics of the message passing system. + +Message Queue Architecture +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D + +The communication between CPU and GSP uses two unidirectional circular que= ues: + +1. **CPU Queue (cpuq)**: CPU writes, GSP reads +2. **GSP Queue (gspq)**: GSP writes, CPU reads + +The advantage of this approach is no synchronization is required to access= the +queues, if one entity wants to communicate with the other (CPU or GSP), th= ey +simply write into their own queue. + +Memory Layout +------------- + +The shared memory region (GspMem) where the queues reside has the following +layout:: + + +------------------------+ GspMem DMA Handle (base address) + | PTE Array (4KB) | <- Self-mapping page table + | PTE[0] =3D base + 0x0000 | Points to this page + | PTE[1] =3D base + 0x1000 | Points to CPU queue Header page + | PTE[2] =3D base + 0x2000 | Points to first page of CPU queue data + | ... | ... + | ... | ... + +------------------------+ base + 0x1000 + | CPU Queue Header | MsgqTxHeader + MsgqRxHeader + | - TX Header (32B) | + | - RX Header (4B) | (1 page) + | - Padding | + +------------------------+ base + 0x2000 + | CPU Queue Data | (63 pages) + | (63 x 4KB pages) | Circular buffer for messages + | ... | ... + +------------------------+ base + 0x41000 + | GSP Queue Header | MsgqTxHeader + MsgqRxHeader + | - TX Header (32B) | + | - RX Header (4B) | (1 page) + | - Padding | + +------------------------+ base + 0x42000 + | GSP Queue Data | (63 pages) + | (63 x 4KB pages) | Circular buffer for messages + | ... | ... + +------------------------+ base + 0x81000 + + +Message Passing Mechanics +------------------------- +The split read/write pointer design allows bidirectional communication bet= ween the +CPU and GSP without synchronization (if it were a shared queue), for examp= le, the +following diagram illustrates pointer updates, when CPU sends message to G= SP:: + + +---------------------------------------------------------------------= -----+ + | DMA coherent Shared Memory (GspMem) = | + +---------------------------------------------------------------------= -----+ + | (CPU sending message to GSP) = | + | +-------------------+ +-------------------+ = | + | | GSP Queue | | CPU Queue | = | + | | | | | = | + | | +-------------+ | | +-------------+ | = | + | | | TX Header | | | | TX Header | | = | + | | | write_ptr | | | | write_ptr |---+---= -, | + | | | | | | | | | = | | + | | +-------------+ | | +-------------+ | = | | + | | | | | = | | + | | +-------------+ | | +-------------+ | = | | + | | | RX Header | | | | RX Header | | = | | + | | | read_ptr ------+-------, | | read_ptr | | = | | + | | | | | | | | | | = | | + | | +-------------+ | | | +-------------+ | = | | + | | | | | | = | | + | | +-------------+ | | | +-------------+ | = | | + | | | Page 0 | | | | | Page 0 | | = | | + | | +-------------+ | | | +-------------+ | = | | + | | | Page 1 | | `--------------> | Page 1 | | = | | + | | +-------------+ | | +-------------+ | = | | + | | | Page 2 | | | | Page 2 |<--+---= -' | + | | +-------------+ | | +-------------+ | = | + | | | ... | | | | ... | | = | + | | +-------------+ | | +-------------+ | = | + | | | Page 62 | | | | Page 62 | | = | + | | +-------------+ | | +-------------+ | = | + | | (63 pages) | | (63 pages) | = | + | +-------------------+ +-------------------+ = | + | = | + +---------------------------------------------------------------------= -----+ + +When the CPU sends a message to the GSP, it writes the message to its own +queue (CPU queue) and updates the write pointer in its queue's TX header. = The GSP +then reads the read pointer in its own queue's RX header and knows that th= ere are +pending messages from the CPU because its RX header's read pointer is behi= nd the +CPU's TX header's write pointer. After reading the message, the GSP update= s its RX +header's read pointer to catch up. The same happens in reverse. + +Page-based message passing +-------------------------- +The message queue is page-based, which means that the message is stored in= a +page-aligned buffer. The page size is 4KB. Each message starts at the begi= nning of +a page. If the message is shorter than a page, the remaining space in the = page is +wasted. The next message starts at the beginning of the next page no matte= r how +small the previous message was. + +Note that messages larger than a page will span multiple pages. This means= that +it is possible that the first part of the message lands on the last page, = and the +second part of the message lands on the first page, thus requiring out-of-= order +memory access. The SBuffer data structure in Nova tackles this use case. + +RPC Message Structure: +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +An RPC message is also called a "Message Element". The entire message has +multiple headers. There is a "message element" header which handles message +queue specific details and integrity, followed by a "RPC" header which han= dles +the RPC protocol details:: + + +----------------------------------+ + | GspMsgHeader (64B) | (aka, Message Element Header) + +----------------------------------+ + | auth_tag_buffer[16] | --+ + | aad_buffer[16] | | + | checksum (u32) | +-- Security & Integrity + | sequence (u32) | | + | elem_count (u32) | | + | pad (u32) | --+ + +----------------------------------+ + | GspRpcHeader (32B) | + +----------------------------------+ + | header_version (0x03000000) | --+ + | signature (0x43505256) | | + | length (u32) | +-- RPC Protocol + | function (u32) | | + | rpc_result (u32) | | + | rpc_result_private (u32) | | + | sequence (u32) | | + | cpu_rm_gfid (u32) | --+ + +----------------------------------+ + | | + | Payload (Variable) | --- Function-specific data + | | + +----------------------------------+ diff --git a/Documentation/gpu/nova/index.rst b/Documentation/gpu/nova/inde= x.rst index e39cb3163581..46302daace34 100644 --- a/Documentation/gpu/nova/index.rst +++ b/Documentation/gpu/nova/index.rst @@ -32,3 +32,4 @@ vGPU manager VFIO driver and the nova-drm driver. core/devinit core/fwsec core/falcon + core/msgq --=20 2.34.1 From nobody Sun Feb 8 06:04:24 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010054.outbound.protection.outlook.com [40.93.198.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA8F632038D; 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charset="utf-8" While not terribly complicated, a little bit of documentation will help augment the code for this very important mechanism. Signed-off-by: Joel Fernandes --- Documentation/gpu/nova/core/pramin.rst | 113 +++++++++++++++++++++++++ Documentation/gpu/nova/index.rst | 1 + 2 files changed, 114 insertions(+) create mode 100644 Documentation/gpu/nova/core/pramin.rst diff --git a/Documentation/gpu/nova/core/pramin.rst b/Documentation/gpu/nov= a/core/pramin.rst new file mode 100644 index 000000000000..19615e504db9 --- /dev/null +++ b/Documentation/gpu/nova/core/pramin.rst @@ -0,0 +1,113 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D +PRAMIN aperture mechanism +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + +.. note:: + The following description is approximate and current as of the Ampere f= amily. + It may change for future generations and is intended to assist in under= standing + the driver code. + +Introduction +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +PRAMIN is a hardware aperture mechanism that provides CPU access to GPU Vi= deo RAM (VRAM) before +the GPU's Memory Management Unit (MMU) and page tables are initialized. Th= is 1MB sliding window, +located at a fixed offset within BAR0, is essential for setting up page ta= bles and other critical +GPU data structures without relying on the GPU's MMU. + +Architecture Overview +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Logically, the PRAMIN aperture mechanism is implemented by the GPU's PBUS = (PCIe Bus Controller Unit) +and provides a CPU-accessible window into VRAM through the PCIe interface:: + + +-----------------+ PCIe +------------------------------+ + | CPU |<----------->| GPU | + +-----------------+ | | + | +----------------------+ | + | | PBUS | | + | | (Bus Controller) | | + | | | | + | | +--------------.<------------ (w= indow always starts at + | | | PRAMIN | | | B= AR0 + 0x700000) + | | | Window | | | + | | | (1MB) | | | + | | +--------------+ | | + | | | | | + | +---------|------------+ | + | | | + | v | + | .----------------------.<----------= -- (Program PRAMIN to any + | | VRAM | | 64= KB VRAM physical boundary) + | | (Several GBs) | | + | | | | + | | FB[0x000000000000] | | + | | ... | | + | | FB[0x7FFFFFFFFFF] | | + | +----------------------+ | + +------------------------------+ + +PBUS (PCIe Bus Controller) among other things is responsible in the GPU fo= r handling MMIO +accesses to the BAR registers. + +PRAMIN Window Operation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The PRAMIN window provides a 1MB sliding aperture that can be repositioned= over +the entire VRAM address space using the NV_PBUS_BAR0_WINDOW register. + +Window Control Mechanism +------------------------- + +The window position is controlled via the PBUS BAR0_WINDOW register:: + + NV_PBUS_BAR0_WINDOW Register + +-----+-----+--------------------------------------+ + |31-26|25-24| 23-0 | + | |TARG | BASE_ADDR | + | | ET | (bits 39:16 of VRAM address) | + +-----+-----+--------------------------------------+ + + TARGET field values: + - 0x0: VID_MEM (Video Memory / VRAM) + - 0x1: SYS_MEM_COHERENT (Coherent system memory) + - 0x2: SYS_MEM_NONCOHERENT (Non-coherent system memory) + +64KB Alignment Requirement +--------------------------- + +The PRAMIN window must be aligned to 64KB boundaries in VRAM. This is enfo= rced +by the BASE_ADDR field representing bits [39:16] of the target address:: + + VRAM Address Calculation: + actual_vram_addr =3D (BASE_ADDR << 16) + pramin_offset + Where: + - BASE_ADDR: 24-bit value from NV_PBUS_BAR0_WINDOW[23:0] + - pramin_offset: 20-bit offset within PRAMIN window [0x00000-0xFFFFF] + Example Window Positioning: + +---------------------------------------------------------+ + | VRAM Space | + | | + | 0x000000000 +-----------------+ <-- 64KB aligned | + | | PRAMIN Window | | + | | (1MB) | | + | 0x0000FFFFF +-----------------+ | + | | + | | ^ | + | | | Window can slide | + | v | to any 64KB boundary | + | | + | 0x123400000 +-----------------+ <-- 64KB aligned | + | | PRAMIN Window | | + | | (1MB) | | + | 0x1234FFFFF +-----------------+ | + | | + | ... | + | | + | 0x7FFFF0000 +-----------------+ <-- 64KB aligned | + | | PRAMIN Window | | + | | (1MB) | | + | 0x7FFFFFFFF +-----------------+ | + +---------------------------------------------------------+ diff --git a/Documentation/gpu/nova/index.rst b/Documentation/gpu/nova/inde= x.rst index 46302daace34..e77d3ee336a4 100644 --- a/Documentation/gpu/nova/index.rst +++ b/Documentation/gpu/nova/index.rst @@ -33,3 +33,4 @@ vGPU manager VFIO driver and the nova-drm driver. core/fwsec core/falcon core/msgq + core/pramin --=20 2.34.1 From nobody Sun Feb 8 06:04:24 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013068.outbound.protection.outlook.com [40.107.201.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22DC5331A77; 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charset="utf-8" Add support for managing GSP falcon interrupts. These are required for GSP message queue interrupt handling. Also rename clear_swgen0_intr() to enable_msq_interrupt() for readability. Signed-off-by: Joel Fernandes Reviewed-by: John Hubbard --- drivers/gpu/nova-core/falcon/gsp.rs | 26 +++++++++++++++++++++++--- drivers/gpu/nova-core/gpu.rs | 2 +- drivers/gpu/nova-core/regs.rs | 10 ++++++++++ 3 files changed, 34 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/fa= lcon/gsp.rs index f17599cb49fa..6da63823996b 100644 --- a/drivers/gpu/nova-core/falcon/gsp.rs +++ b/drivers/gpu/nova-core/falcon/gsp.rs @@ -22,11 +22,31 @@ impl FalconEngine for Gsp { } =20 impl Falcon { - /// Clears the SWGEN0 bit in the Falcon's IRQ status clear register to - /// allow GSP to signal CPU for processing new messages in message que= ue. - pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) { + /// Enable the GSP Falcon message queue interrupt (SWGEN0 interrupt). + #[expect(dead_code)] + pub(crate) fn enable_msgq_interrupt(&self, bar: &Bar0) { + regs::NV_PFALCON_FALCON_IRQMASK::alter(bar, &Gsp::ID, |r| r.set_sw= gen0(true)); + } + + /// Check if the message queue interrupt is pending. + #[expect(dead_code)] + pub(crate) fn has_msgq_interrupt(&self, bar: &Bar0) -> bool { + regs::NV_PFALCON_FALCON_IRQSTAT::read(bar, &Gsp::ID).swgen0() + } + + /// Clears the message queue interrupt to allow GSP to signal CPU + /// for processing new messages. + pub(crate) fn clear_msgq_interrupt(&self, bar: &Bar0) { regs::NV_PFALCON_FALCON_IRQSCLR::default() .set_swgen0(true) .write(bar, &Gsp::ID); } + + /// Acknowledge all pending GSP interrupts. + #[expect(dead_code)] + pub(crate) fn ack_all_interrupts(&self, bar: &Bar0) { + // Read status and write the raw value to IRQSCLR to clear all pen= ding interrupts. + let status =3D regs::NV_PFALCON_FALCON_IRQSTAT::read(bar, &Gsp::ID= ); + regs::NV_PFALCON_FALCON_IRQSCLR::from(u32::from(status)).write(bar= , &Gsp::ID); + } } diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index af20e2daea24..fb120cf7b15d 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -216,7 +216,7 @@ pub(crate) fn new<'a>( bar, spec.chipset > Chipset::GA100, ) - .inspect(|falcon| falcon.clear_swgen0_intr(bar))?, + .inspect(|falcon| falcon.clear_msgq_interrupt(bar))?, =20 sec2_falcon: Falcon::new(pdev.as_ref(), spec.chipset, bar, tru= e)?, =20 diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 206dab2e1335..a3836a01996b 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -198,6 +198,16 @@ pub(crate) fn vga_workspace_addr(self) -> Option { =20 // PFALCON =20 +register!(NV_PFALCON_FALCON_IRQMASK @ PFalconBase[0x00000014] { + 4:4 halt as bool; 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charset="utf-8" Required for writing page tables directly to VRAM physical memory, before page tables and MMU are setup. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/mod.rs | 3 + drivers/gpu/nova-core/mm/pramin.rs | 241 +++++++++++++++++++++++++++++ drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 29 +++- 4 files changed, 273 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nova-core/mm/mod.rs create mode 100644 drivers/gpu/nova-core/mm/pramin.rs diff --git a/drivers/gpu/nova-core/mm/mod.rs b/drivers/gpu/nova-core/mm/mod= .rs new file mode 100644 index 000000000000..54c7cd9416a9 --- /dev/null +++ b/drivers/gpu/nova-core/mm/mod.rs @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0 + +pub(crate) mod pramin; diff --git a/drivers/gpu/nova-core/mm/pramin.rs b/drivers/gpu/nova-core/mm/= pramin.rs new file mode 100644 index 000000000000..4f4e1b8c0b9b --- /dev/null +++ b/drivers/gpu/nova-core/mm/pramin.rs @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Direct VRAM access through PRAMIN window before page tables are set up. +//! PRAMIN can also write to system memory, however for simplicty we only +//! support VRAM access. +//! +//! # Examples +//! +//! ## Writing u32 data to VRAM +//! +//! ```no_run +//! use crate::driver::Bar0; +//! use crate::mm::pramin::PraminVram; +//! +//! fn write_data_to_vram(bar: &Bar0) -> Result { +//! let pramin =3D PraminVram::new(bar); +//! // Write 4 32-bit words to VRAM at offset 0x10000 +//! let data: [u32; 4] =3D [0xDEADBEEF, 0xCAFEBABE, 0x12345678, 0x8765= 4321]; +//! pramin.write::(0x10000, &data)?; +//! Ok(()) +//! } +//! ``` +//! +//! ## Reading bytes from VRAM +//! +//! ```no_run +//! use crate::driver::Bar0; +//! use crate::mm::pramin::PraminVram; +//! +//! fn read_data_from_vram(bar: &Bar0, buffer: &mut KVec) -> Result { +//! let pramin =3D PraminVram::new(bar); +//! // Read a u8 from VRAM starting at offset 0x20000 +//! pramin.read::(0x20000, buffer)?; +//! Ok(()) +//! } +//! ``` + +#![expect(dead_code)] + +use crate::driver::Bar0; +use crate::regs; +use core::mem; +use kernel::prelude::*; + +/// PRAMIN is a window into the VRAM (not a hardware block) that is used t= o access +/// the VRAM directly. These addresses are consistent across all GPUs. +const PRAMIN_BASE: usize =3D 0x700000; // PRAMIN is always at BAR0 + 0x700= 000 +const PRAMIN_SIZE: usize =3D 0x100000; // 1MB aperture - max access per wi= ndow position + +/// Trait for types that can be read/written through PRAMIN. +pub(crate) trait PraminNum: Copy + Default + Sized { + fn read_from_bar(bar: &Bar0, offset: usize) -> Result; + + fn write_to_bar(self, bar: &Bar0, offset: usize) -> Result; + + fn size_bytes() -> usize { + mem::size_of::() + } + + fn alignment() -> usize { + Self::size_bytes() + } +} + +/// Macro to implement PraminNum trait for unsigned integer types. +macro_rules! impl_pramin_unsigned_num { + ($bits:literal) =3D> { + ::kernel::macros::paste! { + impl PraminNum for [] { + fn read_from_bar(bar: &Bar0, offset: usize) -> Result { + bar.[](offset) + } + + fn write_to_bar(self, bar: &Bar0, offset: usize) -> Result= { + bar.[](self, offset) + } + } + } + }; +} + +impl_pramin_unsigned_num!(8); +impl_pramin_unsigned_num!(16); +impl_pramin_unsigned_num!(32); +impl_pramin_unsigned_num!(64); + +/// Direct VRAM access through PRAMIN window before page tables are set up. +pub(crate) struct PraminVram<'a> { + bar: &'a Bar0, + saved_window_addr: usize, +} + +impl<'a> PraminVram<'a> { + /// Create a new PRAMIN VRAM accessor, saving current window state, + /// the state is restored when the accessor is dropped. + /// + /// The BAR0 window base must be 64KB aligned but provides 1MB of VRAM= access. + /// Window is repositioned automatically when accessing data beyond 1M= B boundaries. + pub(crate) fn new(bar: &'a Bar0) -> Self { + let saved_window_addr =3D Self::get_window_addr(bar); + Self { + bar, + saved_window_addr, + } + } + + /// Set BAR0 window to point to specific FB region. + /// + /// # Arguments + /// + /// * `fb_offset` - VRAM byte offset where the window should be positi= oned. + /// Must be 64KB aligned (lower 16 bits zero). + fn set_window_addr(&self, fb_offset: usize) -> Result { + // FB offset must be 64KB aligned (hardware requirement for window= _base field) + // Once positioned, the window provides access to 1MB of VRAM thro= ugh PRAMIN aperture + if fb_offset & 0xFFFF !=3D 0 { + return Err(EINVAL); + } + + let window_reg =3D regs::NV_PBUS_BAR0_WINDOW::default().set_window= _addr(fb_offset); + window_reg.write(self.bar); + + // Read back to ensure it took effect + let readback =3D regs::NV_PBUS_BAR0_WINDOW::read(self.bar); + if readback.window_base() !=3D window_reg.window_base() { + return Err(EIO); + } + + Ok(()) + } + + /// Get current BAR0 window offset. + /// + /// # Returns + /// + /// The byte offset in VRAM where the PRAMIN window is currently posit= ioned. + /// This offset is always 64KB aligned. + fn get_window_addr(bar: &Bar0) -> usize { + let window_reg =3D regs::NV_PBUS_BAR0_WINDOW::read(bar); + window_reg.get_window_addr() + } + + /// Common logic for accessing VRAM data through PRAMIN with windowing. + /// + /// # Arguments + /// + /// * `fb_offset` - Starting byte offset in VRAM (framebuffer) where a= ccess begins. + /// Must be aligned to `T::alignment()`. + /// * `num_items` - Number of items of type `T` to process. + /// * `operation` - Closure called for each item to perform the actual= read/write. + /// Takes two parameters: + /// - `data_idx`: Index of the item in the data array = (0..num_items) + /// - `pramin_offset`: BAR0 offset in the PRAMIN apert= ure to access + /// + /// The function automatically handles PRAMIN window repositioning whe= n accessing + /// data that spans multiple 1MB windows. + fn access_vram( + &self, + fb_offset: usize, + num_items: usize, + mut operation: F, + ) -> Result + where + F: FnMut(usize, usize) -> Result, + { + // FB offset must be aligned to the size of T + if fb_offset & (T::alignment() - 1) !=3D 0 { + return Err(EINVAL); + } + + let mut offset_bytes =3D fb_offset; + let mut remaining_items =3D num_items; + let mut data_index =3D 0; + + while remaining_items > 0 { + // Align the window to 64KB boundary + let target_window =3D offset_bytes & !0xFFFF; + let window_offset =3D offset_bytes - target_window; + + // Set window if needed + if target_window !=3D Self::get_window_addr(self.bar) { + self.set_window_addr(target_window)?; + } + + // Calculate how many items we can access from this window pos= ition + // We can access up to 1MB total, minus the offset within the = window + let remaining_in_window =3D PRAMIN_SIZE - window_offset; + let max_items_in_window =3D remaining_in_window / T::size_byte= s(); + let items_to_write =3D core::cmp::min(remaining_items, max_ite= ms_in_window); + + // Process data through PRAMIN + for i in 0..items_to_write { + // Calculate the byte offset in the PRAMIN window to write= to. + let pramin_offset_bytes =3D PRAMIN_BASE + window_offset + = (i * T::size_bytes()); + operation(data_index + i, pramin_offset_bytes)?; + } + + // Move to next chunk. + data_index +=3D items_to_write; + offset_bytes +=3D items_to_write * T::size_bytes(); + remaining_items -=3D items_to_write; + } + + Ok(()) + } + + /// Generic write for data to VRAM through PRAMIN. + /// + /// # Arguments + /// + /// * `fb_offset` - Starting byte offset in VRAM where data will be wr= itten. + /// Must be aligned to `T::alignment()`. + /// * `data` - Slice of items to write to VRAM. All items will be writ= ten sequentially + /// starting at `fb_offset`. + pub(crate) fn write(&self, fb_offset: usize, data: &[T])= -> Result { + self.access_vram::(fb_offset, data.len(), |data_idx, pramin_= offset| { + data[data_idx].write_to_bar(self.bar, pramin_offset) + }) + } + + /// Generic read data from VRAM through PRAMIN. + /// + /// # Arguments + /// + /// * `fb_offset` - Starting byte offset in VRAM where data will be re= ad from. + /// Must be aligned to `T::alignment()`. + /// * `data` - Mutable slice that will be filled with data read from V= RAM. + /// The number of items read equals `data.len()`. + pub(crate) fn read(&self, fb_offset: usize, data: &mut [= T]) -> Result { + self.access_vram::(fb_offset, data.len(), |data_idx, pramin_= offset| { + data[data_idx] =3D T::read_from_bar(self.bar, pramin_offset)?; + Ok(()) + }) + } +} + +impl<'a> Drop for PraminVram<'a> { + fn drop(&mut self) { + let _ =3D self.set_window_addr(self.saved_window_addr); // Restore= original window. + } +} diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index 112277c7921e..6bd9fc3372d6 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -13,6 +13,7 @@ mod gfw; mod gpu; mod gsp; +mod mm; mod regs; mod util; mod vbios; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index a3836a01996b..ba09da7e1541 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -12,6 +12,7 @@ FalconModSelAlgo, FalconSecurityModel, PFalcon2Base, PFalconBase, Pere= grineCoreSelect, }; use crate::gpu::{Architecture, Chipset}; +use kernel::bits::genmask_u32; use kernel::prelude::*; =20 // PMC @@ -43,7 +44,8 @@ pub(crate) fn chipset(self) -> Result { } } =20 -// PBUS +// PBUS - PBUS is a bus control unit, that helps the GPU communicate with = the PCI bus. +// Handles the BAR windows, decoding of MMIO read/writes on the BARs, etc. =20 register!(NV_PBUS_SW_SCRATCH @ 0x00001400[64] {}); =20 @@ -52,6 +54,31 @@ pub(crate) fn chipset(self) -> Result { 31:16 frts_err_code as u16; }); =20 +// BAR0 window control register to configure the BAR0 window for PRAMIN ac= cess +// (direct physical VRAM access). +register!(NV_PBUS_BAR0_WINDOW @ 0x00001700, "BAR0 window control register"= { + 25:24 target as u8, "Target (0=3DVID_MEM, 1=3DSYS_MEM_COHERENT, 2=3D= SYS_MEM_NONCOHERENT)"; + 23:0 window_base as u32, "Window base address (bits 39:16 of FB add= r)"; +}); + +impl NV_PBUS_BAR0_WINDOW { + /// Returns the 64-bit aligned VRAM address of the window. + pub(crate) fn get_window_addr(self) -> usize { + (self.window_base() as usize) << 16 + } + + /// Sets the window address from a framebuffer offset. + /// The fb_offset must be 64KB aligned (lower bits discared). + pub(crate) fn set_window_addr(self, fb_offset: usize) -> Self { + // Calculate window base (bits 39:16 of FB address) + // The total FB address is 40 bits, mask anything above. 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charset="utf-8" Add data structures and helpers for page table management. Uses bitfield for cleanly representing and accessing the bitfields in the structures. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/mod.rs | 1 + drivers/gpu/nova-core/mm/types.rs | 405 ++++++++++++++++++++++++++++++ 2 files changed, 406 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/types.rs diff --git a/drivers/gpu/nova-core/mm/mod.rs b/drivers/gpu/nova-core/mm/mod= .rs index 54c7cd9416a9..f4985780a8a1 100644 --- a/drivers/gpu/nova-core/mm/mod.rs +++ b/drivers/gpu/nova-core/mm/mod.rs @@ -1,3 +1,4 @@ // SPDX-License-Identifier: GPL-2.0 =20 pub(crate) mod pramin; +pub(crate) mod types; diff --git a/drivers/gpu/nova-core/mm/types.rs b/drivers/gpu/nova-core/mm/t= ypes.rs new file mode 100644 index 000000000000..0a2dec6b9145 --- /dev/null +++ b/drivers/gpu/nova-core/mm/types.rs @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Page table data management for NVIDIA GPUs. +//! +//! This module provides data structures for GPU page table management, in= cluding +//! address types, page table entries (PTEs), page directory entries (PDEs= ), and +//! the page table hierarchy levels. +//! +//! # Examples +//! +//! ## Creating and writing a PDE +//! +//! ```no_run +//! let new_pde =3D Pde::default() +//! .set_valid(true) +//! .set_aperture(AperturePde::VideoMemory) +//! .set_table_frame_number(new_table.frame_number()); +//! // Call a function to write PDE to VRAM address +//! write_pde(pde_addr, new_pde)?; +//! ``` +//! +//! ## Given a PTE, Get or allocate a PFN (page frame number). +//! +//! ```no_run +//! fn get_frame_number(pte_addr: VramAddress) -> Result { +//! // Call a function to read 64-bit PTE value from VRAM address +//! let pte =3D Pte(read_u64_from_vram(pte_addr)?); +//! if pte.valid() { +//! // Return physical frame number from existing mapping +//! Ok(Pfn::new(pte.frame_number())) +//! } else { +//! // Create new PTE mapping +//! // Call a function to allocate a physical page, returning a Pfn +//! let phys_pfn =3D allocate_page()?; +//! let new_pte =3D Pte::default() +//! .set_valid(true) +//! .set_frame_number(phys_pfn.raw()) +//! .set_aperture(AperturePte::VideoMemory) +//! .set_privilege(false) // User-accessible +//! .set_read_only(false); // Writable +//! +//! // Call a function to write 64-bit PTE value to VRAM address +//! write_u64_to_vram(pte_addr, new_pte.raw())?; +//! Ok(phys_pfn) +//! } +//! } +//! ``` + +#![expect(dead_code)] + +/// Memory size constants +pub(crate) const KB: usize =3D 1024; +pub(crate) const MB: usize =3D KB * 1024; + +/// Page size: 4 KiB +pub(crate) const PAGE_SIZE: usize =3D 4 * KB; + +/// Page Table Level hierarchy +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) enum PageTableLevel { + Pdb, // Level 0 - Page Directory Base + L1, // Level 1 + L2, // Level 2 + L3, // Level 3 - Dual PDE (128-bit entries) + L4, // Level 4 - PTEs +} + +impl PageTableLevel { + /// Get the entry size for this level. + pub(crate) fn entry_size(&self) -> usize { + match self { + Self::L3 =3D> 16, // 128-bit dual PDE + _ =3D> 8, // 64-bit PDE/PTE + } + } + + /// PDE levels constant array for iteration. + const PDE_LEVELS: [PageTableLevel; 4] =3D [ + PageTableLevel::Pdb, + PageTableLevel::L1, + PageTableLevel::L2, + PageTableLevel::L3, + ]; + + /// Get iterator over PDE levels. + pub(crate) fn pde_levels() -> impl Iterator { + Self::PDE_LEVELS.into_iter() + } +} + +/// Memory aperture for Page Directory Entries (PDEs) +#[repr(u8)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub(crate) enum AperturePde { + #[default] + Invalid =3D 0, + VideoMemory =3D 1, + SystemCoherent =3D 2, + SystemNonCoherent =3D 3, +} + +impl From for AperturePde { + fn from(val: u8) -> Self { + match val { + 1 =3D> Self::VideoMemory, + 2 =3D> Self::SystemCoherent, + 3 =3D> Self::SystemNonCoherent, + _ =3D> Self::Invalid, + } + } +} + +impl From for u8 { + fn from(val: AperturePde) -> Self { + val as u8 + } +} + +/// Memory aperture for Page Table Entries (PTEs) +#[repr(u8)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub(crate) enum AperturePte { + #[default] + VideoMemory =3D 0, + PeerVideoMemory =3D 1, + SystemCoherent =3D 2, + SystemNonCoherent =3D 3, +} + +impl From for AperturePte { + fn from(val: u8) -> Self { + match val { + 0 =3D> Self::VideoMemory, + 1 =3D> Self::PeerVideoMemory, + 2 =3D> Self::SystemCoherent, + 3 =3D> Self::SystemNonCoherent, + _ =3D> Self::VideoMemory, + } + } +} + +impl From for u8 { + fn from(val: AperturePte) -> Self { + val as u8 + } +} + +/// Common trait for address types +pub(crate) trait Address { + /// Get raw u64 value. + fn raw(&self) -> u64; + + /// Convert an Address to a frame number. + fn frame_number(&self) -> u64 { + self.raw() >> 12 + } + + /// Get the frame offset within an Address. + fn frame_offset(&self) -> u16 { + (self.raw() & 0xFFF) as u16 + } +} + +bitfield! { + pub(crate) struct VramAddress(u64), "Physical VRAM address representat= ion." { + 11:0 offset as u16; // Offset within 4KB page + 63:12 frame_number as u64; // Frame number + } +} + +impl Address for VramAddress { + fn raw(&self) -> u64 { + self.0 + } +} + +impl From for VramAddress { + fn from(pfn: Pfn) -> VramAddress { + VramAddress::default().set_frame_number(pfn.raw()) + } +} + +bitfield! { + pub(crate) struct VirtualAddress(u64), "Virtual address representation= for GPU." { + 11:0 offset as u16; // Offset within 4KB page + 20:12 l4_index as u16; // Level 4 index (PTE) + 29:21 l3_index as u16; // Level 3 index + 38:30 l2_index as u16; // Level 2 index + 47:39 l1_index as u16; // Level 1 index + 56:48 l0_index as u16; // Level 0 index (PDB) + + 63:12 frame_number as u64; // Frame number (combination of lev= els). + } +} + +impl VirtualAddress { + /// Get index for a specific page table level. + /// + /// # Example + /// + /// ```no_run + /// let va =3D VirtualAddress::default(); + /// let pte_idx =3D va.level_index(PageTableLevel::L4); + /// ``` + pub(crate) fn level_index(&self, level: PageTableLevel) -> u16 { + match level { + PageTableLevel::Pdb =3D> self.l0_index(), + PageTableLevel::L1 =3D> self.l1_index(), + PageTableLevel::L2 =3D> self.l2_index(), + PageTableLevel::L3 =3D> self.l3_index(), + PageTableLevel::L4 =3D> self.l4_index(), + } + } +} + +impl Address for VirtualAddress { + fn raw(&self) -> u64 { + self.0 + } +} + +impl From for VirtualAddress { + fn from(vfn: Vfn) -> VirtualAddress { + VirtualAddress::default().set_frame_number(vfn.raw()) + } +} + +bitfield! { + pub(crate) struct Pte(u64), "Page Table Entry (PTE) to map virtual pag= es to physical frames." { + 0:0 valid as bool; // (1 =3D valid for PTEs) + 1:1 privilege as bool; // P - Privileged/kernel-only = access + 2:2 read_only as bool; // RO - Write protection + 3:3 atomic_disable as bool; // AD - Disable atomic ops + 4:4 encrypted as bool; // E - Encryption enabled + 39:8 frame_number as u64; // PA[39:8] - Physical frame n= umber (32 bits) + 41:40 aperture as u8 =3D> AperturePte; // Memory apertu= re type. + 42:42 volatile as bool; // VOL - Volatile flag + 50:43 kind as u8; // K[7:0] - Compression/tiling= kind + 63:51 comptag_line as u16; // CTL[12:0] - Compression tag= line + } +} + +impl Pte { + /// Set the physical address mapped by this PTE. + pub(crate) fn set_address(&mut self, addr: VramAddress) { + self.set_frame_number(addr.frame_number()); + } + + /// Get the physical address mapped by this PTE. + pub(crate) fn address(&self) -> VramAddress { + VramAddress::default().set_frame_number(self.frame_number()) + } + + /// Get raw u64 value. + pub(crate) fn raw(&self) -> u64 { + self.0 + } +} + +bitfield! { + pub(crate) struct Pde(u64), "Page Directory Entry (PDE) pointing to ne= xt-level page tables." { + 0:0 valid_inverted as bool; // V - Valid bit (0=3Dval= id for PDEs) + 2:1 aperture as u8 =3D> AperturePde; // Memor= y aperture type + 3:3 volatile as bool; // VOL - Volatile flag + 39:8 table_frame_number as u64; // PA[39:8] - Table frame= number (32 bits) + } +} + +impl Pde { + /// Check if PDE is valid. + pub(crate) fn is_valid(&self) -> bool { + !self.valid_inverted() && self.aperture() !=3D AperturePde::Invalid + } + + /// The valid bit is inverted so add an accessor to flip it. + pub(crate) fn set_valid(&self, value: bool) -> Pde { + self.set_valid_inverted(!value) + } + + /// Set the physical table address mapped by this PDE. + pub(crate) fn set_table_address(&mut self, addr: VramAddress) { + self.set_table_frame_number(addr.frame_number()); + } + + /// Get the physical table address mapped by this PDE. + pub(crate) fn table_address(&self) -> VramAddress { + VramAddress::default().set_frame_number(self.table_frame_number()) + } + + /// Get raw u64 value. + pub(crate) fn raw(&self) -> u64 { + self.0 + } +} + +/// Dual PDE at Level 3 - 128-bit entry containing both LPT and SPT pointe= rs. +/// Lower 64 bits =3D big/large page, upper 64 bits =3D small page. +/// +/// # Example +/// +/// ## Set the SPT (small page table) address in a Dual PDE +/// +/// ```no_run +/// // Call a function to read dual PDE from VRAM address +/// let mut dual_pde: DualPde =3D read_dual_pde(dpde_addr)?; +/// // Call a function to allocate a page table and return its VRAM address +/// let spt_addr =3D allocate_page_table()?; +/// dual_pde.set_spt(Pfn::from(spt_addr), AperturePde::VideoMemory); +/// // Call a function to write dual PDE to VRAM address +/// write_dual_pde(dpde_addr, dual_pde)?; +/// ``` +#[repr(C)] +#[derive(Debug, Clone, Copy)] +pub(crate) struct DualPde { + pub lpt: Pde, // Large/Big Page Table pointer (2MB pages) - bits 63:0 = (lower) + pub spt: Pde, // Small Page Table pointer (4KB pages) - bits 127:64 (u= pper) +} + +impl DualPde { + /// Create a new empty dual PDE. + pub(crate) fn new() -> Self { + Self { + spt: Pde::default(), + lpt: Pde::default(), + } + } + + /// Set the Small Page Table address with aperture. + pub(crate) fn set_small_pt_address(&mut self, addr: VramAddress, apert= ure: AperturePde) { + self.spt =3D Pde::default() + .set_valid(true) + .set_table_frame_number(addr.frame_number()) + .set_aperture(aperture); + } + + /// Set the Large Page Table address with aperture. + pub(crate) fn set_large_pt_address(&mut self, addr: VramAddress, apert= ure: AperturePde) { + self.lpt =3D Pde::default() + .set_valid(true) + .set_table_frame_number(addr.frame_number()) + .set_aperture(aperture); + } + + /// Check if has valid Small Page Table. + pub(crate) fn has_small_pt_address(&self) -> bool { + self.spt.is_valid() + } + + /// Check if has valid Large Page Table. + pub(crate) fn has_large_pt_address(&self) -> bool { + self.lpt.is_valid() + } + + /// Set SPT (Small Page Table) using Pfn. + pub(crate) fn set_spt(&mut self, pfn: Pfn, aperture: AperturePde) { + self.spt =3D Pde::default() + .set_valid(true) + .set_aperture(aperture) + .set_table_frame_number(pfn.raw()); + } +} + +/// Virtual Frame Number - virtual address divided by 4KB. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) struct Vfn(u64); + +impl Vfn { + /// Create a new VFN from a frame number. + pub(crate) const fn new(frame_number: u64) -> Self { + Self(frame_number) + } + + /// Get raw frame number. + pub(crate) const fn raw(&self) -> u64 { + self.0 + } +} + +impl From for Vfn { + fn from(vaddr: VirtualAddress) -> Self { + Self(vaddr.frame_number()) + } +} + +/// Physical Frame Number - physical address divided by 4KB. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) struct Pfn(u64); + +impl Pfn { + /// Create a new PFN from a frame number. + pub(crate) const fn new(frame_number: u64) -> Self { + Self(frame_number) + } + + /// Get raw frame number. + pub(crate) const fn raw(&self) -> u64 { + self.0 + } +} + +impl From for Pfn { + fn from(addr: VramAddress) -> Self { + Self(addr.frame_number()) + } +} --=20 2.34.1