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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-5a8a9799428sm3116783173.63.2025.10.20.09.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 09:52:01 -0700 (PDT) From: Alex Elder To: han.xu@nxp.com, broonie@kernel.org Cc: dlan@gentoo.org, guodong@riscstar.com, linux-spi@vger.kernel.org, imx@lists.linux.dev, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/8] spi: fsl-qspi: add a clock disable quirk Date: Mon, 20 Oct 2025 11:51:47 -0500 Message-ID: <20251020165152.666221-5-elder@riscstar.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251020165152.666221-1-elder@riscstar.com> References: <20251020165152.666221-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SpacemiT K1 SoC QSPI implementation needs to avoid shutting off the clock when changing its rate. Add a new quirk to indicate the clock should not be disabled/enabled when changing its rate for operations. Signed-off-by: Alex Elder --- drivers/spi/spi-fsl-qspi.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c index 1e27647dd2a09..703a7df394c00 100644 --- a/drivers/spi/spi-fsl-qspi.c +++ b/drivers/spi/spi-fsl-qspi.c @@ -197,6 +197,11 @@ */ #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5) =20 +/* + * Do not disable the "qspi" clock when changing its rate. + */ +#define QUADSPI_QUIRK_NO_CLK_DISABLE BIT(6) + struct fsl_qspi_devtype_data { unsigned int rxfifo; unsigned int txfifo; @@ -306,6 +311,11 @@ static inline int needs_tdh_setting(struct fsl_qspi *q) return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING; } =20 +static inline int needs_clk_disable(struct fsl_qspi *q) +{ + return !(q->devtype_data->quirks & QUADSPI_QUIRK_NO_CLK_DISABLE); +} + /* * An IC bug makes it necessary to rearrange the 32-bit data. * Later chips, such as IMX6SLX, have fixed this bug. @@ -536,15 +546,18 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, s= truct spi_device *spi, if (needs_4x_clock(q)) rate *=3D 4; =20 - fsl_qspi_clk_disable_unprep(q); + if (needs_clk_disable(q)) + fsl_qspi_clk_disable_unprep(q); =20 ret =3D clk_set_rate(q->clk, rate); if (ret) return; =20 - ret =3D fsl_qspi_clk_prep_enable(q); - if (ret) - return; + if (needs_clk_disable(q)) { + ret =3D fsl_qspi_clk_prep_enable(q); + if (ret) + return; + } =20 q->selected =3D spi_get_chipselect(spi, 0); =20 --=20 2.48.1