From nobody Mon Feb 9 10:13:17 2026 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F419A26657D for ; Mon, 20 Oct 2025 15:33:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760974418; cv=none; b=t0W7gB0+QllcbNLS/N5W1KPeOMydxaBzlgKH3Ns7gcLshZVr2HNszNslv2ZEfRFmCXmFI8YE6bqBZ9F4v1+5OXzzJT5yXafa8uONAVxXasrRvi6H1KJETif8LI8lQoSJ/0kp7zMefw1TVMNeNdxww+FaJGD2JpjFfm78t8Yow3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760974418; c=relaxed/simple; bh=XPck7Pu3R5UOQEJwx7GCF1vs4o8WhjABnI7JG+e6iMM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y6z4Eg4QoJ1H6y8fcYFM+Qh2TagDAkOl2ZmIA6YMhGmZLZnG+DCA49BbFqvd0QDmA5JSzhmmqkVQOHHGByWUsn0zEd3jeZvq8DK9SEoOzLwj1dE9BZisW1vVkwGyYsEOSDxYq3ns3h4X89hKxOofsRt7893Sj4tUGu+Tdwg6FZk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn; spf=pass smtp.mailfrom=isrc.iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=isrc.iscas.ac.cn Received: from Mobilestation.localdomain (unknown [183.6.59.216]) by APP-01 (Coremail) with SMTP id qwCowABHoaM4VvZoynsZEg--.39132S2; Mon, 20 Oct 2025 23:33:21 +0800 (CST) From: Yao Zihong To: zihong.plct@isrc.iscas.ac.cn Cc: ajones@ventanamicro.com, alex@ghiti.fr, alexghiti@rivosinc.com, aou@eecs.berkeley.edu, cleger@rivosinc.com, evan@rivosinc.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, pjw@kernel.org, samuel.holland@sifive.com, shuah@kernel.org, zhangyin2018@iscas.ac.cn, zihongyao@outlook.com Subject: [PATCH v3 1/2] riscv: hwprobe: Expose Zicbop extension and its block size Date: Mon, 20 Oct 2025 23:33:08 +0800 Message-ID: <20251020153309.68267-1-zihong.plct@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251020152924.64551-1-zihong.plct@isrc.iscas.ac.cn> References: <20251020152924.64551-1-zihong.plct@isrc.iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowABHoaM4VvZoynsZEg--.39132S2 X-Coremail-Antispam: 1UD129KBjvJXoWxGFWkXrWkWF45GryDKw4DArb_yoWrAF18pF 4DZrsxWFs8Cw4xCFWxt3WkZrn5J3Z7Kw43KF1Uu3yUJFW7trWrXr9xtFsIyr1DtFyFya92 gF4SgrZYya9rAFDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9014x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r 4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628v n2kIc2xKxwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7x kEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E 67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCw CI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1x MIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIda VFxhVjvjDU0xZFpf9x0JUZYFZUUUUU= X-CM-SenderInfo: p2lk00vjoszunw6l223fol2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" - Add `RISCV_HWPROBE_EXT_ZICBOP` to report the presence of the Zicbop extension. - Add `RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE` to expose the block size (in bytes) when Zicbop is supported. - Update hwprobe.rst to document the new extension bit and block size key, following the existing Zicbom/Zicboz style. Signed-off-by: Yao Zihong Reviewed-by: Andrew Jones --- Documentation/arch/riscv/hwprobe.rst | 8 +++++++- arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_hwprobe.c | 6 ++++++ 4 files changed, 16 insertions(+), 2 deletions(-) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 2f449c9b15bd..52f12af43b9d 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -275,6 +275,9 @@ The following keys are defined: ratified in commit 49f49c842ff9 ("Update to Rafified state") of riscv-zabha. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported= , as + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMO= s. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar val= ues to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value. @@ -369,4 +372,7 @@ The following keys are defined: =20 * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq vendor extension is supported in version 1.0 of Matrix Multiply Ac= cumulate - Instruction Extensions Specification. \ No newline at end of file + Instruction Extensions Specification. + +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which + represents the size of the Zicbop block in bytes. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h index 948d2b34e94e..2f278c395af9 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,7 +8,7 @@ =20 #include =20 -#define RISCV_HWPROBE_MAX_KEY 14 +#define RISCV_HWPROBE_MAX_KEY 15 =20 static inline bool riscv_hwprobe_key_is_valid(__s64 key) { diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 5d30a4fae37a..9cc508be54c5 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -82,6 +82,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56) #define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57) #define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58) +#define RISCV_HWPROBE_EXT_ZICBOP (1ULL << 59) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) @@ -107,6 +108,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 12 #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 13 #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0 14 +#define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE 15 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 /* Flags */ diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 000f4451a9d8..7a6ae1327504 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -113,6 +113,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZCB); EXT_KEY(ZCMOP); EXT_KEY(ZICBOM); + EXT_KEY(ZICBOP); EXT_KEY(ZICBOZ); EXT_KEY(ZICNTR); EXT_KEY(ZICOND); @@ -293,6 +294,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pai= r, if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM)) pair->value =3D riscv_cbom_block_size; break; + case RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE: + pair->value =3D 0; + if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOP)) + pair->value =3D riscv_cbop_block_size; + break; case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS: pair->value =3D user_max_virt_addr(); break; --=20 2.47.2 From nobody Mon Feb 9 10:13:17 2026 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3724B266576 for ; Mon, 20 Oct 2025 15:37:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 20 Oct 2025 23:37:28 +0800 (CST) From: Yao Zihong To: zihong.plct@isrc.iscas.ac.cn Cc: ajones@ventanamicro.com, alex@ghiti.fr, alexghiti@rivosinc.com, aou@eecs.berkeley.edu, cleger@rivosinc.com, evan@rivosinc.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, pjw@kernel.org, samuel.holland@sifive.com, shuah@kernel.org, zhangyin2018@iscas.ac.cn, zihongyao@outlook.com Subject: [PATCH v3 2/2] selftests/riscv: Add Zicbop prefetch test Date: Mon, 20 Oct 2025 23:37:20 +0800 Message-ID: <20251020153721.71842-1-zihong.plct@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251020152924.64551-1-zihong.plct@isrc.iscas.ac.cn> References: <20251020152924.64551-1-zihong.plct@isrc.iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowADnQaQ0V_ZoU38aEg--.28544S2 X-Coremail-Antispam: 1UD129KBjvJXoW3JFWkGFyrGry5Xr45CrWDtwb_yoWDGrW5pF Zxur4SvF45ZF40qrWxJr4kCr1Fqrn2qrWUCrWrG3s8ZayUX398GFWkKa97AFWkKr97Zr1F vFn8AFWUua1UGaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9014x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r 4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUXVWUAwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628v n2kIc2xKxwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7x kEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E 67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCw CI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1x MIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIda VFxhVjvjDU0xZFpf9x0JUpwZcUUUUU= X-CM-SenderInfo: p2lk00vjoszunw6l223fol2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" Add selftest to cbo.c to verify Zicbop extension behavior. The test checks: - That hwprobe correctly reports Zicbop presence and block size. - That prefetch instructions execute without exception on valid and NULL addresses when Zicbop is present. - That prefetch.{i,r,w} do not trigger SIGILL even when Zicbop is absent, since Zicbop instructions are defined as hints. Signed-off-by: Yao Zihong Reviewed-by: Andrew Jones --- tools/testing/selftests/riscv/hwprobe/cbo.c | 188 +++++++++++++++++--- 1 file changed, 159 insertions(+), 29 deletions(-) diff --git a/tools/testing/selftests/riscv/hwprobe/cbo.c b/tools/testing/se= lftests/riscv/hwprobe/cbo.c index 5e96ef785d0d..163228e3f2c7 100644 --- a/tools/testing/selftests/riscv/hwprobe/cbo.c +++ b/tools/testing/selftests/riscv/hwprobe/cbo.c @@ -15,24 +15,30 @@ #include #include #include +#include =20 #include "hwprobe.h" #include "../../kselftest.h" =20 #define MK_CBO(fn) le32_bswap((uint32_t)(fn) << 20 | 10 << 15 | 2 << 12 | = 0 << 7 | 15) +#define MK_PREFETCH(fn) \ + le32_bswap(0 << 25 | (uint32_t)(fn) << 20 | 10 << 15 | 6 << 12 | 0 << 7 |= 19) =20 static char mem[4096] __aligned(4096) =3D { [0 ... 4095] =3D 0xa5 }; =20 -static bool illegal_insn; +static bool got_fault; =20 static void sigill_handler(int sig, siginfo_t *info, void *context) { unsigned long *regs =3D (unsigned long *)&((ucontext_t *)context)->uc_mco= ntext; uint32_t insn =3D *(uint32_t *)regs[0]; =20 - assert(insn =3D=3D MK_CBO(regs[11])); + if (regs[12] =3D=3D 0) + assert(insn =3D=3D MK_CBO(regs[11])); + else + assert(insn =3D=3D MK_PREFETCH(regs[11])); =20 - illegal_insn =3D true; + got_fault =3D true; regs[0] +=3D 4; } =20 @@ -41,43 +47,75 @@ static void sigill_handler(int sig, siginfo_t *info, vo= id *context) asm volatile( \ "mv a0, %0\n" \ "li a1, %1\n" \ + "li a2, 0\n" \ ".4byte %2\n" \ - : : "r" (base), "i" (fn), "i" (MK_CBO(fn)) : "a0", "a1", "memory"); \ + : : "r" (base), "i" (fn), "i" (MK_CBO(fn)) : "a0", "a1", "a2", "memory");= \ +}) + +#define prefetch_insn(base, fn) \ +({ \ + asm volatile( \ + "mv a0, %0\n" \ + "li a1, %1\n" \ + "li a2, 1\n" \ + ".4byte %2\n" \ + : : "r" (base), "i" (fn), "i" (MK_PREFETCH(fn)) : "a0", "a1", "a2");\ }) =20 static void cbo_inval(char *base) { cbo_insn(base, 0); } static void cbo_clean(char *base) { cbo_insn(base, 1); } static void cbo_flush(char *base) { cbo_insn(base, 2); } static void cbo_zero(char *base) { cbo_insn(base, 4); } +static void prefetch_i(char *base) { prefetch_insn(base, 0); } +static void prefetch_r(char *base) { prefetch_insn(base, 1); } +static void prefetch_w(char *base) { prefetch_insn(base, 3); } + +static void test_no_zicbop(void *arg) +{ + /* Zicbop prefetch.* are HINT instructions. */ + ksft_print_msg("Testing Zicbop instructions\n"); + + got_fault =3D false; + prefetch_i(&mem[0]); + ksft_test_result(!got_fault, "No prefetch.i\n"); + + got_fault =3D false; + prefetch_r(&mem[0]); + ksft_test_result(!got_fault, "No prefetch.r\n"); + + got_fault =3D false; + prefetch_w(&mem[0]); + ksft_test_result(!got_fault, "No prefetch.w\n"); +} =20 static void test_no_cbo_inval(void *arg) { ksft_print_msg("Testing cbo.inval instruction remain privileged\n"); - illegal_insn =3D false; + got_fault =3D false; cbo_inval(&mem[0]); - ksft_test_result(illegal_insn, "No cbo.inval\n"); + ksft_test_result(got_fault, "No cbo.inval\n"); } =20 static void test_no_zicbom(void *arg) { ksft_print_msg("Testing Zicbom instructions remain privileged\n"); =20 - illegal_insn =3D false; + got_fault =3D false; cbo_clean(&mem[0]); - ksft_test_result(illegal_insn, "No cbo.clean\n"); + ksft_test_result(got_fault, "No cbo.clean\n"); =20 - illegal_insn =3D false; + got_fault =3D false; cbo_flush(&mem[0]); - ksft_test_result(illegal_insn, "No cbo.flush\n"); + ksft_test_result(got_fault, "No cbo.flush\n"); } =20 static void test_no_zicboz(void *arg) { ksft_print_msg("No Zicboz, testing cbo.zero remains privileged\n"); =20 - illegal_insn =3D false; + got_fault =3D false; cbo_zero(&mem[0]); - ksft_test_result(illegal_insn, "No cbo.zero\n"); + ksft_test_result(got_fault, "No cbo.zero\n"); } =20 static bool is_power_of_2(__u64 n) @@ -85,6 +123,34 @@ static bool is_power_of_2(__u64 n) return n !=3D 0 && (n & (n - 1)) =3D=3D 0; } =20 +static void test_zicbop(void *arg) +{ + struct riscv_hwprobe pair =3D { + .key =3D RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE, + }; + cpu_set_t *cpus =3D (cpu_set_t *)arg; + __u64 block_size; + long rc; + + rc =3D riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)cpus, = 0); + block_size =3D pair.value; + ksft_test_result(rc =3D=3D 0 && pair.key =3D=3D RISCV_HWPROBE_KEY_ZICBOP_= BLOCK_SIZE && + is_power_of_2(block_size), "Zicbop block size\n"); + ksft_print_msg("Zicbop block size: %llu\n", block_size); + + got_fault =3D false; + prefetch_i(&mem[0]); + prefetch_r(&mem[0]); + prefetch_w(&mem[0]); + ksft_test_result(!got_fault, "Zicbop prefetch.* on valid address\n"); + + got_fault =3D false; + prefetch_i(NULL); + prefetch_r(NULL); + prefetch_w(NULL); + ksft_test_result(!got_fault, "Zicbop prefetch.* on NULL\n"); +} + static void test_zicbom(void *arg) { struct riscv_hwprobe pair =3D { @@ -100,13 +166,13 @@ static void test_zicbom(void *arg) is_power_of_2(block_size), "Zicbom block size\n"); ksft_print_msg("Zicbom block size: %llu\n", block_size); =20 - illegal_insn =3D false; + got_fault =3D false; cbo_clean(&mem[block_size]); - ksft_test_result(!illegal_insn, "cbo.clean\n"); + ksft_test_result(!got_fault, "cbo.clean\n"); =20 - illegal_insn =3D false; + got_fault =3D false; cbo_flush(&mem[block_size]); - ksft_test_result(!illegal_insn, "cbo.flush\n"); + ksft_test_result(!got_fault, "cbo.flush\n"); } =20 static void test_zicboz(void *arg) @@ -125,11 +191,11 @@ static void test_zicboz(void *arg) is_power_of_2(block_size), "Zicboz block size\n"); ksft_print_msg("Zicboz block size: %llu\n", block_size); =20 - illegal_insn =3D false; + got_fault =3D false; cbo_zero(&mem[block_size]); - ksft_test_result(!illegal_insn, "cbo.zero\n"); + ksft_test_result(!got_fault, "cbo.zero\n"); =20 - if (illegal_insn || !is_power_of_2(block_size)) { + if (got_fault || !is_power_of_2(block_size)) { ksft_test_result_skip("cbo.zero check\n"); return; } @@ -148,7 +214,7 @@ static void test_zicboz(void *arg) if (mem[i * block_size + j] !=3D expected) { ksft_test_result_fail("cbo.zero check\n"); ksft_print_msg("cbo.zero check: mem[%llu] !=3D 0x%x\n", - i * block_size + j, expected); + i * block_size + j, expected); return; } } @@ -177,7 +243,19 @@ static void check_no_zicbo_cpus(cpu_set_t *cpus, __u64= cbo) rc =3D riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)&one_= cpu, 0); assert(rc =3D=3D 0 && pair.key =3D=3D RISCV_HWPROBE_KEY_IMA_EXT_0); =20 - cbostr =3D cbo =3D=3D RISCV_HWPROBE_EXT_ZICBOZ ? "Zicboz" : "Zicbom"; + switch (cbo) { + case RISCV_HWPROBE_EXT_ZICBOZ: + cbostr =3D "Zicboz"; + break; + case RISCV_HWPROBE_EXT_ZICBOM: + cbostr =3D "Zicbom"; + break; + case RISCV_HWPROBE_EXT_ZICBOP: + cbostr =3D "Zicbop"; + break; + default: + ksft_exit_fail_msg("Internal error: invalid cbo %llu\n", cbo); + } =20 if (pair.value & cbo) ksft_exit_fail_msg("%s is only present on a subset of harts.\n" @@ -194,6 +272,8 @@ enum { TEST_ZICBOM, TEST_NO_ZICBOM, TEST_NO_CBO_INVAL, + TEST_ZICBOP, + TEST_NO_ZICBOP }; =20 static struct test_info { @@ -206,27 +286,70 @@ static struct test_info { [TEST_ZICBOM] =3D { .nr_tests =3D 3, test_zicbom }, [TEST_NO_ZICBOM] =3D { .nr_tests =3D 2, test_no_zicbom }, [TEST_NO_CBO_INVAL] =3D { .nr_tests =3D 1, test_no_cbo_inval }, + [TEST_ZICBOP] =3D { .nr_tests =3D 3, test_zicbop }, + [TEST_NO_ZICBOP] =3D { .nr_tests =3D 3, test_no_zicbop }, }; =20 -int main(int argc, char **argv) +static const struct option long_opts[] =3D { + {"sigill", no_argument, 0, 'i'}, + {"sigsegv", no_argument, 0, 's'}, + {"sigbus", no_argument, 0, 'b'}, + {0, 0, 0, 0} +}; + +static void install_sigaction(int argc, char **argv) { + int rc, opt, long_index; + bool sigill; + struct sigaction act =3D { .sa_sigaction =3D &sigill_handler, .sa_flags =3D SA_SIGINFO, }; + + long_index =3D 0; + sigill =3D false; + + while ((opt =3D getopt_long(argc, argv, "isb", long_opts, &long_index)) != =3D -1) { + switch (opt) { + case 'i': + rc =3D sigaction(SIGILL, &act, NULL); + assert(rc =3D=3D 0); + sigill =3D true; + break; + case 's': + rc =3D sigaction(SIGSEGV, &act, NULL); + assert(rc =3D=3D 0); + break; + case 'b': + rc =3D sigaction(SIGBUS, &act, NULL); + assert(rc =3D=3D 0); + break; + case '?': + fprintf(stderr, "Unknown option or missing arg\n"); + exit(1); + default: + break; + } + } + + if (sigill) { + tests[TEST_NO_ZICBOZ].enabled =3D true; + tests[TEST_NO_ZICBOM].enabled =3D true; + tests[TEST_NO_CBO_INVAL].enabled =3D true; + tests[TEST_NO_ZICBOP].enabled =3D true; + } +} + +int main(int argc, char **argv) +{ struct riscv_hwprobe pair; unsigned int plan =3D 0; cpu_set_t cpus; long rc; int i; =20 - if (argc > 1 && !strcmp(argv[1], "--sigill")) { - rc =3D sigaction(SIGILL, &act, NULL); - assert(rc =3D=3D 0); - tests[TEST_NO_ZICBOZ].enabled =3D true; - tests[TEST_NO_ZICBOM].enabled =3D true; - tests[TEST_NO_CBO_INVAL].enabled =3D true; - } + install_sigaction(argc, argv); =20 rc =3D sched_getaffinity(0, sizeof(cpu_set_t), &cpus); assert(rc =3D=3D 0); @@ -253,6 +376,13 @@ int main(int argc, char **argv) check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOM); } =20 + if (pair.value & RISCV_HWPROBE_EXT_ZICBOP) { + tests[TEST_ZICBOP].enabled =3D true; + tests[TEST_NO_ZICBOP].enabled =3D false; + } else { + check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOP); + } + for (i =3D 0; i < ARRAY_SIZE(tests); ++i) plan +=3D tests[i].enabled ? tests[i].nr_tests : 0; =20 --=20 2.47.2