From nobody Mon Feb 9 01:11:34 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1787E1A239A; Mon, 20 Oct 2025 14:31:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760970689; cv=none; b=ZQ0c/J0ZquBGcjZ9oDI3DDJzSW/yjPWiDrnaaYkqcRoaaEK/OWzqq5bvahlCjSItlScCzAw3K4AuRhiL4FVWqViBEpaUzj7j0HqjQcbL2GapuySYBKsPdc3E6q5BA6z4g9o28P5kddzqkjNujzN6xl+C6o3ghJBKteC/7ZdQGhw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760970689; c=relaxed/simple; bh=2ZZaMMEQ4z7meE1xLJ8lzq1PQWW3LcYSdXb3pyAIv28=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DUlSgDZSEN7avjRG4ia0RKoKpOqjrsxr+vF15pHhqjS5AmSAssXU7UgO9WRkJ0W+RZ+SklFSI+O7Qp3llO4lH1gR0qCOf6Hmc4XbPHmp3DuFy0XPxgwyrjBKdMbMvRFKo0Y5lQeHImULXuhegDUZX7t4hDEUKOssLuUo513SbCk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: rB6AduWXR5yuHluoyT7U+Q== X-CSE-MsgGUID: 0bz24/jUTpuSh/VVbSTFsA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Oct 2025 23:31:19 +0900 Received: from vm01.adwin.renesas.com (unknown [10.226.92.23]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id A6E6B41CCD99; Mon, 20 Oct 2025 23:31:14 +0900 (JST) From: Ovidiu Panait To: john.madieu.xa@bp.renesas.com, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 1/3] clk: renesas: r9a09g057: Add clock and reset entries for TSU Date: Mon, 20 Oct 2025 14:31:05 +0000 Message-ID: <20251020143107.13974-2-ovidiu.panait.rb@renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251020143107.13974-1-ovidiu.panait.rb@renesas.com> References: <20251020143107.13974-1-ovidiu.panait.rb@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add module clock and reset entries for the TSU0 and TSU1 blocks on the Renesas RZ/V2H (R9A09G057) SoC. Signed-off-by: Ovidiu Panait Reviewed-by: Geert Uytterhoeven --- v2 changes: none drivers/clk/renesas/r9a09g057-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a0= 9g057-cpg.c index 100cd56c323e..dce5755d85ec 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -389,6 +389,10 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[]= __initconst =3D { BUS_MSTOP(3, BIT(4))), DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, BUS_MSTOP(3, BIT(4))), + DEF_MOD("tsu_0_pclk", CLK_QEXTAL, 16, 9, 8, 9, + BUS_MSTOP(5, BIT(2))), + DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, + BUS_MSTOP(2, BIT(15))), }; =20 static const struct rzv2h_reset r9a09g057_resets[] __initconst =3D { @@ -463,6 +467,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __in= itconst =3D { DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */ DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */ DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */ + DEF_RST(15, 7, 7, 8), /* TSU_0_PRESETN */ + DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ }; =20 const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst =3D { --=20 2.51.0 From nobody Mon Feb 9 01:11:34 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E671421FF4D; Mon, 20 Oct 2025 14:31:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760970688; cv=none; b=iMpKMTS7KFr9NH5eqoOoRp4CYJijcxwf/kQJqRDREjLfQ1B1w241dvNHy5g6B6B1rEjt6rLg+A++hQyh6LOg34K9sXRcvtu5MFcRW4Ml6DP5/yhavitstl+9GM3RLp8XyNNV8LI5fRyKbuBrOi+h6G7F7bGkmZ3y0hhlbuwTpSY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760970688; c=relaxed/simple; bh=RmDctZXm85kTLVYOSDkgdDNVCzPmUFMnuvpzQZziQro=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Do4MmNsbRPEVz0BPaym//+1cJQioSHKo+cXwKjuUeoE0c+47AGYL4s6hLeSVSMMJg7fJC4c57GI7DfXW2KnlTPbEB0HBFUBoYHpTw1X7KLaGOu+LzxswdjldxcXQ3FaasyKRZ8ZhE6ii5cjNAAKi/YwIhpT/vuQi9RWAOj3967U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: safs7Iz4ROaWEswTR1lfVw== X-CSE-MsgGUID: JiGLIIcsTXWmbAUrnk3ZTQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Oct 2025 23:31:25 +0900 Received: from vm01.adwin.renesas.com (unknown [10.226.92.23]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 77D6541CCD99; Mon, 20 Oct 2025 23:31:20 +0900 (JST) From: Ovidiu Panait To: john.madieu.xa@bp.renesas.com, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 2/3] dt-bindings: thermal: r9a09g047-tsu: Document RZ/V2H TSU Date: Mon, 20 Oct 2025 14:31:06 +0000 Message-ID: <20251020143107.13974-3-ovidiu.panait.rb@renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251020143107.13974-1-ovidiu.panait.rb@renesas.com> References: <20251020143107.13974-1-ovidiu.panait.rb@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/V2H SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing two dedicated channels for temperature sensing. The Renesas RZ/V2H SoC is using the same TSU IP found on the RZ/G3E SoC, the only difference being that it has two channels instead of one. Add new compatible string "renesas,r9a09g057-tsu" for RZ/V2H and use "renesas,r9a09g047-tsu" as a fallback compatible to indicate hardware compatibility with the RZ/G3E implementation. Signed-off-by: Ovidiu Panait Reviewed-by: Krzysztof Kozlowski --- v2 changes: - dropped unneeded "items" from compatible list - added "Reviewed-by:" tag from Krzysztof .../devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-ts= u.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.ya= ml index 8d3f3c24f0f2..befdc8b7a082 100644 --- a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml @@ -16,7 +16,11 @@ description: =20 properties: compatible: - const: renesas,r9a09g047-tsu + oneOf: + - const: renesas,r9a09g047-tsu # RZ/G3E + - items: + - const: renesas,r9a09g057-tsu # RZ/V2H + - const: renesas,r9a09g047-tsu # RZ/G3E =20 reg: maxItems: 1 --=20 2.51.0 From nobody Mon Feb 9 01:11:34 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BAAA71A239A; Mon, 20 Oct 2025 14:31:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760970694; cv=none; b=r/TMjHL1c0lknFzsQnfADVF9/qmwKaZQbYN0TieMLkz3U1RaM5l0Z6KkIz/ayXHjU+I84Uo64b0o6V3uMOUnoGg9LhhBniOvemmeFPaSsYkRQ/Vi4NE/pQpdeeYmDi41ZXMNoVD8mZKLR989nblGN8PUbI55pu/K/nLdJluoqL8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760970694; c=relaxed/simple; bh=Bty+vvqO0kZ7CUd0Q2nqj5ngueUp9769n2FevdwMEyw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fGxYKNxFVmm4UAcHjlSQsn8kV64xFRIfVAclN/Mu47HYDiHfuNUdLt1ybF0hC49Ycd76FyjUw8aGQAjXMVwEaBvUE5YXCNuQZ1Tyvvxh5xmNyQY4oibtotuOuNJ5zC/+DQCCXQGo8pI/CNnTy/4wbujRWv9SYIbImqq0r+vHsOw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: qPnqo77zQLGKHJRIXyqJhg== X-CSE-MsgGUID: pMNaHPNaRwSsplcJ/xXfBw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Oct 2025 23:31:31 +0900 Received: from vm01.adwin.renesas.com (unknown [10.226.92.23]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 46A8F41CCD99; Mon, 20 Oct 2025 23:31:25 +0900 (JST) From: Ovidiu Panait To: john.madieu.xa@bp.renesas.com, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 3/3] arm64: dts: renesas: r9a09g057: Add TSU nodes Date: Mon, 20 Oct 2025 14:31:07 +0000 Message-ID: <20251020143107.13974-4-ovidiu.panait.rb@renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251020143107.13974-1-ovidiu.panait.rb@renesas.com> References: <20251020143107.13974-1-ovidiu.panait.rb@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/V2H SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing two dedicated channels for temperature sensing: - TSU0, which is located near the DRP-AI block - TSU1, which is located near the CPU and DRP-AI block Since TSU1 is physically closer the CPU and the highest temperature spot, it is used for CPU throttling through a passive trip and cooling map. TSU0 is configured only with a critical trip. Add TSU nodes along with thermal zones and keep them enabled in the SoC DTSI. Signed-off-by: Ovidiu Panait Reviewed-by: Geert Uytterhoeven --- v2 changes: none arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 75 ++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g057.dtsi index e426b9978e22..e88cfc965415 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -65,6 +65,7 @@ cpu0: cpu@0 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -75,6 +76,7 @@ cpu1: cpu@100 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -85,6 +87,7 @@ cpu2: cpu@200 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -95,6 +98,7 @@ cpu3: cpu@300 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -285,6 +289,32 @@ sys: system-controller@10430000 { resets =3D <&cpg 0x30>; }; =20 + tsu0: thermal@11000000 { + compatible =3D "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; + reg =3D <0 0x11000000 0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + clocks =3D <&cpg CPG_MOD 0x109>; + resets =3D <&cpg 0xf7>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + renesas,tsu-trim =3D <&sys 0x320>; + }; + + tsu1: thermal@14002000 { + compatible =3D "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; + reg =3D <0 0x14002000 0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + clocks =3D <&cpg CPG_MOD 0x10a>; + resets =3D <&cpg 0xf8>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + renesas,tsu-trim =3D <&sys 0x330>; + }; + xspi: spi@11030000 { compatible =3D "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi"; reg =3D <0 0x11030000 0 0x10000>, @@ -1326,6 +1356,51 @@ stmmac_axi_setup: stmmac-axi-config { snps,blen =3D <16 8 4 0 0 0 0>; }; =20 + thermal-zones { + sensor1_thermal: sensor1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&tsu0>; + + trips { + sensor1_crit: sensor1-crit { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + sensor2_thermal: sensor2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&tsu1>; + + cooling-maps { + map0 { + trip =3D <&sensor2_target>; + cooling-device =3D <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution =3D <1024>; + }; + }; + + trips { + sensor2_target: trip-point { + temperature =3D <95000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + sensor2_crit: sensor2-crit { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts =3D , --=20 2.51.0