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[93.34.92.177]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-4283e7804f4sm12692219f8f.10.2025.10.20.04.11.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 04:11:45 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, upstream@airoha.com Subject: [PATCH v6 5/5] PCI: mediatek: Add support for Airoha AN7583 SoC Date: Mon, 20 Oct 2025 13:11:09 +0200 Message-ID: <20251020111121.31779-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251020111121.31779-1-ansuelsmth@gmail.com> References: <20251020111121.31779-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the second PCIe Root Complex present on Airoha AN7583 SoC. This is based on the Mediatek Gen1/2 PCIe driver and similar to Gen3 also require workaround for the reset signals. Introduce a new quirk to skip having to reset signals and also introduce some additional logic to configure the PBUS registers required for Airoha SoC. Signed-off-by: Christian Marangi Reviewed-by: AngeloGioacchino Del Regno --- drivers/pci/controller/pcie-mediatek.c | 75 +++++++++++++++++++++----- 1 file changed, 61 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 313da61a0b8a..4b78b6528f9f 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -147,11 +147,13 @@ struct mtk_pcie_port; * @MTK_PCIE_FIX_CLASS_ID: host's class ID needed to be fixed * @MTK_PCIE_FIX_DEVICE_ID: host's device ID needed to be fixed * @MTK_PCIE_NO_MSI: Bridge has no MSI support, and relies on an external = block + * @MTK_PCIE_SKIP_RSTB: Skip calling RSTB bits on PCIe probe */ enum mtk_pcie_quirks { MTK_PCIE_FIX_CLASS_ID =3D BIT(0), MTK_PCIE_FIX_DEVICE_ID =3D BIT(1), MTK_PCIE_NO_MSI =3D BIT(2), + MTK_PCIE_SKIP_RSTB =3D BIT(3), }; =20 /** @@ -687,23 +689,25 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_p= ort *port) regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); } =20 - /* Assert all reset signals */ - writel(0, port->base + PCIE_RST_CTRL); + if (!(soc->quirks & MTK_PCIE_SKIP_RSTB)) { + /* Assert all reset signals */ + writel(0, port->base + PCIE_RST_CTRL); =20 - /* - * Enable PCIe link down reset, if link status changed from link up to - * link down, this will reset MAC control registers and configuration - * space. - */ - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + /* + * Enable PCIe link down reset, if link status changed from + * link up to link down, this will reset MAC control registers + * and configuration space. + */ + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); =20 - msleep(PCIE_T_PVPERL_MS); + msleep(PCIE_T_PVPERL_MS); =20 - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ - val =3D readl(port->base + PCIE_RST_CTRL); - val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | - PCIE_MAC_SRSTB | PCIE_CRSTB; - writel(val, port->base + PCIE_RST_CTRL); + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ + val =3D readl(port->base + PCIE_RST_CTRL); + val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | + PCIE_MAC_SRSTB | PCIE_CRSTB; + writel(val, port->base + PCIE_RST_CTRL); + } =20 /* Set up vendor ID and class code */ if (soc->quirks & MTK_PCIE_FIX_CLASS_ID) { @@ -824,6 +828,41 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port = *port) return 0; } =20 +static int mtk_pcie_startup_port_an7583(struct mtk_pcie_port *port) +{ + struct mtk_pcie *pcie =3D port->pcie; + struct device *dev =3D pcie->dev; + struct pci_host_bridge *host; + struct resource_entry *entry; + struct regmap *pbus_regmap; + resource_size_t addr; + u32 args[2], size; + + /* + * Configure PBus base address and base address mask to allow + * the hw to detect if a given address is accessible on PCIe + * controller. + */ + pbus_regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, + "mediatek,pbus-csr", + ARRAY_SIZE(args), + args); + if (IS_ERR(pbus_regmap)) + return PTR_ERR(pbus_regmap); + + host =3D pci_host_bridge_from_priv(pcie); + entry =3D resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (!entry) + return -ENODEV; + + addr =3D entry->res->start - entry->offset; + regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); + size =3D lower_32_bits(resource_size(entry->res)); + regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); + + return mtk_pcie_startup_port_v2(port); +} + static void mtk_pcie_enable_port(struct mtk_pcie_port *port) { struct mtk_pcie *pcie =3D port->pcie; @@ -1208,6 +1247,13 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622= =3D { .quirks =3D MTK_PCIE_FIX_CLASS_ID, }; =20 +static const struct mtk_pcie_soc mtk_pcie_soc_an7583 =3D { + .ops =3D &mtk_pcie_ops_v2, + .startup =3D mtk_pcie_startup_port_an7583, + .setup_irq =3D mtk_pcie_setup_irq, + .quirks =3D MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_SKIP_RSTB, +}; + static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 =3D { .device_id =3D PCI_DEVICE_ID_MEDIATEK_7629, .ops =3D &mtk_pcie_ops_v2, @@ -1217,6 +1263,7 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = =3D { }; =20 static const struct of_device_id mtk_pcie_ids[] =3D { + { .compatible =3D "airoha,an7583-pcie", .data =3D &mtk_pcie_soc_an7583 }, { .compatible =3D "mediatek,mt2701-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt7623-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt2712-pcie", .data =3D &mtk_pcie_soc_mt2712 = }, --=20 2.51.0