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[93.34.92.177]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-4283e7804f4sm12692219f8f.10.2025.10.20.04.11.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 04:11:40 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, upstream@airoha.com Subject: [PATCH v6 2/5] dt-bindings: PCI: mediatek: Add support for Airoha AN7583 Date: Mon, 20 Oct 2025 13:11:06 +0200 Message-ID: <20251020111121.31779-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251020111121.31779-1-ansuelsmth@gmail.com> References: <20251020111121.31779-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce Airoha AN7583 SoC compatible in mediatek PCIe controller binding. Similar to GEN3, the Airoha AN7583 GEN2 PCIe controller require the PBUS csr property to permit the correct functionality of the PCIe controller. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/mediatek-pcie.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/mediatek-pcie.yaml index fca6cb20d18b..0b8c78ec4f91 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - airoha,an7583-pcie - mediatek,mt2712-pcie - mediatek,mt7622-pcie - mediatek,mt7629-pcie @@ -40,6 +41,12 @@ properties: - enum: [ obff_ck0, obff_ck1 ] - enum: [ pipe_ck0, pipe_ck1 ] =20 + resets: + maxItems: 1 + + reset-names: + const: pcie-rst1 + interrupts: maxItems: 1 =20 @@ -55,6 +62,17 @@ properties: power-domains: maxItems: 1 =20 + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + '#interrupt-cells': const: 1 =20 @@ -90,6 +108,33 @@ required: allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# =20 + - if: + properties: + compatible: + const: airoha,an7583-pcie + then: + properties: + reg-names: + const: port1 + + clocks: + maxItems: 1 + + clock-names: + const: sys_ck1 + + phy-names: + const: pcie-phy1 + + power-domain: false + + required: + - resets + - reset-names + - phys + - phy-names + - mediatek,pbus-csr + - if: properties: compatible: @@ -104,8 +149,14 @@ allOf: minItems: 2 maxItems: 2 =20 + reset: false + + reset-names: false + power-domains: false =20 + mediatek,pbus-csr: false + required: - phys - phy-names @@ -119,10 +170,16 @@ allOf: clocks: minItems: 6 =20 + reset: false + + reset-names: false + phys: false =20 phy-names: false =20 + mediatek,pbus-csr: false + required: - power-domains =20 @@ -135,6 +192,12 @@ allOf: clocks: minItems: 6 =20 + reset: false + + reset-names: false + + mediatek,pbus-csr: false + required: - power-domains =20 @@ -151,12 +214,18 @@ allOf: clock-names: maxItems: 1 =20 + reset: false + + reset-names: false + phys: false =20 phy-names: false =20 power-domain: false =20 + mediatek,pbus-csr: false + unevaluatedProperties: false =20 examples: @@ -316,3 +385,54 @@ examples: }; }; }; + + # AN7583 + - | + #include + #include + #include + + soc_3 { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1fa92000 { + compatible =3D "airoha,an7583-pcie"; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + reg =3D <0x0 0x1fa92000 0x0 0x1670>; + reg-names =3D "port1"; + + clocks =3D <&scuclk EN7523_CLK_PCIE>; + clock-names =3D "sys_ck1"; + + phys =3D <&pciephy>; + phy-names =3D "pcie-phy1"; + + ranges =3D <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000= >; + + resets =3D <&scuclk>; /* AN7583_PCIE1_RST */ + reset-names =3D "pcie-rst1"; + + mediatek,pbus-csr =3D <&pbus_csr 0x8 0xc>; + + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + bus-range =3D <0x00 0xff>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + + pcie_intc1_4: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; --=20 2.51.0