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[93.34.92.177]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-4283e7804f4sm12692219f8f.10.2025.10.20.04.11.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 04:11:39 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, upstream@airoha.com Subject: [PATCH v6 1/5] dt-bindings: PCI: mediatek: Convert to YAML schema Date: Mon, 20 Oct 2025 13:11:05 +0200 Message-ID: <20251020111121.31779-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251020111121.31779-1-ansuelsmth@gmail.com> References: <20251020111121.31779-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the PCI mediatek Documentation to YAML schema to enable validation of the supported GEN1/2 Mediatek PCIe controller. While converting, lots of cleanup were done from the .txt with better specifying what is supported by the various PCIe controller variant and drop of redundant info that are part of the standard PCIe Host Bridge schema. To reduce schema complexity the .txt is split in 2 YAML, one for mt7623/mt2701 and the other for every other compatible. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/mediatek-pcie-mt7623.yaml | 164 +++++++++ .../devicetree/bindings/pci/mediatek-pcie.txt | 289 ---------------- .../bindings/pci/mediatek-pcie.yaml | 318 ++++++++++++++++++ 3 files changed, 482 insertions(+), 289 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-mt7= 623.yaml delete mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yam= l b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml new file mode 100644 index 000000000000..e33bcc216e30 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie-mt7623.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe controller on MediaTek SoCs + +maintainers: + - Christian Marangi + +properties: + compatible: + enum: + - mediatek,mt2701-pcie + - mediatek,mt7623-pcie + + reg: + minItems: 4 + maxItems: 4 + + reg-names: + items: + - const: subsys + - const: port0 + - const: port1 + - const: port2 + + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: free_ck + - const: sys_ck0 + - const: sys_ck1 + - const: sys_ck2 + + resets: + minItems: 3 + maxItems: 3 + + reset-names: + items: + - const: pcie-rst0 + - const: pcie-rst1 + - const: pcie-rst2 + + phys: + minItems: 3 + maxItems: 3 + + phy-names: + items: + - const: pcie-phy0 + - const: pcie-phy1 + - const: pcie-phy2 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - resets + - reset-names + - phys + - phy-names + - power-domains + - pcie@0,0 + - pcie@1,0 + - pcie@2,0 + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +unevaluatedProperties: false + +examples: + # MT7623 + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1a140000 { + compatible =3D "mediatek,mt7623-pcie"; + device_type =3D "pci"; + reg =3D <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ + <0 0x1a142000 0 0x1000>, /* Port0 registers */ + <0 0x1a143000 0 0x1000>, /* Port1 registers */ + <0 0x1a144000 0 0x1000>; /* Port2 registers */ + reg-names =3D "subsys", "port0", "port1", "port2"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0xf800 0 0 0>; + interrupt-map =3D <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_L= EVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEV= EL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEV= EL_LOW>; + clocks =3D <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names =3D "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets =3D <&hifsys MT2701_HIFSYS_PCIE0_RST>, + <&hifsys MT2701_HIFSYS_PCIE1_RST>, + <&hifsys MT2701_HIFSYS_PCIE2_RST>; + reset-names =3D "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys =3D <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE= >, + <&pcie2_phy PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains =3D <&scpsys MT2701_POWER_DOMAIN_HIF>; + bus-range =3D <0x00 0xff>; + ranges =3D <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000>= , /* I/O space */ + <0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; = /* memory space */ + + pcie@0,0 { + device_type =3D "pci"; + reg =3D <0x0000 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LE= VEL_LOW>; + ranges; + }; + + pcie@1,0 { + device_type =3D "pci"; + reg =3D <0x0800 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LE= VEL_LOW>; + ranges; + }; + + pcie@2,0 { + device_type =3D "pci"; + reg =3D <0x1000 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LE= VEL_LOW>; + ranges; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Docu= mentation/devicetree/bindings/pci/mediatek-pcie.txt deleted file mode 100644 index 684227522267..000000000000 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +++ /dev/null @@ -1,289 +0,0 @@ -MediaTek Gen2 PCIe controller - -Required properties: -- compatible: Should contain one of the following strings: - "mediatek,mt2701-pcie" - "mediatek,mt2712-pcie" - "mediatek,mt7622-pcie" - "mediatek,mt7623-pcie" - "mediatek,mt7629-pcie" - "airoha,en7523-pcie" -- device_type: Must be "pci" -- reg: Base addresses and lengths of the root ports. -- reg-names: Names of the above areas to use during resource lookup. -- #address-cells: Address representation for root ports (must be 3) -- #size-cells: Size representation for root ports (must be 2) -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: - Mandatory entries: - - sys_ckN :transaction layer and data link layer clock - Required entries for MT2701/MT7623: - - free_ck :for reference clock of PCIe subsys - Required entries for MT2712/MT7622: - - ahb_ckN :AHB slave interface operating clock for CSR access and RC - initiated MMIO access - Required entries for MT7622: - - axi_ckN :application layer MMIO channel operating clock - - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when - pcie_mac_ck/pcie_pipe_ck is turned off - - obff_ckN :OBFF functional block operating clock - - pipe_ckN :LTSSM and PHY/MAC layer operating clock - where N starting from 0 to one less than the number of root ports. -- phys: List of PHY specifiers (used by generic PHY framework). -- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the - number of PHYs as specified in *phys* property. -- power-domains: A phandle and power domain specifier pair to the power do= main - which is responsible for collapsing and restoring power to the periphera= l. -- bus-range: Range of bus numbers associated with this controller. -- ranges: Ranges for the PCI memory and I/O regions. - -Required properties for MT7623/MT2701: -- #interrupt-cells: Size representation for interrupts (must be 1) -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the - number of root ports. - -Required properties for MT2712/MT7622/MT7629: --interrupts: A list of interrupt outputs of the controller, must have one - entry for each PCIe port -- interrupt-names: Must include the following entries: - - "pcie_irq": The interrupt that is asserted when an MSI/INTX is received -- linux,pci-domain: PCI domain ID. Should be unique for each host controll= er - -In addition, the device tree node must have sub-nodes describing each -PCIe port interface, having the following mandatory properties: - -Required properties: -- device_type: Must be "pci" -- reg: Only the first four bytes are used to refer to the correct bus numb= er - and device number. -- #address-cells: Must be 3 -- #size-cells: Must be 2 -- #interrupt-cells: Must be 1 -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- ranges: Sub-ranges distributed from the PCIe controller node. An empty - property is sufficient. - -Examples for MT7623: - - hifsys: syscon@1a000000 { - compatible =3D "mediatek,mt7623-hifsys", - "mediatek,mt2701-hifsys", - "syscon"; - reg =3D <0 0x1a000000 0 0x1000>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - }; - - pcie: pcie@1a140000 { - compatible =3D "mediatek,mt7623-pcie"; - device_type =3D "pci"; - reg =3D <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ - <0 0x1a142000 0 0x1000>, /* Port0 registers */ - <0 0x1a143000 0 0x1000>, /* Port1 registers */ - <0 0x1a144000 0 0x1000>; /* Port2 registers */ - reg-names =3D "subsys", "port0", "port1", "port2"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0xf800 0 0 0>; - interrupt-map =3D <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, - <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, - <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - clocks =3D <&topckgen CLK_TOP_ETHIF_SEL>, - <&hifsys CLK_HIFSYS_PCIE0>, - <&hifsys CLK_HIFSYS_PCIE1>, - <&hifsys CLK_HIFSYS_PCIE2>; - clock-names =3D "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; - resets =3D <&hifsys MT2701_HIFSYS_PCIE0_RST>, - <&hifsys MT2701_HIFSYS_PCIE1_RST>, - <&hifsys MT2701_HIFSYS_PCIE2_RST>; - reset-names =3D "pcie-rst0", "pcie-rst1", "pcie-rst2"; - phys =3D <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, - <&pcie2_phy PHY_TYPE_PCIE>; - phy-names =3D "pcie-phy0", "pcie-phy1", "pcie-phy2"; - power-domains =3D <&scpsys MT2701_POWER_DOMAIN_HIF>; - bus-range =3D <0x00 0xff>; - ranges =3D <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O spa= ce */ - 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ - - pcie@0,0 { - reg =3D <0x0000 0 0 0 0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - - pcie@1,0 { - reg =3D <0x0800 0 0 0 0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - - pcie@2,0 { - reg =3D <0x1000 0 0 0 0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - }; - -Examples for MT2712: - - pcie1: pcie@112ff000 { - compatible =3D "mediatek,mt2712-pcie"; - device_type =3D "pci"; - reg =3D <0 0x112ff000 0 0x1000>; - reg-names =3D "port1"; - linux,pci-domain =3D <1>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupts =3D ; - interrupt-names =3D "pcie_irq"; - clocks =3D <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE1>; - clock-names =3D "sys_ck1", "ahb_ck1"; - phys =3D <&u3port1 PHY_TYPE_PCIE>; - phy-names =3D "pcie-phy1"; - bus-range =3D <0x00 0xff>; - ranges =3D <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; - status =3D "disabled"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; - - pcie0: pcie@11700000 { - compatible =3D "mediatek,mt2712-pcie"; - device_type =3D "pci"; - reg =3D <0 0x11700000 0 0x1000>; - reg-names =3D "port0"; - linux,pci-domain =3D <0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupts =3D ; - interrupt-names =3D "pcie_irq"; - clocks =3D <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, - <&pericfg CLK_PERI_PCIE0>; - clock-names =3D "sys_ck0", "ahb_ck0"; - phys =3D <&u3port0 PHY_TYPE_PCIE>; - phy-names =3D "pcie-phy0"; - bus-range =3D <0x00 0xff>; - ranges =3D <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; - status =3D "disabled"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; - -Examples for MT7622: - - pcie0: pcie@1a143000 { - compatible =3D "mediatek,mt7622-pcie"; - device_type =3D "pci"; - reg =3D <0 0x1a143000 0 0x1000>; - reg-names =3D "port0"; - linux,pci-domain =3D <0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupts =3D ; - interrupt-names =3D "pcie_irq"; - clocks =3D <&pciesys CLK_PCIE_P0_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, - <&pciesys CLK_PCIE_P0_PIPE_EN>; - clock-names =3D "sys_ck0", "ahb_ck0", "aux_ck0", - "axi_ck0", "obff_ck0", "pipe_ck0"; - - power-domains =3D <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range =3D <0x00 0xff>; - ranges =3D <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status =3D "disabled"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; - - pcie1: pcie@1a145000 { - compatible =3D "mediatek,mt7622-pcie"; - device_type =3D "pci"; - reg =3D <0 0x1a145000 0 0x1000>; - reg-names =3D "port1"; - linux,pci-domain =3D <1>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupts =3D ; - interrupt-names =3D "pcie_irq"; - clocks =3D <&pciesys CLK_PCIE_P1_MAC_EN>, - /* designer has connect RC1 with p0_ahb clock */ - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P1_OBFF_EN>, - <&pciesys CLK_PCIE_P1_PIPE_EN>; - clock-names =3D "sys_ck1", "ahb_ck1", "aux_ck1", - "axi_ck1", "obff_ck1", "pipe_ck1"; - - power-domains =3D <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range =3D <0x00 0xff>; - ranges =3D <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; - status =3D "disabled"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/mediatek-pcie.yaml new file mode 100644 index 000000000000..fca6cb20d18b --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -0,0 +1,318 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe controller on MediaTek SoCs + +maintainers: + - Christian Marangi + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2712-pcie + - mediatek,mt7622-pcie + - mediatek,mt7629-pcie + - items: + - const: airoha,en7523-pcie + - const: mediatek,mt7622-pcie + + reg: + maxItems: 1 + + reg-names: + enum: [ port0, port1 ] + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + items: + - enum: [ sys_ck0, sys_ck1 ] + - enum: [ ahb_ck0, ahb_ck1 ] + - enum: [ aux_ck0, aux_ck1 ] + - enum: [ axi_ck0, axi_ck1 ] + - enum: [ obff_ck0, obff_ck1 ] + - enum: [ pipe_ck0, pipe_ck1 ] + + interrupts: + maxItems: 1 + + interrupt-names: + const: pcie_irq + + phys: + maxItems: 1 + + phy-names: + enum: [ pcie-phy0, pcie-phy1 ] + + power-domains: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: + description: Interrupt controller node for handling legacy PCI interru= pts. + type: object + properties: + '#address-cells': + const: 0 + '#interrupt-cells': + const: 1 + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - interrupts + - interrupt-names + - interrupt-controller + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + + - if: + properties: + compatible: + const: mediatek,mt2712-pcie + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + minItems: 2 + maxItems: 2 + + power-domains: false + + required: + - phys + - phy-names + + - if: + properties: + compatible: + const: mediatek,mt7622-pcie + then: + properties: + clocks: + minItems: 6 + + phys: false + + phy-names: false + + required: + - power-domains + + - if: + properties: + compatible: + const: mediatek,mt7629-pcie + then: + properties: + clocks: + minItems: 6 + + required: + - power-domains + + - if: + properties: + compatible: + contains: + const: airoha,en7523-pcie + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + phys: false + + phy-names: false + + power-domain: false + +unevaluatedProperties: false + +examples: + # MT2712 + - | + #include + #include + #include + + soc_1 { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@112ff000 { + compatible =3D "mediatek,mt2712-pcie"; + device_type =3D "pci"; + reg =3D <0 0x112ff000 0 0x1000>; + reg-names =3D "port1"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + clocks =3D <&topckgen>, /* CLK_TOP_PE2_MAC_P1_SEL */ + <&pericfg>; /* CLK_PERI_PCIE1 */ + clock-names =3D "sys_ck1", "ahb_ck1"; + phys =3D <&u3port1 PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy1"; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x11400000 0x0 0x11400000 0 0x30000= 0>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + + pcie@11700000 { + compatible =3D "mediatek,mt2712-pcie"; + device_type =3D "pci"; + reg =3D <0 0x11700000 0 0x1000>; + reg-names =3D "port0"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + clocks =3D <&topckgen>, /* CLK_TOP_PE2_MAC_P0_SEL */ + <&pericfg>; /* CLK_PERI_PCIE0 */ + clock-names =3D "sys_ck0", "ahb_ck0"; + phys =3D <&u3port0 PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy0"; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x20000000 0x0 0x20000000 0 0x1000000= 0>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; + + # MT7622 + - | + #include + #include + #include + + soc_2 { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1a143000 { + compatible =3D "mediatek,mt7622-pcie"; + device_type =3D "pci"; + reg =3D <0 0x1a143000 0 0x1000>; + reg-names =3D "port0"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + clocks =3D <&pciesys>, /* CLK_PCIE_P0_MAC_EN */ + <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ + <&pciesys>, /* CLK_PCIE_P0_AUX_EN */ + <&pciesys>, /* CLK_PCIE_P0_AXI_EN */ + <&pciesys>, /* CLK_PCIE_P0_OBFF_EN */ + <&pciesys>; /* CLK_PCIE_P0_PIPE_EN */ + clock-names =3D "sys_ck0", "ahb_ck0", "aux_ck0", + "axi_ck0", "obff_ck0", "pipe_ck0"; + + power-domains =3D <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x20000000 0x0 0x20000000 0 0x80000= 00>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0_1 0>, + <0 0 0 2 &pcie_intc0_1 1>, + <0 0 0 3 &pcie_intc0_1 2>, + <0 0 0 4 &pcie_intc0_1 3>; + pcie_intc0_1: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + + pcie@1a145000 { + compatible =3D "mediatek,mt7622-pcie"; + device_type =3D "pci"; + reg =3D <0 0x1a145000 0 0x1000>; + reg-names =3D "port1"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + clocks =3D <&pciesys>, /* CLK_PCIE_P1_MAC_EN */ + /* designer has connect RC1 with p0_ahb clock */ + <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ + <&pciesys>, /* CLK_PCIE_P1_AUX_EN */ + <&pciesys>, /* CLK_PCIE_P1_AXI_EN */ + <&pciesys>, /* CLK_PCIE_P1_OBFF_EN */ + <&pciesys>; /* CLK_PCIE_P1_PIPE_EN */ + clock-names =3D "sys_ck1", "ahb_ck1", "aux_ck1", + "axi_ck1", "obff_ck1", "pipe_ck1"; + + power-domains =3D <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x28000000 0x0 0x28000000 0 0x80000= 00>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1_1 0>, + <0 0 0 2 &pcie_intc1_1 1>, + <0 0 0 3 &pcie_intc1_1 2>, + <0 0 0 4 &pcie_intc1_1 3>; + pcie_intc1_1: interrupt-controller { + interrupt-controller; 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[93.34.92.177]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-4283e7804f4sm12692219f8f.10.2025.10.20.04.11.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 04:11:40 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, upstream@airoha.com Subject: [PATCH v6 2/5] dt-bindings: PCI: mediatek: Add support for Airoha AN7583 Date: Mon, 20 Oct 2025 13:11:06 +0200 Message-ID: <20251020111121.31779-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251020111121.31779-1-ansuelsmth@gmail.com> References: <20251020111121.31779-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce Airoha AN7583 SoC compatible in mediatek PCIe controller binding. Similar to GEN3, the Airoha AN7583 GEN2 PCIe controller require the PBUS csr property to permit the correct functionality of the PCIe controller. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/mediatek-pcie.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/mediatek-pcie.yaml index fca6cb20d18b..0b8c78ec4f91 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - airoha,an7583-pcie - mediatek,mt2712-pcie - mediatek,mt7622-pcie - mediatek,mt7629-pcie @@ -40,6 +41,12 @@ properties: - enum: [ obff_ck0, obff_ck1 ] - enum: [ pipe_ck0, pipe_ck1 ] =20 + resets: + maxItems: 1 + + reset-names: + const: pcie-rst1 + interrupts: maxItems: 1 =20 @@ -55,6 +62,17 @@ properties: power-domains: maxItems: 1 =20 + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + '#interrupt-cells': const: 1 =20 @@ -90,6 +108,33 @@ required: allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# =20 + - if: + properties: + compatible: + const: airoha,an7583-pcie + then: + properties: + reg-names: + const: port1 + + clocks: + maxItems: 1 + + clock-names: + const: sys_ck1 + + phy-names: + const: pcie-phy1 + + power-domain: false + + required: + - resets + - reset-names + - phys + - phy-names + - mediatek,pbus-csr + - if: properties: compatible: @@ -104,8 +149,14 @@ allOf: minItems: 2 maxItems: 2 =20 + reset: false + + reset-names: false + power-domains: false =20 + mediatek,pbus-csr: false + required: - phys - phy-names @@ -119,10 +170,16 @@ allOf: clocks: minItems: 6 =20 + reset: false + + reset-names: false + phys: false =20 phy-names: false =20 + mediatek,pbus-csr: false + required: - power-domains =20 @@ -135,6 +192,12 @@ allOf: clocks: minItems: 6 =20 + reset: false + + reset-names: false + + mediatek,pbus-csr: false + required: - power-domains =20 @@ -151,12 +214,18 @@ allOf: clock-names: maxItems: 1 =20 + reset: false + + reset-names: false + phys: false =20 phy-names: false =20 power-domain: false =20 + mediatek,pbus-csr: false + unevaluatedProperties: false =20 examples: @@ -316,3 +385,54 @@ examples: }; }; }; + + # AN7583 + - | + #include + #include + #include + + soc_3 { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1fa92000 { + compatible =3D "airoha,an7583-pcie"; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + reg =3D <0x0 0x1fa92000 0x0 0x1670>; + reg-names =3D "port1"; + + clocks =3D <&scuclk EN7523_CLK_PCIE>; + clock-names =3D "sys_ck1"; + + phys =3D <&pciephy>; + phy-names =3D "pcie-phy1"; + + ranges =3D <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000= >; + + resets =3D <&scuclk>; /* AN7583_PCIE1_RST */ + reset-names =3D "pcie-rst1"; + + mediatek,pbus-csr =3D <&pbus_csr 0x8 0xc>; + + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + bus-range =3D <0x00 0xff>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + + pcie_intc1_4: interrupt-controller { + interrupt-controller; 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[93.34.92.177]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-4283e7804f4sm12692219f8f.10.2025.10.20.04.11.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 04:11:42 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, upstream@airoha.com Subject: [PATCH v6 3/5] PCI: mediatek: Convert bool to single quirks entry and bitmap Date: Mon, 20 Oct 2025 13:11:07 +0200 Message-ID: <20251020111121.31779-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251020111121.31779-1-ansuelsmth@gmail.com> References: <20251020111121.31779-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To clean Mediatek SoC PCIe struct, convert all the bool to a bitmap and use a single quirks to reference all the values. This permits cleaner addition of new quirk without having to define a new bool in the struct. Signed-off-by: Christian Marangi Reviewed-by: AngeloGioacchino Del Regno --- drivers/pci/controller/pcie-mediatek.c | 33 ++++++++++++++++---------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 24cc30a2ab6c..cbffa3156da1 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -142,24 +142,32 @@ =20 struct mtk_pcie_port; =20 +/** + * enum mtk_pcie_quirks - MTK PCIe quirks + * @MTK_PCIE_FIX_CLASS_ID: host's class ID needed to be fixed + * @MTK_PCIE_FIX_DEVICE_ID: host's device ID needed to be fixed + * @MTK_PCIE_NO_MSI: Bridge has no MSI support, and relies on an external = block + */ +enum mtk_pcie_quirks { + MTK_PCIE_FIX_CLASS_ID =3D BIT(0), + MTK_PCIE_FIX_DEVICE_ID =3D BIT(1), + MTK_PCIE_NO_MSI =3D BIT(2), +}; + /** * struct mtk_pcie_soc - differentiate between host generations - * @need_fix_class_id: whether this host's class ID needed to be fixed or = not - * @need_fix_device_id: whether this host's device ID needed to be fixed o= r not - * @no_msi: Bridge has no MSI support, and relies on an external block * @device_id: device ID which this host need to be fixed * @ops: pointer to configuration access functions * @startup: pointer to controller setting functions * @setup_irq: pointer to initialize IRQ functions + * @quirks: PCIe device quirks. */ struct mtk_pcie_soc { - bool need_fix_class_id; - bool need_fix_device_id; - bool no_msi; unsigned int device_id; struct pci_ops *ops; int (*startup)(struct mtk_pcie_port *port); int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); + enum mtk_pcie_quirks quirks; }; =20 /** @@ -703,7 +711,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_por= t *port) writel(val, port->base + PCIE_RST_CTRL); =20 /* Set up vendor ID and class code */ - if (soc->need_fix_class_id) { + if (soc->quirks & MTK_PCIE_FIX_CLASS_ID) { val =3D PCI_VENDOR_ID_MEDIATEK; writew(val, port->base + PCIE_CONF_VEND_ID); =20 @@ -711,7 +719,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_por= t *port) writew(val, port->base + PCIE_CONF_CLASS_ID); } =20 - if (soc->need_fix_device_id) + if (soc->quirks & MTK_PCIE_FIX_DEVICE_ID) writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID); =20 /* 100ms timeout value should be enough for Gen1/2 training */ @@ -1099,7 +1107,7 @@ static int mtk_pcie_probe(struct platform_device *pde= v) =20 host->ops =3D pcie->soc->ops; host->sysdata =3D pcie; - host->msi_domain =3D pcie->soc->no_msi; + host->msi_domain =3D !!(pcie->soc->quirks & MTK_PCIE_NO_MSI); =20 err =3D pci_host_probe(host); if (err) @@ -1187,9 +1195,9 @@ static const struct dev_pm_ops mtk_pcie_pm_ops =3D { }; =20 static const struct mtk_pcie_soc mtk_pcie_soc_v1 =3D { - .no_msi =3D true, .ops =3D &mtk_pcie_ops, .startup =3D mtk_pcie_startup_port, + .quirks =3D MTK_PCIE_NO_MSI, }; =20 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 =3D { @@ -1199,19 +1207,18 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt271= 2 =3D { }; =20 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 =3D { - .need_fix_class_id =3D true, .ops =3D &mtk_pcie_ops_v2, .startup =3D mtk_pcie_startup_port_v2, .setup_irq =3D mtk_pcie_setup_irq, + .quirks =3D MTK_PCIE_FIX_CLASS_ID, }; =20 static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 =3D { - .need_fix_class_id =3D true, - .need_fix_device_id =3D true, .device_id =3D PCI_DEVICE_ID_MEDIATEK_7629, .ops =3D &mtk_pcie_ops_v2, .startup =3D mtk_pcie_startup_port_v2, .setup_irq =3D mtk_pcie_setup_irq, + .quirks =3D MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_FIX_DEVICE_ID, }; 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[93.34.92.177]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-4283e7804f4sm12692219f8f.10.2025.10.20.04.11.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 04:11:43 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, upstream@airoha.com Subject: [PATCH v6 4/5] PCI: mediatek: Use generic MACRO for TPVPERL delay Date: Mon, 20 Oct 2025 13:11:08 +0200 Message-ID: <20251020111121.31779-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251020111121.31779-1-ansuelsmth@gmail.com> References: <20251020111121.31779-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the generic PCIe MACRO for TPVPERL delay to wait for clock and power stabilization after PERST# Signal instead of the raw value of 100 ms. Signed-off-by: Christian Marangi Reviewed-by: AngeloGioacchino Del Regno --- drivers/pci/controller/pcie-mediatek.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index cbffa3156da1..313da61a0b8a 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -697,12 +697,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_po= rt *port) */ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); =20 - /* - * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and - * 2.2.1 (Initial Power-Up (G3 to S0)). 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[93.34.92.177]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-4283e7804f4sm12692219f8f.10.2025.10.20.04.11.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 04:11:45 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, upstream@airoha.com Subject: [PATCH v6 5/5] PCI: mediatek: Add support for Airoha AN7583 SoC Date: Mon, 20 Oct 2025 13:11:09 +0200 Message-ID: <20251020111121.31779-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251020111121.31779-1-ansuelsmth@gmail.com> References: <20251020111121.31779-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the second PCIe Root Complex present on Airoha AN7583 SoC. This is based on the Mediatek Gen1/2 PCIe driver and similar to Gen3 also require workaround for the reset signals. Introduce a new quirk to skip having to reset signals and also introduce some additional logic to configure the PBUS registers required for Airoha SoC. Signed-off-by: Christian Marangi Reviewed-by: AngeloGioacchino Del Regno --- drivers/pci/controller/pcie-mediatek.c | 75 +++++++++++++++++++++----- 1 file changed, 61 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 313da61a0b8a..4b78b6528f9f 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -147,11 +147,13 @@ struct mtk_pcie_port; * @MTK_PCIE_FIX_CLASS_ID: host's class ID needed to be fixed * @MTK_PCIE_FIX_DEVICE_ID: host's device ID needed to be fixed * @MTK_PCIE_NO_MSI: Bridge has no MSI support, and relies on an external = block + * @MTK_PCIE_SKIP_RSTB: Skip calling RSTB bits on PCIe probe */ enum mtk_pcie_quirks { MTK_PCIE_FIX_CLASS_ID =3D BIT(0), MTK_PCIE_FIX_DEVICE_ID =3D BIT(1), MTK_PCIE_NO_MSI =3D BIT(2), + MTK_PCIE_SKIP_RSTB =3D BIT(3), }; =20 /** @@ -687,23 +689,25 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_p= ort *port) regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); } =20 - /* Assert all reset signals */ - writel(0, port->base + PCIE_RST_CTRL); + if (!(soc->quirks & MTK_PCIE_SKIP_RSTB)) { + /* Assert all reset signals */ + writel(0, port->base + PCIE_RST_CTRL); =20 - /* - * Enable PCIe link down reset, if link status changed from link up to - * link down, this will reset MAC control registers and configuration - * space. - */ - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + /* + * Enable PCIe link down reset, if link status changed from + * link up to link down, this will reset MAC control registers + * and configuration space. + */ + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); =20 - msleep(PCIE_T_PVPERL_MS); + msleep(PCIE_T_PVPERL_MS); =20 - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ - val =3D readl(port->base + PCIE_RST_CTRL); - val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | - PCIE_MAC_SRSTB | PCIE_CRSTB; - writel(val, port->base + PCIE_RST_CTRL); + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ + val =3D readl(port->base + PCIE_RST_CTRL); + val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | + PCIE_MAC_SRSTB | PCIE_CRSTB; + writel(val, port->base + PCIE_RST_CTRL); + } =20 /* Set up vendor ID and class code */ if (soc->quirks & MTK_PCIE_FIX_CLASS_ID) { @@ -824,6 +828,41 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port = *port) return 0; } =20 +static int mtk_pcie_startup_port_an7583(struct mtk_pcie_port *port) +{ + struct mtk_pcie *pcie =3D port->pcie; + struct device *dev =3D pcie->dev; + struct pci_host_bridge *host; + struct resource_entry *entry; + struct regmap *pbus_regmap; + resource_size_t addr; + u32 args[2], size; + + /* + * Configure PBus base address and base address mask to allow + * the hw to detect if a given address is accessible on PCIe + * controller. + */ + pbus_regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, + "mediatek,pbus-csr", + ARRAY_SIZE(args), + args); + if (IS_ERR(pbus_regmap)) + return PTR_ERR(pbus_regmap); + + host =3D pci_host_bridge_from_priv(pcie); + entry =3D resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (!entry) + return -ENODEV; + + addr =3D entry->res->start - entry->offset; + regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); + size =3D lower_32_bits(resource_size(entry->res)); + regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); + + return mtk_pcie_startup_port_v2(port); +} + static void mtk_pcie_enable_port(struct mtk_pcie_port *port) { struct mtk_pcie *pcie =3D port->pcie; @@ -1208,6 +1247,13 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622= =3D { .quirks =3D MTK_PCIE_FIX_CLASS_ID, }; =20 +static const struct mtk_pcie_soc mtk_pcie_soc_an7583 =3D { + .ops =3D &mtk_pcie_ops_v2, + .startup =3D mtk_pcie_startup_port_an7583, + .setup_irq =3D mtk_pcie_setup_irq, + .quirks =3D MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_SKIP_RSTB, +}; + static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 =3D { .device_id =3D PCI_DEVICE_ID_MEDIATEK_7629, .ops =3D &mtk_pcie_ops_v2, @@ -1217,6 +1263,7 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = =3D { }; =20 static const struct of_device_id mtk_pcie_ids[] =3D { + { .compatible =3D "airoha,an7583-pcie", .data =3D &mtk_pcie_soc_an7583 }, { .compatible =3D "mediatek,mt2701-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt7623-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt2712-pcie", .data =3D &mtk_pcie_soc_mt2712 = }, --=20 2.51.0