From nobody Sat Feb 7 12:34:42 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 01ECF2F60CF; Mon, 20 Oct 2025 09:36:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760953005; cv=none; b=U0KTLkUoLD3u/UbAJwCCwdJhoPDY23o/e0SRb386MbQAWVODUegPphQgr/9cVX7X8QQ44e8y11z8/ArOporDq3ywiSgXdDN7ghU/KF3T78zN4UWireqHuKbZRS25Kt6n8YDNPg5CwgUv1AWqEwZt1cs29JXzHjybbfxSuhF0bdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760953005; c=relaxed/simple; bh=gc86lHsVIlZUMjMNFCTo3ipcmmAyDi/CksELkLflYHc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uWCvcxIy+xvE3IiyuCuBCowWN9zKuYrhTcZfuRsz1tMLrn4n+AyqwOF6sAL75vQur8/X/St9maNAUQza3UQywVGhs1Fbn+6oJ4C29dkD2jYKcz3/8lPn8ACWF8l5QeCnkbe/RjPSQgVjOf4N1794o+joxqgw8DmPwPhq8vY6Tdo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 98DAD1F91; Mon, 20 Oct 2025 02:36:32 -0700 (PDT) Received: from e125769.cambridge.arm.com (e125769.cambridge.arm.com [10.1.196.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6F0273F66E; Mon, 20 Oct 2025 02:36:39 -0700 (PDT) From: Ryan Roberts To: stable@vger.kernel.org Cc: Ryan Roberts , catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, James Morse Subject: [RESEND PATCH 6.16-6.17 1/2] arm64: cputype: Add Neoverse-V3AE definitions Date: Mon, 20 Oct 2025 10:36:25 +0100 Message-ID: <20251020093628.592682-2-ryan.roberts@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251020093628.592682-1-ryan.roberts@arm.com> References: <20251020093628.592682-1-ryan.roberts@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mark Rutland [ Upstream commit 3bbf004c4808e2c3241e5c1ad6cc102f38a03c39 ] Add cputype definitions for Neoverse-V3AE. These will be used for errata detection in subsequent patches. These values can be found in the Neoverse-V3AE TRM: https://developer.arm.com/documentation/SDEN-2615521/9-0/ ... in section A.6.1 ("MIDR_EL1, Main ID Register"). Signed-off-by: Mark Rutland Cc: James Morse Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Ryan Roberts Signed-off-by: Will Deacon [ Ryan: Trivial backport ] Signed-off-by: Ryan Roberts --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cput= ype.h index 661735616787..eaec55dd3dbe 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -93,6 +93,7 @@ #define ARM_CPU_PART_NEOVERSE_V2 0xD4F #define ARM_CPU_PART_CORTEX_A720 0xD81 #define ARM_CPU_PART_CORTEX_X4 0xD82 +#define ARM_CPU_PART_NEOVERSE_V3AE 0xD83 #define ARM_CPU_PART_NEOVERSE_V3 0xD84 #define ARM_CPU_PART_CORTEX_X925 0xD85 #define ARM_CPU_PART_CORTEX_A725 0xD87 @@ -182,6 +183,7 @@ #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOV= ERSE_V2) #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A720) #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX= _X4) +#define MIDR_NEOVERSE_V3AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NE= OVERSE_V3AE) #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOV= ERSE_V3) #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_X925) #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A725) -- 2.43.0 From nobody Sat Feb 7 12:34:42 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AF1862A1CF; Mon, 20 Oct 2025 09:36:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760953007; cv=none; b=jIhtCuB4/WWD8hHxAp++eJa3knhDTFTw6UkyyM8kuObZ57moiC54+DnjdWalzI7P+NcZ5E6613bRHEfSn1smSNSGSIuOfGa5Otxw+byQQt81MHXeEeNzCL5GJ1wwQ+2grCK7bJvJ4uJCoVwZqhTe7oP3vjQ0J5rWW6lNqHMScYM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760953007; c=relaxed/simple; bh=gGUcdt7t5ZFwBl5Ats+3GCWpDl85488BzD1lXNiCkVE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rReOZSatPIkIeC4mZLTfqLH9eh5ofOVvI9K1I7Y2dzA+IMjNMUwewpv5si78lJDWBCjMwkUm9/k0IkiVENlcBTOttd/o4Z/lN+N3hzS0fgPWUi8AiPWkUt1j3IgO2Tfu3sbkYc8XoO5ua+yuEHIyNxFfkUnOtWd9mVxtbo5cLcU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E210E22C7; Mon, 20 Oct 2025 02:36:33 -0700 (PDT) Received: from e125769.cambridge.arm.com (e125769.cambridge.arm.com [10.1.196.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B857C3F66E; Mon, 20 Oct 2025 02:36:40 -0700 (PDT) From: Ryan Roberts To: stable@vger.kernel.org Cc: Ryan Roberts , catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, James Morse Subject: [RESEND PATCH 6.16-6.17 2/2] arm64: errata: Apply workarounds for Neoverse-V3AE Date: Mon, 20 Oct 2025 10:36:26 +0100 Message-ID: <20251020093628.592682-3-ryan.roberts@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251020093628.592682-1-ryan.roberts@arm.com> References: <20251020093628.592682-1-ryan.roberts@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mark Rutland [ Upstream commit 0c33aa1804d101c11ba1992504f17a42233f0e11 ] Neoverse-V3AE is also affected by erratum #3312417, as described in its Software Developer Errata Notice (SDEN) document: Neoverse V3AE (MP172) SDEN v9.0, erratum 3312417 https://developer.arm.com/documentation/SDEN-2615521/9-0/ Enable the workaround for Neoverse-V3AE, and document this. Signed-off-by: Mark Rutland Cc: James Morse Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Ryan Roberts Signed-off-by: Will Deacon [ Ryan: Trivial backport ] Signed-off-by: Ryan Roberts --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 1 + arch/arm64/kernel/cpu_errata.c | 1 + 3 files changed, 4 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index b18ef4064bc0..a7ec57060f64 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -200,6 +200,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_31943= 86 | +----------------+-----------------+-----------------+--------------------= ---------+ +| ARM | Neoverse-V3AE | #3312417 | ARM64_ERRATUM_31943= 86 | ++----------------+-----------------+-----------------+--------------------= ---------+ | ARM | MMU-500 | #841119,826419 | ARM_SMMU_MMU_500_CP= RE_ERRATA| | | | #562869,1047329 | = | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 393d71124f5d..1503b78f8611 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1137,6 +1137,7 @@ config ARM64_ERRATUM_3194386 * ARM Neoverse-V1 erratum 3324341 * ARM Neoverse V2 erratum 3324336 * ARM Neoverse-V3 erratum 3312417 + * ARM Neoverse-V3AE erratum 3312417 On affected cores "MSR SSBS, #0" instructions may not affect subsequent speculative instructions, which may permit unexepected diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 59d723c9ab8f..21f86c160aab 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -545,6 +545,7 @@ static const struct midr_range erratum_spec_ssbs_list[]= =3D { MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE), {} }; #endif -- 2.43.0