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Signed-off-by: Xiandong Wang --- .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aa= l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.ya= ml index daf90ebb39bf..f575835c091d 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -38,6 +38,7 @@ properties: - enum: - mediatek,mt8186-disp-aal - mediatek,mt8188-disp-aal + - mediatek,mt8189-disp-aal - mediatek,mt8192-disp-aal - mediatek,mt8195-disp-aal - mediatek,mt8365-disp-aal --=20 2.46.0 From nobody Sun Feb 8 14:34:29 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F21902DF6E3; Mon, 20 Oct 2025 07:42:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760946149; cv=none; b=tfgNYQfGgfsV5PZYG/31mbB5hSynoIViyEjJDwf/2Z35a7Lqk/mgFJRykVq968eYvI6EvK6ElsWjmGh4Fu7s+hocNROzY+PbynNGXwKB9Tcg0DkEoxIfu82CMMyN7PUVeKTcG+VN/MmRtsvqgUC3nUt9XRfFSK8fd3l5l43FdXc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760946149; c=relaxed/simple; bh=ncpVjYMh5hlgEaQ0MT9ho6u3WvuepX9MTuhtxVWyZno=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JJbbvYvDPxfjVNCLmDFndEV39AebDBeYagNqe8nSDeMcSJy5XHYqfMTLzFsdsxkSxKt1ss2PEbXgiwGvT2bXYy7pc8veVsZUyVR5ByOUaSUS0M4MbBQwFwkItPN0ugnNiEUL856ipTdjXT38UFVZVkjjjX/uxPvM5fGiVO3IA8o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=RQePEAIN; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="RQePEAIN" X-UUID: 4f838e44ad8811f0b33aeb1e7f16c2b6-20251020 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=rWzu47myTmzn8jK2fgTmAhC2DtJpewFrjRoUK6XaZNU=; b=RQePEAINU1XP5Z7FscGCcOBWzZjapPXaAFlto84QrStRHOx8ZuGUnpnpDj0mh1q1alYGEV8IdZOE5jb+hOMJsxSUtDq9y0Lt9UbiBovG4tDk3nEIBgkSAb/BjpzMWSzRU/5kBHJlS2KH5CDor3QD6Q+cVKFpPaH8Y5glDgygwtQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:da9ddcb0-2da4-42d5-939a-892932fab1f2,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:a9d874c,CLOUDID:1b9c3e51-c509-4cf3-8dc0-fcdaad49a6d3,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 4f838e44ad8811f0b33aeb1e7f16c2b6-20251020 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 473401951; Mon, 20 Oct 2025 15:42:20 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Mon, 20 Oct 2025 15:42:15 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Mon, 20 Oct 2025 15:42:14 +0800 From: Xiandong Wang To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu CC: , , , , , , , , Xiandong Wang Subject: [PATCH v1 02/13] dt-bindings: soc: mediatek: add ccorr yaml for MT8189 Date: Mon, 20 Oct 2025 15:40:15 +0800 Message-ID: <20251020074211.8942-3-xiandong.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251020074211.8942-1-xiandong.wang@mediatek.com> References: <20251020074211.8942-1-xiandong.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string to support ccorr for MT8189. Signed-off-by: Xiandong Wang --- .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,cc= orr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccor= r.yaml index fca8e7bb0cbc..5fe58ebdd47b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -31,6 +31,7 @@ properties: - enum: - mediatek,mt8186-disp-ccorr - mediatek,mt8188-disp-ccorr + - mediatek,mt8189-disp-ccorr - mediatek,mt8195-disp-ccorr - const: mediatek,mt8192-disp-ccorr =20 --=20 2.46.0 From nobody Sun Feb 8 14:34:29 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 824702E090A; Mon, 20 Oct 2025 07:42:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760946152; cv=none; b=oC+TRVMqcuUiRoSBUDKibcgU3AfrVJE01eXWxqwCQLGTgfPgflP1uPHg8yE4yaoNUxIjwjzMrw3/7yotSKiLGfZQ8ElG6hNn7xAUEmgGtWdCH72qok/hE3VZ8jYN1NNyX6JOuWvhX8e2qJXJ8/0snV5f88MouTxLhEgrDjp8yWg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760946152; c=relaxed/simple; bh=EgoL/7w1SEIFGXcsaeJuEKKkR7c1swpvZfpovLPEHf4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SmfDYZuYs1vRWjuDLU8oVYEu9opDtQ0HeKnswxN4JA6AoCX3yK8ksaoizQ/uQIZlvzJrydsBZaonoCSYCH1hNVbrm++HuH1taskXZzpH71DB18tcqsT/2tvSPjARzwdNMFX+dGMj9oxCkV4dGLfo7ToITLdl/CmxzPUJTCi/938= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=spP8V38x; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="spP8V38x" X-UUID: 507b00a2ad8811f0b33aeb1e7f16c2b6-20251020 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=icMfwQuZjrHTU1Zdznkm/VRZILo7qFbxizmilmpHG44=; b=spP8V38xK3gCmoG399lH9CIrZ3uGEk5HeNNkZA+3RODsji1NrdFIRvOHvQhQlUcqrUxfty4q3NSKvKVuNijCVvasFPMMmm0p0pUgg+bl6IROjAfSmZeQJPTnqVfVgaJxw13gZg7RngeZM6IKJIUPlwk4sZKCJzoG+tqluR5cRHM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:f23b14bf-1091-4aee-90b5-108c843cfbc3,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:a9d874c,CLOUDID:419c3e51-c509-4cf3-8dc0-fcdaad49a6d3,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 507b00a2ad8811f0b33aeb1e7f16c2b6-20251020 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1828730487; Mon, 20 Oct 2025 15:42:22 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Mon, 20 Oct 2025 15:42:16 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Mon, 20 Oct 2025 15:42:16 +0800 From: Xiandong Wang To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu CC: , , , , , , , , Xiandong Wang Subject: [PATCH v1 03/13] dt-bindings: soc: mediatek: add color yaml for MT8189 Date: Mon, 20 Oct 2025 15:40:16 +0800 Message-ID: <20251020074211.8942-4-xiandong.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251020074211.8942-1-xiandong.wang@mediatek.com> References: <20251020074211.8942-1-xiandong.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string to support color for MT8189. Signed-off-by: Xiandong Wang --- .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,co= lor.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,colo= r.yaml index 5564f4063317..8fcdefa6eb9a 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -42,6 +42,7 @@ properties: - mediatek,mt8183-disp-color - mediatek,mt8186-disp-color - mediatek,mt8188-disp-color + - mediatek,mt8189-disp-color - mediatek,mt8192-disp-color - mediatek,mt8195-disp-color - mediatek,mt8365-disp-color --=20 2.46.0 From nobody Sun Feb 8 14:34:29 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2678E2E0402; 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charset="utf-8" Add compatible string to support dither for MT8189. Signed-off-by: Xiandong Wang --- .../devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,di= ther.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dit= her.yaml index abaf27916d13..be4be0e20de8 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ya= ml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ya= ml @@ -28,6 +28,7 @@ properties: - enum: - mediatek,mt8186-disp-dither - mediatek,mt8188-disp-dither + - mediatek,mt8189-disp-dither - mediatek,mt8192-disp-dither - mediatek,mt8195-disp-dither - mediatek,mt8365-disp-dither --=20 2.46.0 From nobody Sun Feb 8 14:34:29 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 735DC2E1C7B; Mon, 20 Oct 2025 07:42:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add compatible string to support gamma for MT8189. Signed-off-by: Xiandong Wang --- .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ga= mma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamm= a.yaml index 48542dc7e784..6dd35d9e1144 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -33,6 +33,7 @@ properties: - enum: - mediatek,mt8186-disp-gamma - mediatek,mt8188-disp-gamma + - mediatek,mt8189-disp-gamma - mediatek,mt8192-disp-gamma - mediatek,mt8195-disp-gamma - mediatek,mt8365-disp-gamma --=20 2.46.0 From nobody Sun Feb 8 14:34:29 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2422C2E265A; Mon, 20 Oct 2025 07:42:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 20 Oct 2025 15:42:26 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Mon, 20 Oct 2025 15:42:21 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Mon, 20 Oct 2025 15:42:20 +0800 From: Xiandong Wang To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu CC: , , , , , , , , Xiandong Wang Subject: [PATCH v1 06/13] dt-bindings: arm: mediatek: mmsys: add compatible for MT8189 Date: Mon, 20 Oct 2025 15:40:19 +0800 Message-ID: <20251020074211.8942-7-xiandong.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251020074211.8942-1-xiandong.wang@mediatek.com> References: <20251020074211.8942-1-xiandong.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In MT8189, a single HW pipeline was an independent mmsys, which included the OVL module, PQ module, and display interface module. Signed-off-by: Xiandong Wang Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.= yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 3f4262e93c78..f1889b9788ab 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -35,6 +35,7 @@ properties: - mediatek,mt8188-vdosys1 - mediatek,mt8188-vppsys0 - mediatek,mt8188-vppsys1 + - mediatek,mt8189-mmsys - mediatek,mt8192-mmsys - mediatek,mt8195-vdosys1 - mediatek,mt8195-vppsys0 --=20 2.46.0 From nobody Sun Feb 8 14:34:29 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E2662E5D32; Mon, 20 Oct 2025 07:42:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760946157; cv=none; b=d8tjw/Cbzj8SEFlBHe9vkCwn0PS8vgNdIFOzLRbKhZv5PNG6LYEnzBhHlAS93LND9VWIrVq27nhLV5WluP1B9tgBdl6JfCybqwJ7V4X0RTYj1DGj8xu2v0tr1TtAIwFfq8ETAgqCSX8KyOBxs+bpeAuhtnj+HeHl4XqiGUJXWhY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760946157; c=relaxed/simple; bh=ADpRJLxHOGjICQZ0RdbLQSD+gnoLezeKR5KhJKXDmuA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KB/21ZEEvMJbW7eyZpcykkRmF6QIOZR3qHsXzskmiA9uUj5g6TeyTLGt9/TpvFncSCMYfGfmPocBKeVRlepZlZkXCBnTCTrsFWAojwQjK4UrsNjOpoxDoyuC+fTTGUnIYDQJTIvQHlmWCsQiyEil5OgSVCfhGTN/xlpIQeS3re0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=YfHAk+SG; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="YfHAk+SG" X-UUID: 54247f6cad8811f0b33aeb1e7f16c2b6-20251020 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BRqSf4xFwqerRQJeKpftbFM7hfFFt/HgC1uk2U1hefo=; b=YfHAk+SGcvrVGD/0WZFtzNMJ33IAaCw0kW8MqB7dSd5oaftSjyroQmLuOFD1KOujr8yZ8fpPHD0mOZc5L6rACYJu7lLjvRLsUzTDl7IhsN6cxlH+Zk+pkrD4FL8c6Gz0lxiQTmXeaX7ZNl70+c1C2PDKrRkyXuETAmKg7S/LH5Y=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:ee9b7804-c678-4562-9975-0806c59ee473,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:a9d874c,CLOUDID:6c416686-2e17-44e4-a09c-1e463bf6bc47,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 54247f6cad8811f0b33aeb1e7f16c2b6-20251020 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 664503607; Mon, 20 Oct 2025 15:42:28 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Mon, 20 Oct 2025 15:42:22 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Mon, 20 Oct 2025 15:42:22 +0800 From: Xiandong Wang To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu CC: , , , , , , , , Xiandong Wang Subject: [PATCH v1 07/13] dt-bindings: soc: mediatek: add ovl yaml for MT8189 Date: Mon, 20 Oct 2025 15:40:20 +0800 Message-ID: <20251020074211.8942-8-xiandong.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251020074211.8942-1-xiandong.wang@mediatek.com> References: <20251020074211.8942-1-xiandong.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string to support ovl for MT8189. Signed-off-by: Xiandong Wang --- .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ov= l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.ya= ml index 4f110635afb6..578e90d0e3b9 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt2701-disp-ovl - mediatek,mt8173-disp-ovl - mediatek,mt8183-disp-ovl + - mediatek,mt8189-disp-ovl - mediatek,mt8192-disp-ovl - mediatek,mt8195-disp-ovl - mediatek,mt8195-mdp3-ovl @@ -44,6 +45,7 @@ properties: - const: mediatek,mt8192-disp-ovl - items: - const: mediatek,mt8188-disp-ovl + - const: mediatek,mt8189-disp-ovl - const: mediatek,mt8195-disp-ovl - items: - const: mediatek,mt8188-mdp3-ovl --=20 2.46.0 From nobody Sun Feb 8 14:34:29 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CE6D2E62AC; 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charset="utf-8" Add compatible string to support rdma for MT8189. Signed-off-by: Xiandong Wang --- .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rd= ma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.= yaml index 878f676b581f..4d29a1385104 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -44,6 +44,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-rdma + - mediatek,mt8189-disp-rdma - mediatek,mt8192-disp-rdma - mediatek,mt8365-disp-rdma - const: mediatek,mt8183-disp-rdma --=20 2.46.0 From nobody Sun Feb 8 14:34:29 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EAA72E7BBC; Mon, 20 Oct 2025 07:42:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760946160; cv=none; b=jaWPOU0ewKpUUavB/6ZxBgokfIoFTFyyNc9MMPTwqlVM7pwolW4wfjYUB2/SHHvE+jF5kZyjl39psd8T5+hTIFvFyTk+B+zFa6c07Vu9KQ9xYdY3ta5gjyf23znyBcUbi0/aCIyvkShhBIicr67IMNzY0edEwM9RGOwLXuka/T8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760946160; c=relaxed/simple; bh=YhveG6wgcstYwn2a7ypVlp3iMZ5P6vu/WUqfkV61RfY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mKzomJq5Y92skxToHG7gDaWfv3EB2yBtRCnmYwVWJh3ZCZoi0DkGJIOSK/kA0WtA0XcqFRYVtdTGz6MOFEZDasI18kXYrJj7Xs8tfmRMWxzq/6UTZ0g3vUAIdT/YGY4X1oXsbT9GeRwKPwEBRW69BhiAQYf9Vg8fQ4NbdPi+Crk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=aL9GMez+; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="aL9GMez+" X-UUID: 567105d8ad8811f0b33aeb1e7f16c2b6-20251020 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=XAx5KTymNAKE0YP7LKcg699MagckCl//FXk5u/2759o=; b=aL9GMez+ZMRrTsamCmt0kOzk2byoUm9WexA2sUdDUuJ8IQvGEyRqFUQI5WoGuVFhZBJyBHg7K35KAl9ClcSRfd7nnFO4Zv7kFLRi54tiS7oJmHPNF3fDtglWnimPlD6fCQ8WKR0JZ0VnHJntHMdDjkvlZxD/QKTykMPRYLk18tg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:8e9dfe87-d210-4b14-9e1c-454601c458d2,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:a9d874c,CLOUDID:8e416686-2e17-44e4-a09c-1e463bf6bc47,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 567105d8ad8811f0b33aeb1e7f16c2b6-20251020 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 745515297; Mon, 20 Oct 2025 15:42:32 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Mon, 20 Oct 2025 15:42:26 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Mon, 20 Oct 2025 15:42:26 +0800 From: Xiandong Wang To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu CC: , , , , , , , , Xiandong Wang Subject: [PATCH v1 09/13] dt-bindings: soc: mediatek: add mutex yaml for MT8189 Date: Mon, 20 Oct 2025 15:40:22 +0800 Message-ID: <20251020074211.8942-10-xiandong.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251020074211.8942-1-xiandong.wang@mediatek.com> References: <20251020074211.8942-1-xiandong.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string to support mutex for MT8189. Signed-off-by: Xiandong Wang Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.= yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index a10326a9683d..c0c565acdc64 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -85,6 +85,7 @@ allOf: - mediatek,mt8173-disp-mutex - mediatek,mt8186-disp-mutex - mediatek,mt8186-mdp3-mutex + - mediatek,mt8189-disp-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex then: --=20 2.46.0 From nobody Sun Feb 8 14:34:29 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F7DD2E8DF7; Mon, 20 Oct 2025 07:42:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760946163; cv=none; b=s3J+wcDB7+LMJ6zDD97doRvaPMPI2h+X31jqUmFUs4Okk7f+eoACbG90lOejf9UhYmi7hvUZIfmtLmf1W2RhNEyszLsF4qU8bNYYd2QQKR691VqniwPkABQrqXJh/P0o5kUJgExFQVQ9HUpiV5cp7shsBdslaFRcUnv/oSTAYKY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760946163; c=relaxed/simple; bh=VedNdTpKm5tRUC/+vBUImI7r+ZNXL5nzVWgqY+8DzGc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SVUkNr2GOIlfEsV2Xo+GCPjoRltArSIUt7jrCq5XrWFwB2Ndx5hVIRHDwOlDtMfIIgDF/HYKrvzAxw4CRDfPnvwF8Ntmzq9gZztAAZpxIp6kaWTe0w/Q1wdnji/2x8/tFgs8U05Lhsi/qUxje0wXxfoerOi2TuJ6sGVAj34ynO0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=Cd8C8esI; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Cd8C8esI" X-UUID: 5784821aad8811f0b33aeb1e7f16c2b6-20251020 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=8UN7sanGx2RMjFN9PAenKVDy3ihnS31FxWkQ7IZwMfg=; b=Cd8C8esIwuDL69NXhHqVvFlvTUgQltJgxDQio3Wq8Z/+bkzjBksIh9uAdfdkogkSq/DtPyroP1FdTh+ZyaTsu0Nv83Zl92LcJ8MZ3gZ9lWMvChN/sBsEGBYx9H+g4IEX4VaA+/vhymjXlnOrqiBWSEQPZp1AUzrsesPrLfHTiWs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:95b7c738-4721-4f88-b84f-530b94e9af32,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:a9d874c,CLOUDID:c09c3e51-c509-4cf3-8dc0-fcdaad49a6d3,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 5784821aad8811f0b33aeb1e7f16c2b6-20251020 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1952008899; Mon, 20 Oct 2025 15:42:34 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Mon, 20 Oct 2025 15:42:28 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Mon, 20 Oct 2025 15:42:27 +0800 From: Xiandong Wang To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu CC: , , , , , , , , Xiandong Wang Subject: [PATCH v1 10/13] dt-bindings: soc: mediatek: add dsi yaml for MT8189 Date: Mon, 20 Oct 2025 15:40:23 +0800 Message-ID: <20251020074211.8942-11-xiandong.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251020074211.8942-1-xiandong.wang@mediatek.com> References: <20251020074211.8942-1-xiandong.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string to support dsi for MT8189. Signed-off-by: Xiandong Wang --- .../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ds= i.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.ya= ml index 27ffbccc2a08..ae23f192e1e0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -36,6 +36,7 @@ properties: - const: mediatek,mt8173-dsi - items: - enum: + - mediatek,mt8189-dsi - mediatek,mt8195-dsi - mediatek,mt8365-dsi - const: mediatek,mt8183-dsi --=20 2.46.0 From nobody Sun Feb 8 14:34:29 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01DBC2E9735; Mon, 20 Oct 2025 07:42:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760946166; cv=none; b=PurWzkTO71p33kSc/xpI734B/hVrUIqD6sG6bwFxVfjipYeB2tLcVO47AqVo0mNQMD2968OM09jOReluCQ/TY4wOGBupuF2ZCl2NEoq76Jcg93PBqMsHT3AfLWapRwFxPfZP6T+nFMtsMnM6iyndPLYoTlovgMi+Ax5HmToFMyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760946166; c=relaxed/simple; bh=kXvgD49/oiZtkIDFu5jnSf40Y1LdECY61Trkg5w0BE0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=t6VM/BQWgjOttLlkuaSVvWypD08NJ8Ra/0gpqA+hyKNee4O8ASWmSinVKTm8facVI1PUl/soFyC7OWuqW1/9kkWdQHydoY5HLlRh3gRzmOe4PxWE1LSEioagVucpahQHpJlaOOGPDuM+VU8w0DY32IV2eSmJvSZPLFpRJw5fnrM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=eQ5Y/s4B; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="eQ5Y/s4B" X-UUID: 588f9082ad8811f0ae1e63ff8927bad3-20251020 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=PQCWLUlWiyxvQaMBcUsF+Z0zW93ZbqkmIBVjZvUSn+Y=; b=eQ5Y/s4Bv0t+zbgvbNN0mDT/De++uUMp891kdTsdYgOf9f3StQpW2v+XGTgreuet26hVkoISYkmSQRgcuW1m8nzTZZmPJIpwczl16M06z8MjH1YkKy8J/iBAoSbYc74xqyCCmF+JQK/7S7tOozuXEy5kgHqemNw1VPk3mZTJbzw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:41168890-3e05-47df-acee-1598940ff108,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:a9d874c,CLOUDID:aa309302-eaf8-4c8c-94de-0bc39887e077,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 588f9082ad8811f0ae1e63ff8927bad3-20251020 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 592775459; Mon, 20 Oct 2025 15:42:36 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Mon, 20 Oct 2025 15:42:30 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Mon, 20 Oct 2025 15:42:29 +0800 From: Xiandong Wang To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu CC: , , , , , , , , Xiandong Wang Subject: [PATCH v1 11/13] soc: mediatek: add mmsys support for MT8189 Date: Mon, 20 Oct 2025 15:40:24 +0800 Message-ID: <20251020074211.8942-12-xiandong.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251020074211.8942-1-xiandong.wang@mediatek.com> References: <20251020074211.8942-1-xiandong.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add driver data for MT8189 and add the routing table for each mmsys. Signed-off-by: Xiandong Wang --- drivers/soc/mediatek/mt8189-mmsys.h | 300 +++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 12 + include/linux/soc/mediatek/mtk-mmsys.h | 5 + 3 files changed, 317 insertions(+) create mode 100644 drivers/soc/mediatek/mt8189-mmsys.h diff --git a/drivers/soc/mediatek/mt8189-mmsys.h b/drivers/soc/mediatek/mt8= 189-mmsys.h new file mode 100644 index 000000000000..31378b6ee100 --- /dev/null +++ b/drivers/soc/mediatek/mt8189-mmsys.h @@ -0,0 +1,300 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 MediaTek Inc. + */ + +#ifndef __SOC_MEDIATEK_MT8189_MMSYS_H +#define __SOC_MEDIATEK_MT8189_MMSYS_H + +#include + +#define MT8189_MMSYS_SW0_RST_B 0x190 + +#define MT8189_MMSYS_GCE_EVENT_SEL 0x308 +#define MT8189_EVENT_GCE_EN (BIT(0) | BIT(1)) + +#define MT8189_DISP_OVL0_OUT0_MOUT_EN 0xc10 + #define MT8189_MOUT_DISP_OVL0_TO_DISP_RSZ0 BIT(0) + #define MT8189_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(1) + #define MT8189_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(2) + +#define MT8189_DISP_OVL1_OUT0_MOUT_EN 0xc14 + #define MT8189_MOUT_DISP_OVL1_TO_DISP_RSZ1 BIT(0) + #define MT8189_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(1) + #define MT8189_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(2) +#define MT8189_DISP_OVL_OUT0_MOUT_MASK 0x7 + +#define MT8189_OVL_PQ_OUT_CROSSBAR0_MOUT_EN 0xc74 + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_DISP_DSC_WRAP0_0 BIT(0) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_DISP_DSC_WRAP0_1 BIT(1) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_VPP_MERGE0_0 BIT(2) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_VPP_MERGE0_1 BIT(3) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_COMP_OUT_CROSSBAR4 BIT(4) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_COMP_OUT_CROSSBAR5 BIT(5) + +#define MT8189_OVL_PQ_OUT_CROSSBAR1_MOUT_EN 0xc78 + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_DISP_DSC_WRAP0_0 BIT(0) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_DISP_DSC_WRAP0_1 BIT(1) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_VPP_MERGE0_0 BIT(2) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_VPP_MERGE0_1 BIT(3) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_COMP_OUT_CROSSBAR4 BIT(4) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_COMP_OUT_CROSSBAR5 BIT(5) + +#define MT8189_OVL_PQ_OUT_CROSSBAR2_MOUT_EN 0xc7c + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_DISP_DSC_WRAP0_0 BIT(0) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_DISP_DSC_WRAP0_1 BIT(1) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_VPP_MERGE0_0 BIT(2) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_VPP_MERGE0_1 BIT(3) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_COMP_OUT_CROSSBAR4 BIT(4) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_COMP_OUT_CROSSBAR5 BIT(5) + +#define MT8189_OVL_PQ_OUT_CROSSBAR3_MOUT_EN 0xc80 + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_DISP_DSC_WRAP0_0 BIT(0) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_DISP_DSC_WRAP0_1 BIT(1) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_VPP_MERGE0_0 BIT(2) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_VPP_MERGE0_1 BIT(3) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_COMP_OUT_CROSSBAR4 BIT(4) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_COMP_OUT_CROSSBAR5 BIT(5) + +#define MT8189_OVL_PQ_OUT_CROSSBAR4_MOUT_EN 0xc84 + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_DISP_DSC_WRAP0_0 BIT(0) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_DISP_DSC_WRAP0_1 BIT(1) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_VPP_MERGE0_0 BIT(2) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_VPP_MERGE0_1 BIT(3) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_COMP_OUT_CROSSBAR4 BIT(4) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_COMP_OUT_CROSSBAR5 BIT(5) + +#define MT8189_OVL_PQ_OUT_CROSSBAR5_MOUT_EN 0xc88 + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_DISP_DSC_WRAP0_0 BIT(0) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_DISP_DSC_WRAP0_1 BIT(1) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_VPP_MERGE0_0 BIT(2) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_VPP_MERGE0_1 BIT(3) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_COMP_OUT_CROSSBAR4 BIT(4) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_COMP_OUT_CROSSBAR5 BIT(5) +#define MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MASK 0x3f + +#define MT8189_OVL_PQ_OUT_CROSSBAR0_SEL_IN 0xc8c + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_DITER0 (0) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_RDMA0_RSZ0_SOUT (1) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_OVL0_OUT0_MOUT (2) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_DITER1 (3) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_RDMA1_RSZ1_SOUT (4) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_OVL1_OUT0_MOUT (5) + +#define MT8189_OVL_PQ_OUT_CROSSBAR1_SEL_IN 0xc90 + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_DITER0 (0) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_RDMA0_RSZ0_SOUT (1) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_OVL0_OUT0_MOUT (2) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_DITER1 (3) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_RDMA1_RSZ1_SOUT (4) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_OVL1_OUT0_MOUT (5) + +#define MT8189_OVL_PQ_OUT_CROSSBAR2_SEL_IN 0xc94 + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_DITER0 (0) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_RDMA0_RSZ0_SOUT (1) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_OVL0_OUT0_MOUT (2) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_DITER1 (3) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_RDMA1_RSZ1_SOUT (4) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_OVL1_OUT0_MOUT (5) + +#define MT8189_OVL_PQ_OUT_CROSSBAR3_SEL_IN 0xc98 + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_DITER0 (0) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_RDMA0_RSZ0_SOUT (1) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_FROM_DISP_OVL0_OUT0_MOUT = (2) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_DITER1 (3) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_RDMA1_RSZ1_SOUT (4) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_OVL1_OUT0_MOUT (5) + +#define MT8189_OVL_PQ_OUT_CROSSBAR4_SEL_IN 0xc9c + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_DITER0 (0) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_RDMA0_RSZ0_SOUT (1) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_OVL0_OUT0_MOUT (2) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_DITER1 (3) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_RDMA1_RSZ1_SOUT (4) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_OVL1_OUT0_MOUT (5) + +#define MT8189_OVL_PQ_OUT_CROSSBAR5_SEL_IN 0xca0 + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_DITER0 (0) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_RDMA0_RSZ0_SOUT (1) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_OVL0_OUT0_MOUT (2) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_DITER1 (3) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_RDMA1_RSZ1_SOUT (4) + #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_OVL1_OUT0_MOUT (5) + +#define MT8189_COMP_OUT_CROSSBAR0_MOUT_EN 0xd70 + #define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_DSI0 BIT(0) + #define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_DVO0 BIT(1) + #define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_DVO1 BIT(2) + #define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DPI0 BIT(3) + #define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_WDMA0 BIT(4) + #define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_WDMA1 BIT(5) + +#define MT8189_COMP_OUT_CROSSBAR1_MOUT_EN 0xd74 + #define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_DSI0 BIT(0) + #define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_DVO0 BIT(1) + #define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_DVO1 BIT(2) + #define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DPI0 BIT(3) + #define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_WDMA0 BIT(4) + #define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_WDMA1 BIT(5) + +#define MT8189_COMP_OUT_CROSSBAR2_MOUT_EN 0xd78 + #define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_DSI0 BIT(0) + #define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_DVO0 BIT(1) + #define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_DVO1 BIT(2) + #define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DPI0 BIT(3) + #define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_WDMA0 BIT(4) + #define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_WDMA1 BIT(5) + +#define MT8189_COMP_OUT_CROSSBAR3_MOUT_EN 0xd7c + #define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_DSI0 BIT(0) + #define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_DVO0 BIT(1) + #define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_DVO1 BIT(2) + #define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DPI0 BIT(3) + #define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_WDMA0 BIT(4) + #define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_WDMA1 BIT(5) + +#define MT8189_COMP_OUT_CROSSBAR4_MOUT_EN 0xd80 + #define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DSI0 BIT(0) + #define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DVO0 BIT(1) + #define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DVO1 BIT(2) + #define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DPI0 BIT(3) + #define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_WDMA0 BIT(4) + #define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_WDMA1 BIT(5) + +#define MT8189_COMP_OUT_CROSSBAR5_MOUT_EN 0xd84 + #define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DSI0 BIT(0) + #define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DVO0 BIT(1) + #define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DVO1 BIT(2) + #define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DPI0 BIT(3) + #define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_WDMA0 BIT(4) + #define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_WDMA1 BIT(5) + + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_DISP_DSC_WRAP0_0 BIT(0) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_DISP_DSC_WRAP0_1 BIT(1) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_VPP_MERGE0_0 BIT(2) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_VPP_MERGE0_1 BIT(3) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_COMP_OUT_CROSSBAR4 BIT(4) + #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_COMP_OUT_CROSSBAR5 BIT(5) +#define MT8189_COMP_OUT_CROSSBAR_MOUT_MASK 0x3f + +#define MT8189_COMP_OUT_CROSSBAR0_SEL_IN 0xd88 + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_DISP_DSC_WRAP0_0 (0) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_DISP_DSC_WRAP0_1 (1) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_VPP_MERGE0_0 (2) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_VPP_MERGE0_1 (3) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_OVL_PQ_OUT_CROSSBAR4 (4) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_OVL_PQ_OUT_CROSSBAR5 (5) + +#define MT8189_COMP_OUT_CROSSBAR1_SEL_IN 0xd8c + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_DISP_DSC_WRAP0_0 (0) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_DISP_DSC_WRAP0_1 (1) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_VPP_MERGE0_0 (2) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_VPP_MERGE0_1 (3) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_OVL_PQ_OUT_CROSSBAR4 (4) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_OVL_PQ_OUT_CROSSBAR5 (5) + +#define MT8189_COMP_OUT_CROSSBAR2_SEL_IN 0xd90 + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_DISP_DSC_WRAP0_0 (0) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_DISP_DSC_WRAP0_1 (1) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_VPP_MERGE0_0 (2) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_VPP_MERGE0_1 (3) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_OVL_PQ_OUT_CROSSBAR4 (4) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_OVL_PQ_OUT_CROSSBAR5 (5) + +#define MT8189_COMP_OUT_CROSSBAR3_SEL_IN 0xd94 + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_DISP_DSC_WRAP0_0 (0) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_DISP_DSC_WRAP0_1 (1) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_VPP_MERGE0_0 (2) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_VPP_MERGE0_1 (3) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_OVL_PQ_OUT_CROSSBAR4 (4) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_OVL_PQ_OUT_CROSSBAR5 (5) + +#define MT8189_COMP_OUT_CROSSBAR4_SEL_IN 0xd98 + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_DISP_DSC_WRAP0_0 (0) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_DISP_DSC_WRAP0_1 (1) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_VPP_MERGE0_0 (2) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_VPP_MERGE0_1 (3) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_OVL_PQ_OUT_CROSSBAR4 (4) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_OVL_PQ_OUT_CROSSBAR5 (5) + +#define MT8189_COMP_OUT_CROSSBAR5_SEL_IN 0xd9c + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_DISP_DSC_WRAP0_0 (0) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_DISP_DSC_WRAP0_1 (1) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_VPP_MERGE0_0 (2) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_VPP_MERGE0_1 (3) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_OVL_PQ_OUT_CROSSBAR4 (4) + #define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_OVL_PQ_OUT_CROSSBAR5 (5) + +#define MT8189_DISP_RDMA0_RSZ0_SOUT_SEL 0xe00 + #define MT8189_SOUT_DISP_RDMA0_RSZ0_TO_OVL_PQ_OUT_CROSSBAR1 (0) + #define MT8189_SOUT_DISP_RDMA0_RSZ0_TO_DISP_COLOR0 (1) + +#define MT8189_DISP_RDMA0_SEL_IN 0xe04 + #define MT8189_SEL_IN_DISP_RDMA0_FROM_DISP_RSZ0_MOUT (0) + #define MT8189_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0_OUT0_MOUT (1) +#define MT8189_DISP_RDMA_SEL_IN_MASK 0x1 + +#define MT8189_DISP_RDMA1_RSZ1_SOUT_SEL 0xe08 + #define MT8189_SOUT_DISP_RDMA1_RSZ1_TO_OVL_PQ_OUT_CROSSBAR4 (0) + #define MT8189_SOUT_DISP_RDMA1_RSZ1_TO_DISP_COLOR1 (1) + +#define MT8189_DISP_RDMA1_SEL_IN 0xe0c + #define MT8189_SEL_IN_DISP_RDMA1_FROM_DISP_RSZ1_MOUT (0) + #define MT8189_SEL_IN_DISP_RDMA1_FROM_DISP_OVL1_OUT0_MOUT (1) + +#define MT8189_DISP_OVL0_BGCLR_MOUT_EN 0xe24 + #define MT8189_MOUT_OVL_TO_BLENDOUT BIT(0) + #define MT8189_MOUT_OVL_TO_BG BIT(1) + +#define MT8189_DISP_OVL1_BGCLR_MOUT_EN 0xe28 +#define MT8189_DISP_OVL_BGCLR_MOUT_MASK 0x3 + +static const struct mtk_mmsys_routes mmsys_mt8189_routing_table[] =3D { + /* main path */ + MMSYS_ROUTE(DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8189_DISP_OVL0_BGCLR_MOUT_EN, MT8189_DISP_OVL_BGCLR_MOUT_MASK, + MT8189_MOUT_OVL_TO_BLENDOUT), + MMSYS_ROUTE(DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8189_DISP_OVL0_OUT0_MOUT_EN, MT8189_DISP_OVL_OUT0_MOUT_MASK, + MT8189_MOUT_DISP_OVL0_TO_DISP_RDMA0), + MMSYS_ROUTE(DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8189_DISP_RDMA0_SEL_IN, MT8189_DISP_RDMA_SEL_IN_MASK, + MT8189_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0_OUT0_MOUT), + MMSYS_ROUTE(DDP_COMPONENT_RDMA0, DDP_COMPONENT_COMP0_OUT_CB4, + MT8189_DISP_RDMA0_RSZ0_SOUT_SEL, MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MAS= K, + MT8189_SOUT_DISP_RDMA0_RSZ0_TO_OVL_PQ_OUT_CROSSBAR1), + MMSYS_ROUTE(DDP_COMPONENT_RDMA0, DDP_COMPONENT_COMP0_OUT_CB4, + MT8189_OVL_PQ_OUT_CROSSBAR1_MOUT_EN, MT8189_OVL_PQ_OUT_CROSSBAR_MOUT= _MASK, + MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_COMP_OUT_CROSSBAR4), + MMSYS_ROUTE(DDP_COMPONENT_COMP0_OUT_CB4, DDP_COMPONENT_DVO0, + MT8189_COMP_OUT_CROSSBAR4_MOUT_EN, MT8189_COMP_OUT_CROSSBAR_MOUT_MAS= K, + MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DVO0), + /* ext path */ + MMSYS_ROUTE(DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, + MT8189_DISP_OVL1_BGCLR_MOUT_EN, MT8189_DISP_OVL_BGCLR_MOUT_MASK, + MT8189_MOUT_OVL_TO_BLENDOUT), + MMSYS_ROUTE(DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, + MT8189_DISP_OVL1_OUT0_MOUT_EN, MT8189_DISP_OVL_OUT0_MOUT_MASK, + MT8189_MOUT_DISP_OVL1_TO_DISP_RDMA1), + MMSYS_ROUTE(DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, + MT8189_DISP_RDMA1_SEL_IN, MT8189_DISP_RDMA_SEL_IN_MASK, + MT8189_SEL_IN_DISP_RDMA1_FROM_DISP_OVL1_OUT0_MOUT), + MMSYS_ROUTE(DDP_COMPONENT_RDMA1, DDP_COMPONENT_COMP0_OUT_CB5, + MT8189_DISP_RDMA1_RSZ1_SOUT_SEL, MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MAS= K, + MT8189_SOUT_DISP_RDMA1_RSZ1_TO_OVL_PQ_OUT_CROSSBAR4), + MMSYS_ROUTE(DDP_COMPONENT_RDMA1, DDP_COMPONENT_COMP0_OUT_CB5, + MT8189_OVL_PQ_OUT_CROSSBAR4_MOUT_EN, MT8189_OVL_PQ_OUT_CROSSBAR_MOUT= _MASK, + MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_COMP_OUT_CROSSBAR5), + MMSYS_ROUTE(DDP_COMPONENT_COMP0_OUT_CB5, DDP_COMPONENT_DVO1, + MT8189_COMP_OUT_CROSSBAR5_MOUT_EN, MT8189_COMP_OUT_CROSSBAR_MOUT_MAS= K, + MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DVO1), + MMSYS_ROUTE(DDP_COMPONENT_COMP0_OUT_CB5, DDP_COMPONENT_DSI0, + MT8189_COMP_OUT_CROSSBAR5_MOUT_EN, MT8189_COMP_OUT_CROSSBAR_MOUT_MAS= K, + MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DSI0), +}; + +static const struct mtk_mmsys_default mmsys_mt8189_disp0_default_table[] = =3D { + {MT8189_MMSYS_GCE_EVENT_SEL, MT8189_EVENT_GCE_EN, GENMASK(1, 0)}, +}; + +#endif /* __SOC_MEDIATEK_MT8189_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index 3b490b993549..da5de4061007 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -22,6 +22,7 @@ #include "mt8183-mmsys.h" #include "mt8186-mmsys.h" #include "mt8188-mmsys.h" +#include "mt8189-mmsys.h" #include "mt8192-mmsys.h" #include "mt8195-mmsys.h" #include "mt8196-mmsys.h" @@ -116,6 +117,16 @@ static const struct mtk_mmsys_driver_data mt8188_vppsy= s1_driver_data =3D { .is_vppsys =3D true, }; =20 +static const struct mtk_mmsys_driver_data mt8189_mmsys_driver_data =3D { + .clk_driver =3D "clk-mt8189-mmsys", + .routes =3D mmsys_mt8189_routing_table, + .num_routes =3D ARRAY_SIZE(mmsys_mt8189_routing_table), + .def_config =3D mmsys_mt8189_disp0_default_table, + .num_def_config =3D ARRAY_SIZE(mmsys_mt8189_disp0_default_table), + .sw0_rst_offset =3D MT8189_MMSYS_SW0_RST_B, + .num_resets =3D 32, +}; + static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { .clk_driver =3D "clk-mt8192-mm", .routes =3D mmsys_mt8192_routing_table, @@ -668,6 +679,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = =3D { { .compatible =3D "mediatek,mt8188-vdosys1", .data =3D &mt8188_vdosys1_dr= iver_data }, { .compatible =3D "mediatek,mt8188-vppsys0", .data =3D &mt8188_vppsys0_dr= iver_data }, { .compatible =3D "mediatek,mt8188-vppsys1", .data =3D &mt8188_vppsys1_dr= iver_data }, + { .compatible =3D "mediatek,mt8189-mmsys", .data =3D &mt8189_mmsys_driver= _data }, { .compatible =3D "mediatek,mt8192-mmsys", .data =3D &mt8192_mmsys_driver= _data }, /* "mediatek,mt8195-mmsys" compatible is deprecated */ { .compatible =3D "mediatek,mt8195-mmsys", .data =3D &mt8195_vdosys0_driv= er_data }, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index 4a0b10567581..7d63b9f0899f 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -49,6 +49,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DSI2, DDP_COMPONENT_DSI3, DDP_COMPONENT_DVO0, + DDP_COMPONENT_DVO1, DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_GAMMA, DDP_COMPONENT_MDP_RDMA0, @@ -133,6 +134,10 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_UFOE, DDP_COMPONENT_WDMA0, DDP_COMPONENT_WDMA1, + DDP_COMPONENT_RSZ0, + DDP_COMPONENT_RSZ1, + DDP_COMPONENT_COMP0_OUT_CB4, + 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Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 968935925; Mon, 20 Oct 2025 15:42:37 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Mon, 20 Oct 2025 15:42:31 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Mon, 20 Oct 2025 15:42:31 +0800 From: Xiandong Wang To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu CC: , , , , , , , , Xiandong Wang Subject: [PATCH v1 12/13] drm/mediatek: Add support for mt8189 mmsys driver probe Date: Mon, 20 Oct 2025 15:40:25 +0800 Message-ID: <20251020074211.8942-13-xiandong.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251020074211.8942-1-xiandong.wang@mediatek.com> References: <20251020074211.8942-1-xiandong.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mmsys probe for mt8189 Signed-off-by: Xiandong Wang --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 40 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.h | 2 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 8 +++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 39 +++++++++++++++++++++++ 5 files changed, 91 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index ac6620e10262..b83ecd5404c6 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -498,6 +498,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_UFOE] =3D { MTK_DISP_UFOE, 0, &ddp_ufoe }, [DDP_COMPONENT_WDMA0] =3D { MTK_DISP_WDMA, 0, NULL }, [DDP_COMPONENT_WDMA1] =3D { MTK_DISP_WDMA, 1, NULL }, + [DDP_COMPONENT_COMP0_OUT_CB4] =3D { MTK_DISP_VIRTUAL, -1, NULL }, + [DDP_COMPONENT_COMP0_OUT_CB5] =3D { MTK_DISP_VIRTUAL, -1, NULL }, }; =20 static bool mtk_ddp_comp_find(struct device *dev, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 7cd3978beb98..f1fa1f1c3ff0 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -110,6 +110,32 @@ const u32 mt8173_ovl_formats[] =3D { =20 const size_t mt8173_ovl_formats_len =3D ARRAY_SIZE(mt8173_ovl_formats); =20 +const u32 mt8189_ovl_formats[] =3D { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_XRGB2101010, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRX1010102, + DRM_FORMAT_BGRA1010102, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_RGBX8888, + DRM_FORMAT_RGBA8888, + DRM_FORMAT_RGBX1010102, + DRM_FORMAT_RGBA1010102, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + +const size_t mt8189_ovl_formats_len =3D ARRAY_SIZE(mt8189_ovl_formats); + const u32 mt8195_ovl_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, @@ -779,6 +805,18 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_dr= iver_data =3D { .num_formats =3D mt8173_ovl_formats_len, }; =20 +static const struct mtk_disp_ovl_data mt8189_ovl_driver_data =3D { + .addr =3D DISP_REG_OVL_ADDR_MT8173, + .gmc_bits =3D 10, + .layer_nr =3D 4, + .fmt_rgb565_is_0 =3D true, + .smi_id_en =3D true, + .supports_afbc =3D true, + .formats =3D mt8189_formats, + .num_formats =3D ARRAY_SIZE(mt8189_formats), + .supports_clrfmt_ext =3D true, +}; + static const struct mtk_disp_ovl_data mt8192_ovl_driver_data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, @@ -823,6 +861,8 @@ static const struct of_device_id mtk_disp_ovl_driver_dt= _match[] =3D { .data =3D &mt8183_ovl_driver_data}, { .compatible =3D "mediatek,mt8183-disp-ovl-2l", .data =3D &mt8183_ovl_2l_driver_data}, + { .compatible =3D "mediatek,mt8189-disp-ovl", + .data =3D &mt8189_ovl_driver_data}, { .compatible =3D "mediatek,mt8192-disp-ovl", .data =3D &mt8192_ovl_driver_data}, { .compatible =3D "mediatek,mt8192-disp-ovl-2l", diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.h index 431567538eb5..675254e786d4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h @@ -16,6 +16,8 @@ =20 extern const u32 mt8173_ovl_formats[]; extern const size_t mt8173_ovl_formats_len; +extern const u32 mt8189_ovl_formats[]; +extern const size_t mt8189_ovl_formats_len; extern const u32 mt8195_ovl_formats[]; extern const size_t mt8195_ovl_formats_len; =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/med= iatek/mtk_disp_rdma.c index c9d41d75e7f2..593d9d144218 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -394,6 +394,12 @@ static const struct mtk_disp_rdma_data mt8183_rdma_dri= ver_data =3D { .num_formats =3D ARRAY_SIZE(mt8173_formats), }; =20 +static const struct mtk_disp_rdma_data mt8189_rdma_driver_data =3D { + .fifo_size =3D 1920, + .formats =3D mt8173_formats, + .num_formats =3D ARRAY_SIZE(mt8173_formats), +}; + static const struct mtk_disp_rdma_data mt8195_rdma_driver_data =3D { .fifo_size =3D 1920, .formats =3D mt8173_formats, @@ -407,6 +413,8 @@ static const struct of_device_id mtk_disp_rdma_driver_d= t_match[] =3D { .data =3D &mt8173_rdma_driver_data}, { .compatible =3D "mediatek,mt8183-disp-rdma", .data =3D &mt8183_rdma_driver_data}, + { .compatible =3D "mediatek,mt8189-disp-rdma", + .data =3D &mt8189_rdma_driver_data}, { .compatible =3D "mediatek,mt8195-disp-rdma", .data =3D &mt8195_rdma_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 4c19cffafd0f..9e6d949e5d17 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -187,11 +187,27 @@ static const unsigned int mt8188_mtk_ddp_main[] =3D { DDP_COMPONENT_DITHER0, }; =20 +static const unsigned int mt8189_mtk_ddp_main[] =3D { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COMP0_OUT_CB4, +}; + +static const unsigned int mt8189_mtk_ddp_ext[] =3D { + DDP_COMPONENT_OVL1, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_COMP0_OUT_CB5, +}; + static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] =3D { {0, DDP_COMPONENT_DP_INTF0}, {0, DDP_COMPONENT_DSI0}, }; =20 +static const struct mtk_drm_route mt8189_mtk_ddp_ext_routes[] =3D { + {1, DDP_COMPONENT_DSI0}, +}; + static const struct mtk_drm_route mt8196_mtk_ddp_routes[] =3D { {2, DDP_COMPONENT_DSI0}, }; @@ -347,6 +363,19 @@ static const struct mtk_mmsys_driver_data mt8188_vdosy= s0_driver_data =3D { .min_height =3D 1, }; =20 +static const struct mtk_mmsys_driver_data mt8189_mmsys_driver_data =3D { + .main_path =3D mt8189_mtk_ddp_main, + .main_len =3D ARRAY_SIZE(mt8189_mtk_ddp_main), + .mmsys_dev_num =3D 1, + .ext_path =3D mt8189_mtk_ddp_ext, + .ext_len =3D ARRAY_SIZE(mt8189_mtk_ddp_ext), + .conn_routes =3D mt8189_mtk_ddp_ext_routes, + .num_conn_routes =3D ARRAY_SIZE(mt8189_mtk_ddp_ext_routes), + .max_width =3D 8191, + .min_width =3D 1, + .min_height =3D 1, +}; + static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { .main_path =3D mt8192_mtk_ddp_main, .main_len =3D ARRAY_SIZE(mt8192_mtk_ddp_main), @@ -454,6 +483,8 @@ static const struct of_device_id mtk_drm_of_ids[] =3D { .data =3D &mt8188_vdosys0_driver_data}, { .compatible =3D "mediatek,mt8188-vdosys1", .data =3D &mt8195_vdosys1_driver_data}, + { .compatible =3D "mediatek,mt8189-mmsys", + .data =3D &mt8189_mmsys_driver_data}, { .compatible =3D "mediatek,mt8192-mmsys", .data =3D &mt8192_mmsys_driver_data}, { .compatible =3D "mediatek,mt8195-mmsys", @@ -883,6 +914,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DISP_MUTEX }, { .compatible =3D "mediatek,mt8188-disp-mutex", .data =3D (void *)MTK_DISP_MUTEX }, + { .compatible =3D "mediatek,mt8189-disp-mutex", + .data =3D (void *)MTK_DISP_MUTEX}, { .compatible =3D "mediatek,mt8192-disp-mutex", .data =3D (void *)MTK_DISP_MUTEX }, { .compatible =3D "mediatek,mt8195-disp-mutex", @@ -899,6 +932,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DISP_OVL }, { .compatible =3D "mediatek,mt8183-disp-ovl", .data =3D (void *)MTK_DISP_OVL }, + { .compatible =3D "mediatek,mt8189-disp-ovl", + .data =3D (void *)MTK_DISP_OVL}, { .compatible =3D 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id 1237109764; Mon, 20 Oct 2025 15:42:38 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Mon, 20 Oct 2025 15:42:33 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Mon, 20 Oct 2025 15:42:32 +0800 From: Xiandong Wang To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu CC: , , , , , , , , Xiandong Wang Subject: [PATCH v1 13/13] soc: mediatek: mutex: add mutex support for MT8189 Date: Mon, 20 Oct 2025 15:40:26 +0800 Message-ID: <20251020074211.8942-14-xiandong.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251020074211.8942-1-xiandong.wang@mediatek.com> References: <20251020074211.8942-1-xiandong.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add mutex support for the main and external displays in MT8189: - Introduce a new DVO1 output component for the new mutex settings of MT8189. - Add a need_sof_mof flag to configure both SOF and MOD settings for the output component. Signed-off-by: Xiandong Wang Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-mutex.c | 88 ++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mu= tex.c index c48983d8a6cd..743c4b93a39e 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -177,6 +177,48 @@ #define MT8188_MUTEX_MOD_DISP1_DPI1 38 #define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39 =20 +#define MT8189_DISP_MUTEX0_MOD0 0x30 +#define MT8189_DISP_MUTEX0_MOD1 0x34 +#define MT8189_DISP_MUTEX0_SOF 0x2C +#define MT8189_MUTEX_MOD_DISP_OVL0 0 +#define MT8189_MUTEX_MOD_DISP_OVL1 1 +#define MT8189_MUTEX_MOD_DISP_RSZ0 2 +#define MT8189_MUTEX_MOD_DISP_RSZ1 3 +#define MT8189_MUTEX_MOD_DISP_RDMA0 4 +#define MT8189_MUTEX_MOD_DISP_RDMA1 5 +#define MT8189_MUTEX_MOD_DISP_COLOR0 6 +#define MT8189_MUTEX_MOD_DISP_COLOR1 4 +#define MT8189_MUTEX_MOD_DISP_CCORR0 8 +#define MT8189_MUTEX_MOD_DISP_CCORR1 9 +#define MT8189_MUTEX_MOD_DISP_CCORR2 10 +#define MT8189_MUTEX_MOD_DISP_CCORR3 11 +#define MT8189_MUTEX_MOD_DISP_AAL0 12 +#define MT8189_MUTEX_MOD_DISP_AAL1 13 +#define MT8189_MUTEX_MOD_DISP_GAMMA0 14 +#define MT8189_MUTEX_MOD_DISP_GAMMA1 15 +#define MT8189_MUTEX_MOD_DISP_DITHER0 16 +#define MT8189_MUTEX_MOD_DISP_DITHER1 17 +#define MT8189_MUTEX_MOD_DISP_VPP_MERGE0 18 +#define MT8189_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 19 +#define MT8189_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 20 +#define MT8189_MUTEX_MOD_DISP_DVO0 21 +#define MT8189_MUTEX_MOD_DISP_DSI0 22 +#define MT8189_MUTEX_MOD_DISP_DVO1 23 +#define MT8189_MUTEX_MOD_DISP_DPI0 24 +#define MT8189_MUTEX_MOD_DISP_WDMA0 25 +#define MT8189_MUTEX_MOD_DISP_WDMA1 26 +#define MT8189_MUTEX_MOD_DISP_PWM0 27 +#define MT8189_MUTEX_MOD_DISP_PWM1 28 +#define MT8189_MUTEX_MOD_ALL 0xff + +#define MT8189_MUTEX_SOF_SINGLE_MODE 0 +#define MT8189_MUTEX_SOF_DSI0 1 +#define MT8189_MUTEX_EOF_DSI0 (MT8189_MUTEX_SOF_DSI0 << 7) +#define MT8189_MUTEX_SOF_DVO 5 +#define MT8189_MUTEX_EOF_DVO (MT8189_MUTEX_SOF_DVO << 7) +#define MT8189_MUTEX_SOF_DPTX 6 +#define MT8189_MUTEX_EOF_DPTX (MT8189_MUTEX_SOF_DPTX << 7) + #define MT8195_MUTEX_MOD_DISP_OVL0 0 #define MT8195_MUTEX_MOD_DISP_WDMA0 1 #define MT8195_MUTEX_MOD_DISP_RDMA0 2 @@ -554,6 +596,34 @@ static const u8 mt8188_mdp_mutex_table_mod[MUTEX_MOD_I= DX_MAX] =3D { [MUTEX_MOD_IDX_MDP_WROT3] =3D MT8195_MUTEX_MOD_MDP_WROT3, }; =20 +static const unsigned int mt8189_mutex_mod[DDP_COMPONENT_ID_MAX] =3D { + [DDP_COMPONENT_OVL0] =3D MT8189_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL1] =3D MT8189_MUTEX_MOD_DISP_OVL1, + [DDP_COMPONENT_RSZ0] =3D MT8189_MUTEX_MOD_DISP_RSZ0, + [DDP_COMPONENT_RSZ1] =3D MT8189_MUTEX_MOD_DISP_RSZ1, + [DDP_COMPONENT_RDMA0] =3D MT8189_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] =3D MT8189_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_COLOR0] =3D MT8189_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_COLOR1] =3D MT8189_MUTEX_MOD_DISP_COLOR1, + [DDP_COMPONENT_CCORR0] =3D MT8189_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_CCORR1] =3D MT8189_MUTEX_MOD_DISP_CCORR1, + [DDP_COMPONENT_AAL0] =3D MT8189_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_AAL1] =3D MT8189_MUTEX_MOD_DISP_AAL1, + [DDP_COMPONENT_GAMMA] =3D MT8189_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_DITHER0] =3D MT8189_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_DITHER1] =3D MT8189_MUTEX_MOD_DISP_DITHER1, + [DDP_COMPONENT_MERGE0] =3D MT8189_MUTEX_MOD_DISP_VPP_MERGE0, + [DDP_COMPONENT_DSC0] =3D MT8189_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, + [DDP_COMPONENT_DVO0] =3D MT8189_MUTEX_MOD_DISP_DVO0, + [DDP_COMPONENT_DVO1] =3D MT8189_MUTEX_MOD_DISP_DVO1, + [DDP_COMPONENT_DSI0] =3D MT8189_MUTEX_MOD_DISP_DSI0, + [DDP_COMPONENT_WDMA0] =3D MT8189_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_PWM0] =3D MT8189_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_COMP0_OUT_CB4] =3D MT8189_MUTEX_MOD_ALL, + [DDP_COMPONENT_COMP0_OUT_CB5] =3D MT8189_MUTEX_MOD_ALL, + [MT8189_MUTEX_MOD_DISP_PWM1] =3D MT8189_MUTEX_MOD_DISP_PWM1, +}; + static const u8 mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] =3D { [DDP_COMPONENT_AAL0] =3D MT8192_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] =3D MT8192_MUTEX_MOD_DISP_CCORR0, @@ -718,6 +788,14 @@ static const u16 mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = =3D { MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1, }; =20 +static const unsigned int mt8189_mutex_sof[DDP_MUTEX_SOF_MAX] =3D { + [MUTEX_SOF_SINGLE_MODE] =3D MT8189_MUTEX_SOF_SINGLE_MODE, + [MUTEX_SOF_DSI0] =3D + MT8189_MUTEX_SOF_DSI0 | MT8189_MUTEX_EOF_DSI0, + [MUTEX_SOF_DP_INTF0] =3D + MT8189_MUTEX_SOF_DPTX | MT8189_MUTEX_EOF_DPTX, +}; + static const u16 mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] =3D { [MUTEX_SOF_SINGLE_MODE] =3D MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] =3D MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0, @@ -812,6 +890,14 @@ static const struct mtk_mutex_data mt8188_vpp_mutex_dr= iver_data =3D { .mutex_table_mod =3D mt8188_mdp_mutex_table_mod, }; =20 +static const struct mtk_mutex_data mt8189_mutex_driver_data =3D { + .mutex_mod =3D mt8189_mutex_mod, + .mutex_sof =3D mt8189_mutex_sof, + .mutex_mod_reg =3D MT8189_DISP_MUTEX0_MOD0, + .mutex_sof_reg =3D MT8189_DISP_MUTEX0_SOF, + .need_sof_mod =3D true, +}; + static const struct mtk_mutex_data mt8192_mutex_driver_data =3D { .mutex_mod =3D mt8192_mutex_mod, .mutex_sof =3D mt8183_mutex_sof, @@ -903,6 +989,7 @@ static int mtk_mutex_get_output_comp_sof(enum mtk_ddp_c= omp_id id) case DDP_COMPONENT_DPI1: return MUTEX_SOF_DPI1; case DDP_COMPONENT_DP_INTF0: + case DDP_COMPONENT_DVO1: return MUTEX_SOF_DP_INTF0; case DDP_COMPONENT_DP_INTF1: return MUTEX_SOF_DP_INTF1; @@ -1182,6 +1269,7 @@ static const struct of_device_id mutex_driver_dt_matc= h[] =3D { { .compatible =3D "mediatek,mt8186-mdp3-mutex", .data =3D &mt8186_mdp_mut= ex_driver_data }, { .compatible =3D "mediatek,mt8188-disp-mutex", .data =3D &mt8188_mutex_d= river_data }, { .compatible =3D "mediatek,mt8188-vpp-mutex", .data =3D &mt8188_vpp_mut= ex_driver_data }, + { .compatible =3D "mediatek,mt8189-disp-mutex", .data =3D &mt8189_mutex_d= river_data }, { .compatible =3D "mediatek,mt8192-disp-mutex", .data =3D &mt8192_mutex_d= river_data }, { .compatible =3D "mediatek,mt8195-disp-mutex", .data =3D &mt8195_mutex_d= river_data }, { .compatible =3D "mediatek,mt8195-vpp-mutex", .data =3D &mt8195_vpp_mut= ex_driver_data }, --=20 2.46.0