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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2671210dd; Mon, 20 Oct 2025 10:37:31 +0800 (GMT+08:00) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, sugar.zhang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com Subject: [PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll Date: Mon, 20 Oct 2025 10:37:23 +0800 Message-Id: <20251020023724.2723372-5-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251020023724.2723372-1-zhangqing@rock-chips.com> References: <20251020023724.2723372-1-zhangqing@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a99ff7aa5a703a3kunmd1f16c94462e86 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkkdSlZNS0pCTkoaGU1PQk1WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=fnCGE3AvCqy+lAqvO5kkUP36ClWsBOdSlTNhK47/dPSvgalGNcB6C1bTZVnxUR7/sygmJP7NfYQmvbFNl9eKJpTETCCBx0CQpV0OyVTHErWzYUfSkJ4nHCQS5nCXnXpEoxp1c3jkthWTFzqNXErAa0rSOfSnBGPxi1v1oH9wB8A=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=jaDds7wpnfMN/ZjknQjwA9mcNKD9y11S1VST/bKKkz0=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add pvtpll documentation for rockchip. Signed-off-by: Elaine Zhang --- .../bindings/clock/rockchip,clk-pvtpll.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-pv= tpll.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.ya= ml b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml new file mode 100644 index 000000000000..8be34bcde7b0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,clk-pvtpll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Pvtpll + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +properties: + compatible: + items: + - enum: + - rockchip,rv1103b-core-pvtpll + - rockchip,rv1103b-enc-pvtpll + - rockchip,rv1103b-isp-pvtpll + - rockchip,rv1103b-npu-pvtpll + - rockchip,rv1126b-core-pvtpll + - rockchip,rv1126b-isp-pvtpll + - rockchip,rv1126b-enc-pvtpll + - rockchip,rv1126b-aisp-pvtpll + - rockchip,rv1126b-npu-pvtpll + - rockchip,rk3506-core-pvtpll + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + rockchip,cru: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the main Clock and Reset Unit (CRU) controller. + Required for PVTPLLs that need to interact with the main CRU + for clock management operations. + +required: + - "#clock-cells" + - compatible + - reg + - clock-output-names + +additionalProperties: false + +examples: + - | + pvtpll_core: pvtpll-core@20480000 { + compatible =3D "rockchip,rv1126b-core-pvtpll", "syscon"; + reg =3D <0x20480000 0x100>; + #clock-cells =3D <0>; + clock-output-names =3D "clk_core_pvtpll"; + }; + + - | + pvtpll_isp: pvtpll-isp@21c60000 { + compatible =3D "rockchip,rv1126b-isp-pvtpll", "syscon"; + reg =3D <0x21c60000 0x100>; + rockchip,cru =3D <&cru>; + #clock-cells =3D <0>; + clock-output-names =3D "clk_isp_pvtpll"; + }; + + - | + pvtpll_enc: pvtpll-enc@21f00000 { + compatible =3D "rockchip,rv1126b-enc-pvtpll", "syscon"; + reg =3D <0x21f00000 0x100>; + #clock-cells =3D <0>; + clock-output-names =3D "clk_vepu_pvtpll"; + }; + + - | + pvtpll_aisp: pvtpll-aisp@21fc0000 { + compatible =3D "rockchip,rv1126b-aisp-pvtpll", "syscon"; + reg =3D <0x21fc0000 0x100>; + rockchip,cru =3D <&cru>; + #clock-cells =3D <0>; + clock-output-names =3D "clk_vcp_pvtpll"; + }; + + - | + pvtpll_npu: pvtpll-npu@22080000 { + compatible =3D "rockchip,rv1126b-npu-pvtpll", "syscon"; + reg =3D <0x22080000 0x100>; + rockchip,cru =3D <&cru>; + #clock-cells =3D <0>; + clock-output-names =3D "clk_npu_pvtpll"; + }; + +... --=20 2.34.1