From nobody Tue Feb 10 17:14:42 2026 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEE4033345C for ; Mon, 20 Oct 2025 20:22:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760991773; cv=none; b=iic6VdGBcYSSd3zvnd1v8C3ZhKsyOAYn+24zy2Xn6d/Pe3xCfVOk7KCU4y02k/PxNwNO19lSm1gMuuXtuLqvXfpHaNfZrRxiNUbmwA3QrCloEFEY10E/fIL2AWpgeapJlFnq6Tr9B86T/y1RT4iwAH+eORd3SHn6FKNnKy6Q5iM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760991773; c=relaxed/simple; bh=5BjKvcc/tENK3IyHGYbYH8RdeZGuMoAH+q4KjM10at8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D/ybO0vEBiQjHgnM5OEQuuTt7qdnfW9hw6wr5kgVI0177vOwT2q8umXfrOLWhye0P9m4RslXIRa7FZTkW+I3ketVD4/9WvH4ThlP+HBif1zBL6dQBaFYB9iKG8figmFqApk9diY+mCBlNUFJPHLKLKsaJv1IN916R5CH9V3pSH4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc.com header.i=@rivosinc.com header.b=L65d7rih; arc=none smtp.client-ip=209.85.210.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc.com header.i=@rivosinc.com header.b="L65d7rih" Received: by mail-pf1-f170.google.com with SMTP id d2e1a72fcca58-7930132f59aso6431908b3a.0 for ; Mon, 20 Oct 2025 13:22:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc.com; s=google; t=1760991771; x=1761596571; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pyem79rLJLXQpzWR0JwioWbcU+J8r0OLXTuCA/SaFvw=; b=L65d7rihkNEkn7e0sUQs9IbyPmgY87ggDZyQrP2WkPlKQLnHh2qQXsZ5n4Dh9eWaDl YY5zpNH++OKcG8oAX1Q41JS/SnNVBHBFJDS4LBPHUC6PBj5W9fLVg0/P64HT3OSE5nMi qBo0cNf0n7HsBNRTSMEjYT4q++RIbYu4BRnMxPbTxBc8iIfk4CvQw/ZZcZ0H3DXJQlFl gOcXyWkqppRjtXC48sPAUZhOA76mubmOh0kw1+9mlkR8tonbSl7BhnliqjUzpxQmiGRi Kbld0u5dZQ0mE70oilYIei2MNYYyyn/U3PdC+O2TAaYlijdN8nhO/Vj1dd6Pk3vNcjf2 8dPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760991771; x=1761596571; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pyem79rLJLXQpzWR0JwioWbcU+J8r0OLXTuCA/SaFvw=; b=b38YbZ1hMuYS5ihfQBIm4xYlkXAi7FMTR65FV8eNB35CuKcsESG2rD6G+T8Lgl3E+Y HZ2cree8lnk7mxbVC8ZrBqI4KbHowMw2rA+jnsSwYT7ABgaA5keT0lEJmj81NdwfY7RE hEXyv44jU7fqup5uiPTFqahFCJYpeLhhn8npfTd/WUiA8x7nuiWPvMmTU/io+jvY13eM CgXhs0QRSEWC9myi6qzL2i2jT7VkXi2yAQiFUY5bdXL4ZqE3A9nDya7KOeG+XcsT/jkN Uho8WBC4HpMm3tBDxGuBj1WcECDFx9yCV3vsbekohYm90axB7hBxU3emIXW/Kw5bX2Mr G46A== X-Gm-Message-State: AOJu0Yz1BWhkJUbfk29TCoB5WwE+9gmwRQ46bA72BEmcjoWZCZWOHUWe lmFdMpqEvWc8IBPN+fnJm61HAGg9Kx82GgMvrzC0qwT8sziaubJO3ul0wZaETQwmt/I= X-Gm-Gg: ASbGncsUhCgXmxQ5TIckkSTkFDgLUfNQs1YO0EZZOBJR3nzeeYsKDnrPd1vv4fTHC5I /SDXmfTI+3vSJuZ8ql7fWgqjBiDT4Z1/kiH7iQq5Odl08FAE00cSYPJZXlHGinNSKoUM4e30sdr hl43jNJOjAqotXwcj2qlSk86Q7kIEG1d4eZ1rS3TcFD+zMlnm6LbKe2Qc9GjqcM0/g22LKY2laa hkuir1+B+0JWsD53gDSB+9yhJfum5xtpAoJsx3N2q2PNPi9soHRhFYGDZCpPMAC/8BP36QZXj/u zPJ2j6YVyYYHJtsJqF1GWQ/Lq2I+Bvf9Y0F+dqYj9FpZiPV8AMdDf+hyieZ3uJO0isEAa1vtDqu DalX+M2+iaggaQbsqnE30XAJlZOfW1BsQz26iE31SySzbLUpXjDatkkw/ibRs+OK+lK0AuG3JTt chT+WuUMdS6g== X-Google-Smtp-Source: AGHT+IHCUggIPMFs3p3YqDKdkPO2jCwhmhi/bL773/KhCAQLWB8ulShW9Lr2mVwOqzrGgVQh6gVvsg== X-Received: by 2002:a05:6a20:42a3:b0:334:a82b:97d0 with SMTP id adf61e73a8af0-334a84cf411mr17749764637.22.1760991770903; Mon, 20 Oct 2025 13:22:50 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b6a766745dasm8443240a12.14.2025.10.20.13.22.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 13:22:50 -0700 (PDT) From: Deepak Gupta Date: Mon, 20 Oct 2025 13:22:35 -0700 Subject: [PATCH v22 06/28] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251020-v5_user_cfi_series-v22-6-66732256ad8f@rivosinc.com> References: <20251020-v5_user_cfi_series-v22-0-66732256ad8f@rivosinc.com> In-Reply-To: <20251020-v5_user_cfi_series-v22-0-66732256ad8f@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Benno Lossin Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Zong Li , Deepak Gupta X-Mailer: b4 0.13.0 `arch_calc_vm_prot_bits` is implemented on risc-v to return VM_READ | VM_WRITE if PROT_WRITE is specified. Similarly `riscv_sys_mmap` is updated to convert all incoming PROT_WRITE to (PROT_WRITE | PROT_READ). This is to make sure that any existing apps using PROT_WRITE still work. Earlier `protection_map[VM_WRITE]` used to pick read-write PTE encodings. Now `protection_map[VM_WRITE]` will always pick PAGE_SHADOWSTACK PTE encodings for shadow stack. Above changes ensure that existing apps continue to work because underneath kernel will be picking `protection_map[VM_WRITE|VM_READ]` PTE encodings. Reviewed-by: Zong Li Reviewed-by: Alexandre Ghiti Signed-off-by: Arnd Bergmann Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/mman.h | 26 ++++++++++++++++++++++++++ arch/riscv/include/asm/pgtable.h | 1 + arch/riscv/kernel/sys_riscv.c | 10 ++++++++++ arch/riscv/mm/init.c | 2 +- 4 files changed, 38 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/mman.h b/arch/riscv/include/asm/mman.h new file mode 100644 index 000000000000..0ad1d19832eb --- /dev/null +++ b/arch/riscv/include/asm/mman.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MMAN_H__ +#define __ASM_MMAN_H__ + +#include +#include +#include +#include + +static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot, + unsigned long pkey __always_unused) +{ + unsigned long ret =3D 0; + + /* + * If PROT_WRITE was specified, force it to VM_READ | VM_WRITE. + * Only VM_WRITE means shadow stack. + */ + if (prot & PROT_WRITE) + ret =3D (VM_READ | VM_WRITE); + return ret; +} + +#define arch_calc_vm_prot_bits(prot, pkey) arch_calc_vm_prot_bits(prot, pk= ey) + +#endif /* ! __ASM_MMAN_H__ */ diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index 29e994a9afb6..4c4057a2550e 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -182,6 +182,7 @@ extern struct pt_alloc_ops pt_ops __meminitdata; #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ _PAGE_EXEC | _PAGE_WRITE) +#define PAGE_SHADOWSTACK __pgprot(_PAGE_BASE | _PAGE_WRITE) =20 #define PAGE_COPY PAGE_READ #define PAGE_COPY_EXEC PAGE_READ_EXEC diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 795b2e815ac9..22fc9b3268be 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -7,6 +7,7 @@ =20 #include #include +#include =20 static long riscv_sys_mmap(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, @@ -16,6 +17,15 @@ static long riscv_sys_mmap(unsigned long addr, unsigned = long len, if (unlikely(offset & (~PAGE_MASK >> page_shift_offset))) return -EINVAL; =20 + /* + * If PROT_WRITE is specified then extend that to PROT_READ + * protection_map[VM_WRITE] is now going to select shadow stack encodings. + * So specifying PROT_WRITE actually should select protection_map [VM_WRI= TE | VM_READ] + * If user wants to create shadow stack then they should use `map_shadow_= stack` syscall. + */ + if (unlikely((prot & PROT_WRITE) && !(prot & PROT_READ))) + prot |=3D PROT_READ; + return ksys_mmap_pgoff(addr, len, prot, flags, fd, offset >> (PAGE_SHIFT - page_shift_offset)); } diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index d85efe74a4b6..62ab2c7de7c8 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -376,7 +376,7 @@ pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __aligned(P= AGE_SIZE); static const pgprot_t protection_map[16] =3D { [VM_NONE] =3D PAGE_NONE, [VM_READ] =3D PAGE_READ, - [VM_WRITE] =3D PAGE_COPY, + [VM_WRITE] =3D PAGE_SHADOWSTACK, [VM_WRITE | VM_READ] =3D PAGE_COPY, [VM_EXEC] =3D PAGE_EXEC, [VM_EXEC | VM_READ] =3D PAGE_READ_EXEC, --=20 2.45.0