From nobody Tue Feb 10 13:36:44 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94C202EB87B for ; Mon, 20 Oct 2025 09:10:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760951419; cv=none; b=JYGYyrciTKSoWJ1d/TWKFsdJxLTGWvRI/rK7CYa9BG5h/nsoffMCvxeqyynr5YI8JnwmQDteFzwfjB2202vx9DlbZgrW09u9nM2EGZdNElf7l34pZZvfbrfniugTwhXkVvDFrh0FUVd9B53TyqhqAomJqBuYSUaDdv+rMzq9W2E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760951419; c=relaxed/simple; bh=gip3WEVxcbEDhVNgyKGQVLGz/FDgnu9S4h+8+B4cMys=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JLw47P4CmlPWIuCd+kZqnyjUU1FRCVNL02H0vmKkqI4FE+A5D/VdsRQkOl9HNe0nGNLHt+QejnfPgD0UUGIq67y/oC6sKW0tEicR3WkH8HNt51MNyqOfvcCIhyyTYZfUcrtpnUCWXkJO3h8p+9JvO5aAI66ylcsaLUrAwUZevv4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.85.109]) by APP-03 (Coremail) with SMTP id rQCowAD3RoFo_PVo4mflEQ--.23190S6; Mon, 20 Oct 2025 17:10:01 +0800 (CST) From: Vivian Wang Date: Mon, 20 Oct 2025 17:09:59 +0800 Subject: [PATCH v4 4/5] riscv: bitops: Use riscv_has_extension_likely Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251020-riscv-altn-helper-wip-v4-4-ef941c87669a@iscas.ac.cn> References: <20251020-riscv-altn-helper-wip-v4-0-ef941c87669a@iscas.ac.cn> In-Reply-To: <20251020-riscv-altn-helper-wip-v4-0-ef941c87669a@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yury Norov , Rasmus Villemoes , Paul Walmsley Cc: Charlie Jenkins , Xiao Wang , =?utf-8?q?Christoph_M=C3=BCllner?= , Vivian Wang , Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-CM-TRANSID: rQCowAD3RoFo_PVo4mflEQ--.23190S6 X-Coremail-Antispam: 1UD129KBjvJXoWxGrW8Kw1rtFWrCw1DCrWDtwb_yoW5AF4xpr 97K347JFWDta45uFZFyryfXF4ruw47G3yfGryS9FykAFyUA39a9r90k3WFkr15AFWvga47 Zr4UJ3sxWa1UXw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUma14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2 ka0xkIwI1lc7CjxVAaw2AFwI0_Jw0_GFyl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Y z7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zV AF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1l IxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF 4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsG vfC2KfnxnUUI43ZEXa7VU1zpBDUUUUU== X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Use riscv_has_extension_likely() to check for RISCV_ISA_EXT_ZBB, replacing the use of asm goto with ALTERNATIVE. The "likely" variant is used to match the behavior of the original implementation using ALTERNATIVE("j %l[legacy]", "nop", ...). Signed-off-by: Vivian Wang --- arch/riscv/include/asm/bitops.h | 32 ++++++++------------------------ 1 file changed, 8 insertions(+), 24 deletions(-) diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitop= s.h index 77880677b06e..238092125c11 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -47,9 +47,8 @@ =20 static __always_inline __attribute_const__ unsigned long variable__ffs(uns= igned long word) { - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + return generic___ffs(word); =20 asm volatile (".option push\n" ".option arch,+zbb\n" @@ -58,9 +57,6 @@ static __always_inline __attribute_const__ unsigned long = variable__ffs(unsigned : "=3Dr" (word) : "r" (word) :); =20 return word; - -legacy: - return generic___ffs(word); } =20 /** @@ -76,9 +72,8 @@ static __always_inline __attribute_const__ unsigned long = variable__ffs(unsigned =20 static __always_inline __attribute_const__ unsigned long variable__fls(uns= igned long word) { - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + return generic___fls(word); =20 asm volatile (".option push\n" ".option arch,+zbb\n" @@ -87,9 +82,6 @@ static __always_inline __attribute_const__ unsigned long = variable__fls(unsigned : "=3Dr" (word) : "r" (word) :); =20 return BITS_PER_LONG - 1 - word; - -legacy: - return generic___fls(word); } =20 /** @@ -105,9 +97,8 @@ static __always_inline __attribute_const__ unsigned long= variable__fls(unsigned =20 static __always_inline __attribute_const__ int variable_ffs(int x) { - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + return generic_ffs(x); =20 if (!x) return 0; @@ -119,9 +110,6 @@ static __always_inline __attribute_const__ int variable= _ffs(int x) : "=3Dr" (x) : "r" (x) :); =20 return x + 1; - -legacy: - return generic_ffs(x); } =20 /** @@ -137,9 +125,8 @@ static __always_inline __attribute_const__ int variable= _ffs(int x) =20 static __always_inline int variable_fls(unsigned int x) { - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + return generic_fls(x); =20 if (!x) return 0; @@ -151,9 +138,6 @@ static __always_inline int variable_fls(unsigned int x) : "=3Dr" (x) : "r" (x) :); =20 return 32 - x; - -legacy: - return generic_fls(x); } =20 /** --=20 2.51.0