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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251020-imx8mp-pollux-display-overlays-v6-4-c65ceac56c53@phytec.de> References: <20251020-imx8mp-pollux-display-overlays-v6-0-c65ceac56c53@phytec.de> In-Reply-To: <20251020-imx8mp-pollux-display-overlays-v6-0-c65ceac56c53@phytec.de> To: Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , Peng Fan , Yannic Moog X-Mailer: b4 0.14.2 X-ClientProxiedBy: Postix.phytec.de (172.25.0.11) To Postix.phytec.de (172.25.0.11) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM1PEPF000252DA:EE_|PR3P195MB0975:EE_ X-MS-Office365-Filtering-Correlation-Id: a172fc8f-fff0-45e1-126c-08de0fd71d26 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?B?OU1Gelpmc0VkSFZwYWZ3bHdXQ0YwUThqN1kzdEVIb0hQaExyM0x1d1JIQWxu?= =?utf-8?B?UEpPU21ORWVWVFU5WDc3b0wyMll5VzNHdTB1TWxmRFBBUC9LZnEzbzFTRlMx?= =?utf-8?B?ZU9uekY1UmRNVzM3K0RZSlUzS3ppTEtPbFdqVHljMUNjWjhaOGVsSkZVa3ha?= =?utf-8?B?TXdhZ2FpSnh6Ukg0VjRLWHNRN0xOQ1RzdWhTYnpNUUNaY1BxeUpYVDJnMnRN?= =?utf-8?B?SGcwakphT0FFK3lnbmlSNGNaVTZ4d2dvb0w3VWJMSURzTFFxRlROVVBMUEJ1?= =?utf-8?B?aUhDU296VWhVVEtzWFdXSzBZQmoxUXhMbEtPckRhL3dlZENuY2kwb05jSFk3?= =?utf-8?B?VC9tZ3RRbHJuZGJYTnIwci9hOEllWkoxQWNvWTNubzhhbDRKakptaXM4alVr?= =?utf-8?B?NlZiMk9DVHlIS1N1MDNDaUxUVDdvMERCUkNJUGRnbXNOYXdiNVJRVXNnVHBT?= =?utf-8?B?eU12Y0hidEs1N2gvWHR1MzZ1blI2YVlzcXBDT3VqK1ZzanJBVzBLdUdsUmQ1?= =?utf-8?B?YTFxNjIrS1I5c2tHOG1Pd28rOSt0ditMVFRKczZVVVRwcXVKbXJVMGFsdEFa?= =?utf-8?B?ZUFYNGVuUWhZeXI3STZQTWpEUU4zYm5ibmJYQ2UzelYyNm9nUWJ2NGQvVlg4?= =?utf-8?B?VkVneFM0ZndTSGhyY3AyS0FTN2F1NTcvdGU4RE5BcU5wYi9FMGtZdGJIOGQ1?= =?utf-8?B?WXZrT1JlbWhtZGFsY1ZJODZFUXlnZDV1clBpWERWN2FaZjVnNG5UUDJlYmNw?= =?utf-8?B?SDhxMG9OY0tYUmZaTHRZeEJKRS9qamxJK0c0VjhjdSthaGo1a2tPZ1RIalhk?= =?utf-8?B?QVoycGRNWlRpZHMybDdjc1g0a3o0WEFNOGRhRmo5ZTI0Wi9HLzd4OS9BNFNC?= =?utf-8?B?WUdkL1pFVWhObTg3UnpQS2RzQlg0L252ZzVYUFNKb0JCTFVXS1kzY3VRVDVV?= =?utf-8?B?cUovWFRNN1ZMditrb1o3SUVHUGJrM0o0SHQ2amJZYWZJZ1BJdXJKRVRQTkxr?= =?utf-8?B?TzhpdFd5cjFuZjM3NkMzTVhTdTBERlBpRlJ1eGpncFI5RTA1UWFuYTlCUXBV?= =?utf-8?B?WEpUM01ONlRwd0pnc0dVeUxvQTZZZFB3NDhabUYvd3daN0JXbm8xWk1oUzlt?= =?utf-8?B?RTBUL00xM2hVd0RKaUNBSzB4M2R5ckgrMWkzMlhkOTdodTVPWmRxdWxpNlR2?= =?utf-8?B?cHEzall5dDcwdml2aVN3eVYrWGlSZ2lRUzFsMmxhNThWeDVmZDFCQ3VrakV3?= =?utf-8?B?d0hHVklMVDE0WlZpdTViY0RBUEM0K1IrUFJtdVI1RjNic1VVczdEdkVmRXRP?= =?utf-8?B?K0c4Wjk3cWUrUXExdFFuSGZYUkhpRmtEVmNjK2ZrMzh3NlJXTnVmd29FQ0JK?= =?utf-8?B?eUtWUnIxTC9lVU1HRDdueWVVYkdRQ3AyMytWbUtPR0gzZHZPaldrMW1hdTNL?= =?utf-8?B?SUcvZlp6L0JFMUxxclZFTUcxUFkxbytJL0Y3WTdhRVZRN0owTU0zTVd1SUhF?= =?utf-8?B?TG9CVzJyTWdUWmhmUmdNUTdxR1didFk0dGJvQ2Q0V3FaRXEyUXhQaStSK2lB?= =?utf-8?B?VFpIeFpmK2M2ODRmV2VDRFFHWnJ3c0xRUDJNd0wxZnlETWp3T1FTaHdoU1Zj?= =?utf-8?B?dnFYMXdwWHVvNVVkZnJqSFB2Qy8wMklwOWxkcXdvQS9NN3JLVTNJR3RYTkcz?= =?utf-8?B?M1I0NmFJSFZPU3dHd3NyeDFOVDRHTkVSTXhKYzQ3Q1BPMS9ieWFzSWhPd0tV?= =?utf-8?B?Q3hRKzJjRnJPQzgxNU15aGRsM2UzeWZBMFdscjRFS0x0REd1alBLSTZ0MDV2?= =?utf-8?B?bWZDZTVyRUJjeEQzVVE1QS9VL21reTBhWUNEUG55R3hZeEhoL0hDNGgwUzlT?= =?utf-8?B?dXhCS1hVLzBQall6MitpVk8zVWIza0YySWt1c1JIbXJIT3luUUFXNXJualMz?= =?utf-8?B?VGVCS3VTaXFodXhiVkhmVFA5MHlKbEhuaDI2LzZaaUpnZFhDTHFjOHlqb2VX?= =?utf-8?B?Q0lyMytRY2tTME9neGJJMnp2WXp6QUNYblViV011U3FsTUl3MmNsd29RRW5k?= =?utf-8?B?eFdrYzkxeU1ST1ZCKy94N0tWcmZjQkZ1RVl3Vy8yZW10c2s1MHhDMWJxczhs?= =?utf-8?Q?GyyY=3D?= X-Forefront-Antispam-Report: CIP:91.26.50.189;CTRY:DE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:Postix.phytec.de;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026);DIR:OUT;SFP:1102; X-OriginatorOrg: phytec.de X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Oct 2025 12:49:31.4156 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a172fc8f-fff0-45e1-126c-08de0fd71d26 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Postix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: AM1PEPF000252DA.eurprd07.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3P195MB0975 The same displays that can be connected directly to the imx8mp-phyboard-pollux can also be connected to the expansion board PEB-AV-10. For displays connected to the expansion board, a second LVDS channel of the i.MX 8M Plus SoC is used and only a single display connected to the SoC LVDS display bridge at a given time is supported. Reviewed-by: Peng Fan Signed-off-by: Yannic Moog --- arch/arm64/boot/dts/freescale/Makefile | 6 +++ ...mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso | 45 ++++++++++++++++++= ++++ ...8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso | 45 ++++++++++++++++++= ++++ 3 files changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 9c121041128972d2239e2cc74df98b0bf7de1ac2..e4b097446440f41785dd1a0e5d3= 54796e800ee76 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -222,11 +222,17 @@ imx8mp-phyboard-pollux-etml1010g3dra-dtbs +=3D imx8mp= -phyboard-pollux-rdk.dtb \ imx8mp-phyboard-pollux-etml1010g3dra.dtbo imx8mp-phyboard-pollux-peb-av-10-dtbs +=3D imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-phyboard-pollux-peb-av-10.dtbo +imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra-dtbs +=3D imx8mp-phyboard-p= ollux-rdk.dtb \ + imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtbo +imx8mp-phyboard-pollux-peb-av-10-ph128800t006-dtbs +=3D imx8mp-phyboard-po= llux-rdk.dtb \ + imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtbo imx8mp-phyboard-pollux-ph128800t006-dtbs +=3D imx8mp-phyboard-pollux-rdk.d= tb \ imx8mp-phyboard-pollux-ph128800t006.dtbo imx8mp-phyboard-pollux-rdk-no-eth-dtbs +=3D imx8mp-phyboard-pollux-rdk.dtb= imx8mp-phycore-no-eth.dtbo dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-etml1010g3dra.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-peb-av-10.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra= .dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-peb-av-10-ph128800t006.= dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-ph128800t006.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-rdk-no-eth.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-basic.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10= -etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-= peb-av-10-etml1010g3dra.dtso new file mode 100644 index 0000000000000000000000000000000000000000..aceb5b6056ef1298ad9e105e673= c7ab403411ab0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml10= 10g3dra.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "imx8mp-phyboard-pollux-peb-av-10.dtsi" + +&backlight_lvds0 { + brightness-levels =3D <0 8 16 32 64 128 255>; + default-brightness-level =3D <8>; + enable-gpios =3D <&gpio5 1 GPIO_ACTIVE_HIGH>; + num-interpolated-steps =3D <2>; + pwms =3D <&pwm4 0 50000 0>; + status =3D "okay"; +}; + +&lcdif2 { + status =3D "okay"; +}; + +&lvds_bridge { + assigned-clocks =3D <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents =3D <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 72.4 * 7 =3D 506.8 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 72.4 MHz. + */ + assigned-clock-rates =3D <0>, <506800000>; + status =3D "okay"; +}; + +&panel_lvds0 { + compatible =3D "edt,etml1010g3dra"; + status =3D "okay"; +}; + +&pwm4 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10= -ph128800t006.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-p= eb-av-10-ph128800t006.dtso new file mode 100644 index 0000000000000000000000000000000000000000..559286f384be452f1c953689e03= 249fbea24fac5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph1288= 00t006.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "imx8mp-phyboard-pollux-peb-av-10.dtsi" + +&backlight_lvds0 { + brightness-levels =3D <0 8 16 32 64 128 255>; + default-brightness-level =3D <8>; + enable-gpios =3D <&gpio5 1 GPIO_ACTIVE_HIGH>; + num-interpolated-steps =3D <2>; + pwms =3D <&pwm4 0 66667 0>; + status =3D "okay"; +}; + +&lcdif2 { + status =3D "okay"; +}; + +&lvds_bridge { + assigned-clocks =3D <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents =3D <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 66.5 * 7 =3D 465.5 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 66.5 MHz. + */ + assigned-clock-rates =3D <0>, <465500000>; + status =3D "okay"; +}; + +&panel_lvds0 { + compatible =3D "powertip,ph128800t006-zhc01"; + status =3D "okay"; +}; + +&pwm4 { + status =3D "okay"; +}; --=20 2.51.0