From nobody Fri Dec 19 01:37:54 2025 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 554152FE59F for ; Sat, 18 Oct 2025 12:12:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760789539; cv=none; b=afVPmz0jOX6ZuTMuDPltdveQv3ncwEsEAprlL4GYUHFWjliznGVI+UoSITp9wlbbC4QVGOTdZwmmWlUyGvk7cvHLJeh0yg72qzVdKtHUyrSATQn3ahmmL1sOfKFSV2SoRehCSQlftqZiwDvySxQXSMFmNGaRvzFCtuxvM4c6+rw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760789539; c=relaxed/simple; bh=g3c67g0JuAQ/MF5TeeywHnKyQWy5NcHxIAatThiSlk0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EGVb6kTUkZ3f0v0A6lEcMMC08NBikPaT1t6qDqkors2cok3AQKLQZkkD06p5rwFT699Qnlo73iR0LmmT9M/SKUDXWeJ8Wrdg3nSX+mVswmfPLoofbONwkbMH5Ow2CQTkz1E3HBvaIq2R+FXi8srJrO7NrLcu4qw2KABZeUf+2Ew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=mMQ5Xz4T; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mMQ5Xz4T" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-426f7da0b64so214863f8f.2 for ; Sat, 18 Oct 2025 05:12:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1760789534; x=1761394334; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X0t4ELZpwdFTZdxiqhNSp7y3ezBf0UkavYUxtLN6k7g=; b=mMQ5Xz4Tg13/YXtgSYozYmt/0dGtUOkwJn34nLZBnqSp13P2fdxaiZ6SfmISO/YQhN Da75lXbTnJGwVTFzpQFptGCm7h3k12rCkzke0qV+2MaMF6hj6TszX5kQCivkZLUi4Jo3 0rAx5q8x97U0Yhh452RGQwidAlKQmBLa46ZnMvhRfCvB72BTLvXJHPIj1j+Z5afMIbdb KyrhbtRhD80N+O4fEMXFab8ORTjvyiGmByNy/+Dnp6mIKrRvnVagE6PezsWOftGoMhDk BY2YzzdaM0PTzr7hR0p6lvxcogWWfiziRLHk6/XIY92+6S8DLU5PooVq8E6OZSK5e95a Nd1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760789534; x=1761394334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X0t4ELZpwdFTZdxiqhNSp7y3ezBf0UkavYUxtLN6k7g=; b=Cy2l+xYKFiKB/awEk3f+5IJUoImL79CLZDXgIbOYF/I08GpR3aHYr3a97fKOVB6Aod fQ+srpa6pOYnt+i7/WAs+4+cOKstC4EluUyag1mJwRNbJ6Rnwc5tZ6Wm3SmyNCMzxiOv k+Cp+2bmV0rTAQeS1oGl/zwsbV/5NMD+jbUkgVZuQASl4tZPz8j6ltZpLEHCozEW0nPA e2lhNwV95i3oxkj+LGVYilsAWHIKqINYVbluTWBJhabWqJmVfggNqNvKTTUo5fkerF7y wgCg8O3qlOhwr4GKbbv9XLUs2rKA7Mm9pfogaD9jItG3AowdHC3zasMqh5gF1qFB89Pu eqjw== X-Forwarded-Encrypted: i=1; AJvYcCWyUYPfg4HzpvnbksHrb4PhSRrGyKzZK8ItHb7XrUZEdKlMOGZVOMhbrZJWLCw4vMQOKPT5QzPutL3r6j0=@vger.kernel.org X-Gm-Message-State: AOJu0YzlcQ9S+ScyCAoJy6r8VEURaAuIGaBXCZj04JudYC1gsTAP1wTw r8oP5T3DunjW+YwLpbZadBHTkjsNs0u2Jj9gg0OhEHkhBH5qgEYiCZt6 X-Gm-Gg: ASbGncvYWTvZM852I5+FVVTCWXsy2Sjlc70NXF0gXiGBRMRYKU4gq2KZJp5hgsTLii0 sknPTPwJCoxyEhxRel10rUlGlkjBnJZ7nH8mkulHJ5gZna0pflmHddTLU3wfNI+vT6Z/15nXaTC DTolKzKtMNf2a39OU9V5PZmiMDv/MaDWZ4IZfoL+aLEbXP+XJ2bN72QUdfDFAHwAcfbh3pH3XrK cN2tAM3HdcAPFnuBlw9biFjc3zOlLiSVtxdZRkV8t1gr2B7SWakFn0OI0idzEYiCJvehwMyHyg/ O8wj7hJVfOSUDek/432OlDgozUOIx+E/ouTAJ4/LpFAJfKX6gPGORU2PTx9Qa6lvwe+7hJsERAe 96gQqs+79QALYLHnroPn1GjsgzMkVaSzQx3mq3Lx0zlaPDmx1nPO1HE0j/is/1ChC7NNfBPS3oc 7LPah2H/+lKRWi2nL8SqOXONZMtzyq89ruSvpU0Ks710zE/e5Co9Q= X-Google-Smtp-Source: AGHT+IHT8xlAGsvrmqTgrtBw+jrSf/dKaLIc5q20nHTcSN9mP4BR9UHnDuW98hA54JyOxHpF9e054A== X-Received: by 2002:a5d:56d2:0:b0:426:fff3:5d0c with SMTP id ffacd0b85a97d-42704d87f2fmr2247814f8f.1.1760789533368; Sat, 18 Oct 2025 05:12:13 -0700 (PDT) Received: from localhost.localdomain (84-74-0-139.dclient.hispeed.ch. [84.74.0.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5a0f19sm4763812f8f.9.2025.10.18.05.12.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Oct 2025 05:12:13 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, martin.petersen@oracle.com, pabeni@redhat.com, rostedt@goodmis.org, bhelgaas@google.com, l.rubusch@gmail.com Cc: arnd@arndb.de, matthew.gerlach@altera.com, tien.fong.chee@altera.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 11/11] ARM: dts: socfpga: add Enclustra SoM dts files Date: Sat, 18 Oct 2025 12:11:55 +0000 Message-Id: <20251018121155.7743-12-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251018121155.7743-1-l.rubusch@gmail.com> References: <20251018121155.7743-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the approach to set up a combination of Enclustra's SoM on a carrier board and corresponding boot-mode as single device-tree target. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/Makefile | 24 +++++++++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe1_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe3_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe3_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_st1_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_st1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_pe1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_pe3_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_st1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts | 16 +++++++++++++ 25 files changed, 408 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_st1_sdmmc.dts diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/i= ntel/socfpga/Makefile index 73a912ec6d95..8df0976da01c 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -2,6 +2,30 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ + socfpga_arria10_mercury_aa1_pe1_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe1_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe1_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe3_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_st1_emmc.dtb \ + socfpga_arria10_mercury_aa1_st1_qspi.dtb \ + socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_emmc.dts new file mode 100644 index 000000000000..b6cca0b5fd09 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_qspi.dts new file mode 100644 index 000000000000..6ad023477cd2 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_p= e1_sdmmc.dts new file mode 100644 index 000000000000..653c9a86516b --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_emmc.dts new file mode 100644 index 000000000000..ae9c7c6a2370 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_qspi.dts new file mode 100644 index 000000000000..c3a0c30a07a5 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_p= e3_sdmmc.dts new file mode 100644 index 000000000000..dc1e1ad20381 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_emmc.dts new file mode 100644 index 000000000000..61d5e4c85d9b --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_qspi.dts new file mode 100644 index 000000000000..a3b99c9b16fd --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_s= t1_sdmmc.dts new file mode 100644 index 000000000000..5deb289e2b55 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe1_emmc.dts new file mode 100644 index 000000000000..85d6146da0da --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe1_qspi.dts new file mode 100644 index 000000000000..770ab680a18c --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _pe1_sdmmc.dts new file mode 100644 index 000000000000..990ca0fec61e --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe3_emmc.dts new file mode 100644 index 000000000000..6c8fd5b0d6eb --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe3_qspi.dts new file mode 100644 index 000000000000..3292426078a1 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _pe3_sdmmc.dts new file mode 100644 index 000000000000..1eb10b5244dd --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= st1_emmc.dts new file mode 100644 index 000000000000..8c97b5b3adea --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= st1_qspi.dts new file mode 100644 index 000000000000..e6d14b22e41d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _st1_sdmmc.dts new file mode 100644 index 000000000000..beaeca94d4df --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= pe1_qspi.dts new file mode 100644 index 000000000000..6f79d9ed1d36 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _pe1_sdmmc.dts new file mode 100644 index 000000000000..b94bd8bafc26 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= pe3_qspi.dts new file mode 100644 index 000000000000..51fc4a22937a --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _pe3_sdmmc.dts new file mode 100644 index 000000000000..e4209209f4fa --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_s= t1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= st1_qspi.dts new file mode 100644 index 000000000000..ab4549a0d455 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_s= t1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _st1_sdmmc.dts new file mode 100644 index 000000000000..ebe62879c3fb --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; --=20 2.39.5