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[84.74.0.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5a0f19sm4763812f8f.9.2025.10.18.05.11.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Oct 2025 05:11:59 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, martin.petersen@oracle.com, pabeni@redhat.com, rostedt@goodmis.org, bhelgaas@google.com, l.rubusch@gmail.com Cc: arnd@arndb.de, matthew.gerlach@altera.com, tien.fong.chee@altera.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 01/11] ARM: dts: socfpga: add Enclustra boot-mode dtsi Date: Sat, 18 Oct 2025 12:11:45 +0000 Message-Id: <20251018121155.7743-2-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251018121155.7743-1-l.rubusch@gmail.com> References: <20251018121155.7743-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add generic boot-mode support to Enclustra Arria10 and Cyclone5 boards. Some Enclustra carrier boards need hardware adjustments specific to the selected boot-mode. Enclustra's Arria10 SoMs allow for booting from different media. By muxing certain IO pins, the media can be selected. This muxing can be done by gpios at runtime e.g. when flashing QSPI from off the bootloader. But also to have statically certain boot media available, certain adjustments to the DT are needed: - SD: QSPI must be disabled - eMMC: QSPI must be disabled, bus width can be doubled to 8 byte - QSPI: any mmc is disabled, QSPI then defaults to be enabled The boot media must be accessible to the bootloader, e.g. to load a bitstream file, but also to the system to mount the rootfs and to use the specific performance. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga_enclustra_mercury_bootmode_emmc.dtsi | 12 ++++++++++++ .../socfpga_enclustra_mercury_bootmode_qspi.dtsi | 8 ++++++++ .../socfpga_enclustra_mercury_bootmode_sdmmc.dtsi | 8 ++++++++ 3 files changed, 28 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_bootmode_emmc.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_bootmode_qspi.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_bootmode_sdmmc.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_boot= mode_emmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_= bootmode_emmc.dtsi new file mode 100644 index 000000000000..d79cb64da0de --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_em= mc.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status =3D "disabled"; +}; + +&mmc { + bus-width =3D <8>; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_boot= mode_qspi.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_= bootmode_qspi.dtsi new file mode 100644 index 000000000000..5ba21dd8f5ba --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qs= pi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&mmc { + status =3D "disabled"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_boot= mode_sdmmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury= _bootmode_sdmmc.dtsi new file mode 100644 index 000000000000..2b102e0b6217 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sd= mmc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status =3D "disabled"; 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[84.74.0.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5a0f19sm4763812f8f.9.2025.10.18.05.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Oct 2025 05:12:01 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, martin.petersen@oracle.com, pabeni@redhat.com, rostedt@goodmis.org, bhelgaas@google.com, l.rubusch@gmail.com Cc: arnd@arndb.de, matthew.gerlach@altera.com, tien.fong.chee@altera.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 02/11] ARM: dts: socfpga: add Enclustra base-board dtsi Date: Sat, 18 Oct 2025 12:11:46 +0000 Message-Id: <20251018121155.7743-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251018121155.7743-1-l.rubusch@gmail.com> References: <20251018121155.7743-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add generic Enclustra base-board support for the Mercury+ PE1, the Mercury+ PE3 and the Mercury+ ST1 board. The carrier boards can be freely combined with the SoMs Mercury+ AA1, Mercury SA1 and Mercury+ SA2. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga_enclustra_mercury_pe1.dtsi | 33 +++++++++++ .../socfpga_enclustra_mercury_pe3.dtsi | 55 +++++++++++++++++++ .../socfpga_enclustra_mercury_st1.dtsi | 15 +++++ 3 files changed, 103 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_pe1.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_pe3.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_st1.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi new file mode 100644 index 000000000000..abc4bfb7fccf --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + status =3D "okay"; + + eeprom@57 { + status =3D "okay"; + compatible =3D "microchip,24c128"; + reg =3D <0x57>; + pagesize =3D <64>; + label =3D "user eeprom"; + address-width =3D <16>; + }; + + lm96080: temperature-sensor@2f { + status =3D "okay"; + compatible =3D "national,lm80"; + reg =3D <0x2f>; + }; + + si5338: clock-controller@70 { + compatible =3D "silabs,si5338"; + reg =3D <0x70>; + }; + +}; + +&i2c_encl_fpga { + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi new file mode 100644 index 000000000000..bc57b0680878 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + i2c-mux@74 { + status =3D "okay"; + compatible =3D "nxp,pca9547"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x74>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + eeprom@56 { + status =3D "okay"; + compatible =3D "microchip,24c128"; + reg =3D <0x56>; + pagesize =3D <64>; + label =3D "user eeprom"; + address-width =3D <16>; + }; + + lm96080: temperature-sensor@2f { + status =3D "okay"; + compatible =3D "national,lm80"; + reg =3D <0x2f>; + }; + + pcal6416: gpio@20 { + status =3D "okay"; + compatible =3D "nxp,pcal6416"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; + }; + }; +}; + +&i2c_encl_fpga { + status =3D "okay"; + + i2c-mux@75 { + status =3D "okay"; + compatible =3D "nxp,pca9547"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x75>; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi new file mode 100644 index 000000000000..4c00475f4303 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + si5338: clock-controller@70 { + compatible =3D "silabs,si5338"; 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[84.74.0.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5a0f19sm4763812f8f.9.2025.10.18.05.12.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Oct 2025 05:12:02 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, martin.petersen@oracle.com, pabeni@redhat.com, rostedt@goodmis.org, bhelgaas@google.com, l.rubusch@gmail.com Cc: arnd@arndb.de, matthew.gerlach@altera.com, tien.fong.chee@altera.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 03/11] ARM: dts: socfpga: add Enclustra Mercury SA1 Date: Sat, 18 Oct 2025 12:11:47 +0000 Message-Id: <20251018121155.7743-4-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251018121155.7743-1-l.rubusch@gmail.com> References: <20251018121155.7743-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce support for Enclustra's Mercury SA1 SoM based on Intel Cyclone5 technology as a .dtsi file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_cyclone5_mercury_sa1.dtsi | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.d= tsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi new file mode 100644 index 000000000000..49944f9632f9 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model =3D "Enclustra Mercury SA1"; + compatible =3D "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + aliases { + ethernet0 =3D &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name =3D "memory"; + device_type =3D "memory"; + reg =3D <0x0 0x40000000>; /* 1GB */ + }; +}; + +&osc1 { + clock-frequency =3D <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns =3D <300>; + clock-frequency =3D <100000>; + status =3D "okay"; + + isl12020: rtc@6f { + compatible =3D "isil,isl12022"; + reg =3D <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns =3D <300>; + status =3D "disabled"; +}; + +&uart0 { + clock-frequency =3D <100000000>; +}; + +&mmc0 { + status =3D "okay"; + /delete-property/ cap-mmc-highspeed; + /delete-property/ cap-sd-highspeed; +}; + +&qspi { + status =3D "okay"; + + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <10000000>; + + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partition@raw { + label =3D "Flash Raw"; + reg =3D <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status =3D "okay"; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac1 { + status =3D "okay"; + /delete-property/ mac-address; + phy-mode =3D "rgmii-id"; + phy-handle =3D <&phy3>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg =3D <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps =3D <1680>; + rxd0-skew-ps =3D <420>; + rxd1-skew-ps =3D <420>; + rxd2-skew-ps =3D <420>; + rxd3-skew-ps =3D <420>; + rxdv-skew-ps =3D <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps =3D <1860>; + txd0-skew-ps =3D <0>; + txd1-skew-ps =3D <0>; + txd2-skew-ps =3D <0>; + txd3-skew-ps =3D <0>; + txen-skew-ps =3D <0>; + }; + }; +}; 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charset="utf-8" Update the DT binding for the Enclustra Mercury+ SA1 SoM Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 30c44a0e6407..30ef03c53d73 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -52,6 +52,16 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga =20 + - description: Mercury SA1 boards + items: + - enum: + - enclustra,mercury-sa1-pe1 + - enclustra,mercury-sa1-pe3 + - enclustra,mercury-sa1-st1 + - const: enclustra,mercury-sa1 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: --=20 2.39.5 From nobody Thu Dec 18 16:33:48 2025 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADE322D94A4 for ; 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[84.74.0.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5a0f19sm4763812f8f.9.2025.10.18.05.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Oct 2025 05:12:04 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, martin.petersen@oracle.com, pabeni@redhat.com, rostedt@goodmis.org, bhelgaas@google.com, l.rubusch@gmail.com Cc: arnd@arndb.de, matthew.gerlach@altera.com, tien.fong.chee@altera.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 05/11] ARM: dts: socfpga: add Enclustra Mercury+ SA2 Date: Sat, 18 Oct 2025 12:11:49 +0000 Message-Id: <20251018121155.7743-6-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251018121155.7743-1-l.rubusch@gmail.com> References: <20251018121155.7743-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce Enclustra's Mercury+ SA2 SoM based on Intel Cyclone5 technology as a .dtsi file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_cyclone5_mercury_sa2.dtsi | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.d= tsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi new file mode 100644 index 000000000000..0b28964e0378 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2"; + compatible =3D "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + aliases { + ethernet0 =3D &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name =3D "memory"; + device_type =3D "memory"; + reg =3D <0x0 0x80000000>; /* 2GB */ + }; +}; + +&osc1 { + clock-frequency =3D <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns =3D <300>; + clock-frequency =3D <100000>; + status =3D "okay"; + + isl12020: rtc@6f { + compatible =3D "isil,isl12022"; + reg =3D <0x6f>; + }; + + atsha204a: crypto@64 { + compatible =3D "atmel,atsha204a"; + reg =3D <0x64>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns =3D <300>; + status =3D "disabled"; +}; + +&uart0 { + clock-frequency =3D <100000000>; +}; + +&mmc0 { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; + + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <10000000>; + + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partition@raw { + label =3D "Flash Raw"; + reg =3D <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status =3D "okay"; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac1 { + status =3D "okay"; + /delete-property/ mac-address; + phy-mode =3D "rgmii-id"; + phy-handle =3D <&phy3>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg =3D <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps =3D <1680>; + rxd0-skew-ps =3D <420>; + rxd1-skew-ps =3D <420>; + rxd2-skew-ps =3D <420>; + rxd3-skew-ps =3D <420>; + rxdv-skew-ps =3D <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps =3D <1860>; + txd0-skew-ps =3D <0>; + txd1-skew-ps =3D <0>; + txd2-skew-ps =3D <0>; + txd3-skew-ps =3D <0>; + txen-skew-ps =3D <0>; + }; + }; +}; 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[84.74.0.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5a0f19sm4763812f8f.9.2025.10.18.05.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Oct 2025 05:12:05 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, martin.petersen@oracle.com, pabeni@redhat.com, rostedt@goodmis.org, bhelgaas@google.com, l.rubusch@gmail.com Cc: arnd@arndb.de, matthew.gerlach@altera.com, tien.fong.chee@altera.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v7 06/11] dt-bindings: altera: add binding for Mercury+ SA2 Date: Sat, 18 Oct 2025 12:11:50 +0000 Message-Id: <20251018121155.7743-7-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251018121155.7743-1-l.rubusch@gmail.com> References: <20251018121155.7743-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the device-tree binding for the Enclustra Mercury+ SA2 SoM. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 30ef03c53d73..72cf04b22a08 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -62,6 +62,16 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga =20 + - description: Mercury+ SA2 boards + items: + - enum: + - enclustra,mercury-sa2-pe1 + - enclustra,mercury-sa2-pe3 + - enclustra,mercury-sa2-st1 + - const: enclustra,mercury-sa2 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: --=20 2.39.5 From nobody Thu Dec 18 16:33:48 2025 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 252C429BDB1 for ; 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[84.74.0.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5a0f19sm4763812f8f.9.2025.10.18.05.12.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Oct 2025 05:12:06 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, martin.petersen@oracle.com, pabeni@redhat.com, rostedt@goodmis.org, bhelgaas@google.com, l.rubusch@gmail.com Cc: arnd@arndb.de, matthew.gerlach@altera.com, tien.fong.chee@altera.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 07/11] ARM: dts: socfpga: add Mercury AA1 variants Date: Sat, 18 Oct 2025 12:11:51 +0000 Message-Id: <20251018121155.7743-8-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251018121155.7743-1-l.rubusch@gmail.com> References: <20251018121155.7743-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce support for Enclustra's Mercury+ AA1 SoM, based on Intel Arria10. This is a flexible approach to allow for combining SoM with carrier board .dtsi and boot-mode .dtsi in a device-tree file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_arria10_mercury_aa1.dtsi | 143 +++++++++++++++--- 1 file changed, 121 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dt= si b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi index 41f865c8c098..c80201bce793 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi @@ -7,12 +7,14 @@ =20 / { =20 - model =3D "Enclustra Mercury AA1"; - compatible =3D "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,soc= fpga"; + model =3D "Enclustra Mercury+ AA1"; + compatible =3D "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; =20 aliases { ethernet0 =3D &gmac0; serial1 =3D &uart1; + spi0 =3D &qspi; }; =20 memory@0 { @@ -24,52 +26,102 @@ memory@0 { chosen { stdout-path =3D "serial1:115200n8"; }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc02300 { + }; + i2c_encl_fpga: i2c@ffc02200 { + }; + }; +}; + +&i2c_encl { + status =3D "okay"; + i2c-sda-hold-time-ns =3D <300>; + clock-frequency =3D <100000>; + + atsha204a: crypto@64 { + compatible =3D "atmel,atsha204a"; + reg =3D <0x64>; + }; + + isl12022: rtc@6f { + compatible =3D "isil,isl12022"; + reg =3D <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns =3D <300>; + status =3D "disabled"; }; =20 &gmac0 { - phy-mode =3D "rgmii"; + status =3D "okay"; + phy-mode =3D "rgmii-id"; phy-addr =3D <0xffffffff>; /* probe for phy addr */ - max-frame-size =3D <3800>; - phy-handle =3D <&phy3>; =20 + /delete-property/ mac-address; + mdio { #address-cells =3D <1>; #size-cells =3D <0>; compatible =3D "snps,dwmac-mdio"; phy3: ethernet-phy@3 { - txd0-skew-ps =3D <0>; /* -420ps */ - txd1-skew-ps =3D <0>; /* -420ps */ - txd2-skew-ps =3D <0>; /* -420ps */ - txd3-skew-ps =3D <0>; /* -420ps */ + reg =3D <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps =3D <1680>; /* 780ps */ rxd0-skew-ps =3D <420>; /* 0ps */ rxd1-skew-ps =3D <420>; /* 0ps */ rxd2-skew-ps =3D <420>; /* 0ps */ rxd3-skew-ps =3D <420>; /* 0ps */ - txen-skew-ps =3D <0>; /* -420ps */ - txc-skew-ps =3D <1860>; /* 960ps */ rxdv-skew-ps =3D <420>; /* 0ps */ - rxc-skew-ps =3D <1680>; /* 780ps */ - reg =3D <3>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps =3D <1860>; /* 960ps */ + txd0-skew-ps =3D <0>; /* -420ps */ + txd1-skew-ps =3D <0>; /* -420ps */ + txd2-skew-ps =3D <0>; /* -420ps */ + txd3-skew-ps =3D <0>; /* -420ps */ + txen-skew-ps =3D <0>; /* -420ps */ }; }; }; =20 -&i2c1 { - atsha204a: crypto@64 { - compatible =3D "atmel,atsha204a"; - reg =3D <0x64>; - }; +&gpio0 { + status =3D "okay"; +}; =20 - isl12022: isl12022@6f { - compatible =3D "isil,isl12022"; - reg =3D <0x6f>; - }; +&gpio1 { + status =3D "okay"; +}; + +&gpio2 { + status =3D "okay"; +}; + +&uart0 { + status =3D "disabled"; +}; + +&uart1 { + status =3D "okay"; }; =20 /* Following mappings are taken from arria10 socdk dts */ &mmc { + status =3D "okay"; cap-sd-highspeed; broken-cd; bus-width =3D <4>; @@ -79,3 +131,50 @@ &mmc { &osc1 { clock-frequency =3D <33330000>; }; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible =3D "altr,socfpga-sdmmc-ecc"; + reg =3D <0xff8c2c00 0x400>; + altr,ecc-parent =3D <&mmc>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&qspi { + status =3D "okay"; + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <10000000>; + + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partition@raw { + label =3D "Flash Raw"; + reg =3D <0x0 0x4000000>; + }; + }; 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[84.74.0.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5a0f19sm4763812f8f.9.2025.10.18.05.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Oct 2025 05:12:08 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, martin.petersen@oracle.com, pabeni@redhat.com, rostedt@goodmis.org, bhelgaas@google.com, l.rubusch@gmail.com Cc: arnd@arndb.de, matthew.gerlach@altera.com, tien.fong.chee@altera.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v7 08/11] dt-bindings: altera: add Mercury AA1 variants Date: Sat, 18 Oct 2025 12:11:52 +0000 Message-Id: <20251018121155.7743-9-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251018121155.7743-1-l.rubusch@gmail.com> References: <20251018121155.7743-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update binding with combined .dts for the Mercury+ PE1, PE3 and ST1 carrier boards with the Mercury+ AA1 SoM. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 72cf04b22a08..227665d0016f 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -31,6 +31,9 @@ properties: - description: Mercury+ AA1 boards items: - enum: + - enclustra,mercury-aa1-pe1 + - enclustra,mercury-aa1-pe3 + - enclustra,mercury-aa1-st1 - enclustra,mercury-pe1 - google,chameleon-v3 - const: enclustra,mercury-aa1 --=20 2.39.5 From nobody Thu Dec 18 16:33:48 2025 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 341052FB99F for ; Sat, 18 Oct 2025 12:12:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760789533; cv=none; b=mH7OTYmW9MnChKQ+hDr+MN0nIfmpNLfv7EpiYxM834GANryMdGy6lWGZ/n9sQwfPtTtuMEbR7mSChyEO/aDwinSN0Y6il86C+HA4usdpWQsGtQPeoUni6X1qU+tosxI1Zg8sQLvL/azpGL1P1FFtd+U5nH9quy21VmyNzFWxmSo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760789533; c=relaxed/simple; bh=3i5hN70EkS+R2vT407APeWIAYo0I/+m93+hR8moAbAg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=j79cUOlNeuiEH1jwdWH3P1Swho9iIAtfeNi8ygipyoQGYCB3+1IEbUqU5UqqYNBmB+V5qx0VU/e437c1N0esJW84QNNAiuXq/11DlCJVvL/IQ2mtJzc+u5AbQn/NIPGcgxgIqZuO5vCXjIkINFSZSzyeb+ThSM/yjjYfPcO/sCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=X1JkyaYD; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="X1JkyaYD" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-4271234b49cso140087f8f.3 for ; Sat, 18 Oct 2025 05:12:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1760789530; x=1761394330; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yj2U7Ks4Aai4rP5FlRiq75b6DNk0shSZ9f9hco/FDQo=; b=X1JkyaYDVQu6ShFZGoHAiHQF2ZYFHMyZ45VDNxgmq28xPHHUcIKNDsTVwmkxtjuTwU He/7BPEJV25YUifJMaHY3DqGZmSLbiIQwEodx2qlBIt380FBIA4czrIzcdJad+WkAkM6 UhbxVXd6BC2/7kdOZ7pbjRvykPFqYzWmkuy4hywMjWVUwfQRbISB11wg0cwDk4GFgsz/ Ld70ARbakhoA72ph7dYhf5z8jsaTWJE0Cs2HaUkx8Eg+eBVkPozbSQq1c2KsYe0DnOxO +GIN2NeC7JRC6VUj3qBuaD1cNUwqQf7EZEsSQcxsAocTbIttG2xBU0WyC/DoR5kn0wwz tZgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760789530; x=1761394330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yj2U7Ks4Aai4rP5FlRiq75b6DNk0shSZ9f9hco/FDQo=; b=S7KVkOR4BemDLm48V6swpgmMbmZwzv6HCCYXvbHSGoWcvp7PCN1k+Qw8I0s9idM5zM h+AL594zLu2HBPJo7ZwgNww/ByYZGy2th3CAun1yMzHG/s2XV4sMozV/U/yi548b5MFW 3V04vX/0fQgmGxBEQilR2Wp0Zqth3IaWsLJlQO+MG4SemhEI7kzXqVre76fjaDL4eHWJ Ye2zgExKKyStHak2op9o7rN7SeBAhT0GT13D+FwmriiPN9oRDIMMKZU96QXBRnrAUveC 2g+zfsYYfiVI67WCJvHfcFdvOaT64xd7aam1fZfl3NAG0Pnp9edwxBwYZItwPzcb+n2Y HlBg== X-Forwarded-Encrypted: i=1; AJvYcCXmqdti3TA2k3PIzi7Cik+G4Zp7oVSL+2p0G1cfNZw8xHIgF1k8569eGkT69FTC9mhx098HPB2Lj4qWidY=@vger.kernel.org X-Gm-Message-State: AOJu0YyGV4pEwz8tKXc6lOgedVjk46Y5USI97QB1c9aUvCQ5yxSkGyMg QEIdSjFTUE7VffDn/zk5OnC7Ym8HSHNd90bNf2AMonVTgvz804UutmMJ X-Gm-Gg: ASbGnctdEiUR4WvAD6HrY1748xth7o2/uFL+4nB2et3hy2x+yGjyqbgHdIKL5KR42yN W6arT1bkgFdE+58t5ecPHTQO7LEyj+bYQ2SimnLWZVhS/X3PJohIM3sKFo+rZI/KN1h7If6nnzU LbvJeICHRYGuNNeU6PmbDI4SS3ozPA9R9J4+NChvYTRX1x6ad3bv2ps3clXbClMImUnuHrwZkS3 6t5OH7P2HWTjwEf4qULQDdg6PrRpyd3rx1OJO6D4VnUG9SsBJnVR51wXA3J0SVLzwqHjb8Ld2pb KZCcgqNI4AJGp/shC77BUGeuRw11n/i1J/6EJHvRgJgDKvUnLHZdSeJSmj2ouHH+gobdEDzS+/C 2AMqt37zP4AgvCfPpNxLTdmuyx1Y/pcsyzUfN9AVoi0ZyzpHEJrqX+FLcvkkKtUB+AkuPbYF76a +XtS1lz9NxCY5GC6IIV3UIT12PGgAS7+apjyboEuBBst2uTWAmeLA= X-Google-Smtp-Source: AGHT+IEBdyKtF2N2KL9lmNfwqEGlADXNFa9DsShem0CkpLr8AuBNYJQxf6N3vylc+U/0FgLDa4AAyg== X-Received: by 2002:a05:600c:3149:b0:471:161b:4244 with SMTP id 5b1f17b1804b1-4711792a696mr28075605e9.5.1760789530237; Sat, 18 Oct 2025 05:12:10 -0700 (PDT) Received: from localhost.localdomain (84-74-0-139.dclient.hispeed.ch. [84.74.0.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5a0f19sm4763812f8f.9.2025.10.18.05.12.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Oct 2025 05:12:09 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, martin.petersen@oracle.com, pabeni@redhat.com, rostedt@goodmis.org, bhelgaas@google.com, l.rubusch@gmail.com Cc: arnd@arndb.de, matthew.gerlach@altera.com, tien.fong.chee@altera.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Steffen Trumtrar Subject: [PATCH v7 09/11] ARM: dts: socfpga: removal of generic PE1 dts Date: Sat, 18 Oct 2025 12:11:53 +0000 Message-Id: <20251018121155.7743-10-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251018121155.7743-1-l.rubusch@gmail.com> References: <20251018121155.7743-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the older socfpga_arria10_mercury_pe1.dts, since it is duplicate, the hardware is covered by the combination of Enclustra's .dtsi files. The older .dts was limited to only the case of having an Enclustra Mercury+ AA1 on a Mercury+ PE1 base board, booting from sdmmc. This functionality is provided also by the generic Enclustra dtsi and dts files, in particular socfpga_arria10_mercury_aa1_pe1_sdmmc.dts. Since both .dts files cover the same, the older one is to e replaced in favor of the more modularized approach. Signed-off-by: Lothar Rubusch Acked-by: Steffen Trumtrar --- arch/arm/boot/dts/intel/socfpga/Makefile | 1 - .../socfpga/socfpga_arria10_mercury_pe1.dts | 55 ------------------- 2 files changed, 56 deletions(-) delete mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _pe1.dts diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/i= ntel/socfpga/Makefile index 7f69a0355ea5..73a912ec6d95 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -2,7 +2,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ - socfpga_arria10_mercury_pe1.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dt= s b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts deleted file mode 100644 index cf533f76a9fd..000000000000 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2023 Steffen Trumtrar - */ -/dts-v1/; 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[84.74.0.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5a0f19sm4763812f8f.9.2025.10.18.05.12.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Oct 2025 05:12:11 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, martin.petersen@oracle.com, pabeni@redhat.com, rostedt@goodmis.org, bhelgaas@google.com, l.rubusch@gmail.com Cc: arnd@arndb.de, matthew.gerlach@altera.com, tien.fong.chee@altera.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v7 10/11] dt-bindings: altera: removal of generic PE1 dts Date: Sat, 18 Oct 2025 12:11:54 +0000 Message-Id: <20251018121155.7743-11-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251018121155.7743-1-l.rubusch@gmail.com> References: <20251018121155.7743-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the binding for the generic Mercury+ AA1 on PE1 carrier board. The removed Mercury+ AA1 on PE1 carrier board is just a particular setup case, which is actually replaced by the set of generic Mercury+ AA1 combinations patch. In other words a combination of a Mercury+ AA1 on a PE1 base board, with boot mode SD card is already covered by the generic AA1 combinations. There is no further reason to keep this particular case now in a redundantly. Thus the redundant DT setup is removed. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 227665d0016f..db61537b7115 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -34,7 +34,6 @@ properties: - enclustra,mercury-aa1-pe1 - enclustra,mercury-aa1-pe3 - enclustra,mercury-aa1-st1 - - enclustra,mercury-pe1 - google,chameleon-v3 - const: enclustra,mercury-aa1 - const: altr,socfpga-arria10 --=20 2.39.5 From nobody Thu Dec 18 16:33:48 2025 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 554152FE59F for ; Sat, 18 Oct 2025 12:12:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760789539; cv=none; b=afVPmz0jOX6ZuTMuDPltdveQv3ncwEsEAprlL4GYUHFWjliznGVI+UoSITp9wlbbC4QVGOTdZwmmWlUyGvk7cvHLJeh0yg72qzVdKtHUyrSATQn3ahmmL1sOfKFSV2SoRehCSQlftqZiwDvySxQXSMFmNGaRvzFCtuxvM4c6+rw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760789539; c=relaxed/simple; bh=g3c67g0JuAQ/MF5TeeywHnKyQWy5NcHxIAatThiSlk0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EGVb6kTUkZ3f0v0A6lEcMMC08NBikPaT1t6qDqkors2cok3AQKLQZkkD06p5rwFT699Qnlo73iR0LmmT9M/SKUDXWeJ8Wrdg3nSX+mVswmfPLoofbONwkbMH5Ow2CQTkz1E3HBvaIq2R+FXi8srJrO7NrLcu4qw2KABZeUf+2Ew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=mMQ5Xz4T; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mMQ5Xz4T" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-426f7da0b64so214863f8f.2 for ; Sat, 18 Oct 2025 05:12:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1760789534; x=1761394334; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X0t4ELZpwdFTZdxiqhNSp7y3ezBf0UkavYUxtLN6k7g=; b=mMQ5Xz4Tg13/YXtgSYozYmt/0dGtUOkwJn34nLZBnqSp13P2fdxaiZ6SfmISO/YQhN Da75lXbTnJGwVTFzpQFptGCm7h3k12rCkzke0qV+2MaMF6hj6TszX5kQCivkZLUi4Jo3 0rAx5q8x97U0Yhh452RGQwidAlKQmBLa46ZnMvhRfCvB72BTLvXJHPIj1j+Z5afMIbdb KyrhbtRhD80N+O4fEMXFab8ORTjvyiGmByNy/+Dnp6mIKrRvnVagE6PezsWOftGoMhDk BY2YzzdaM0PTzr7hR0p6lvxcogWWfiziRLHk6/XIY92+6S8DLU5PooVq8E6OZSK5e95a Nd1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760789534; x=1761394334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X0t4ELZpwdFTZdxiqhNSp7y3ezBf0UkavYUxtLN6k7g=; b=Cy2l+xYKFiKB/awEk3f+5IJUoImL79CLZDXgIbOYF/I08GpR3aHYr3a97fKOVB6Aod fQ+srpa6pOYnt+i7/WAs+4+cOKstC4EluUyag1mJwRNbJ6Rnwc5tZ6Wm3SmyNCMzxiOv k+Cp+2bmV0rTAQeS1oGl/zwsbV/5NMD+jbUkgVZuQASl4tZPz8j6ltZpLEHCozEW0nPA e2lhNwV95i3oxkj+LGVYilsAWHIKqINYVbluTWBJhabWqJmVfggNqNvKTTUo5fkerF7y wgCg8O3qlOhwr4GKbbv9XLUs2rKA7Mm9pfogaD9jItG3AowdHC3zasMqh5gF1qFB89Pu eqjw== X-Forwarded-Encrypted: i=1; AJvYcCWyUYPfg4HzpvnbksHrb4PhSRrGyKzZK8ItHb7XrUZEdKlMOGZVOMhbrZJWLCw4vMQOKPT5QzPutL3r6j0=@vger.kernel.org X-Gm-Message-State: AOJu0YzlcQ9S+ScyCAoJy6r8VEURaAuIGaBXCZj04JudYC1gsTAP1wTw r8oP5T3DunjW+YwLpbZadBHTkjsNs0u2Jj9gg0OhEHkhBH5qgEYiCZt6 X-Gm-Gg: ASbGncvYWTvZM852I5+FVVTCWXsy2Sjlc70NXF0gXiGBRMRYKU4gq2KZJp5hgsTLii0 sknPTPwJCoxyEhxRel10rUlGlkjBnJZ7nH8mkulHJ5gZna0pflmHddTLU3wfNI+vT6Z/15nXaTC DTolKzKtMNf2a39OU9V5PZmiMDv/MaDWZ4IZfoL+aLEbXP+XJ2bN72QUdfDFAHwAcfbh3pH3XrK cN2tAM3HdcAPFnuBlw9biFjc3zOlLiSVtxdZRkV8t1gr2B7SWakFn0OI0idzEYiCJvehwMyHyg/ O8wj7hJVfOSUDek/432OlDgozUOIx+E/ouTAJ4/LpFAJfKX6gPGORU2PTx9Qa6lvwe+7hJsERAe 96gQqs+79QALYLHnroPn1GjsgzMkVaSzQx3mq3Lx0zlaPDmx1nPO1HE0j/is/1ChC7NNfBPS3oc 7LPah2H/+lKRWi2nL8SqOXONZMtzyq89ruSvpU0Ks710zE/e5Co9Q= X-Google-Smtp-Source: AGHT+IHT8xlAGsvrmqTgrtBw+jrSf/dKaLIc5q20nHTcSN9mP4BR9UHnDuW98hA54JyOxHpF9e054A== X-Received: by 2002:a5d:56d2:0:b0:426:fff3:5d0c with SMTP id ffacd0b85a97d-42704d87f2fmr2247814f8f.1.1760789533368; Sat, 18 Oct 2025 05:12:13 -0700 (PDT) Received: from localhost.localdomain (84-74-0-139.dclient.hispeed.ch. [84.74.0.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5a0f19sm4763812f8f.9.2025.10.18.05.12.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Oct 2025 05:12:13 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, martin.petersen@oracle.com, pabeni@redhat.com, rostedt@goodmis.org, bhelgaas@google.com, l.rubusch@gmail.com Cc: arnd@arndb.de, matthew.gerlach@altera.com, tien.fong.chee@altera.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 11/11] ARM: dts: socfpga: add Enclustra SoM dts files Date: Sat, 18 Oct 2025 12:11:55 +0000 Message-Id: <20251018121155.7743-12-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251018121155.7743-1-l.rubusch@gmail.com> References: <20251018121155.7743-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the approach to set up a combination of Enclustra's SoM on a carrier board and corresponding boot-mode as single device-tree target. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/Makefile | 24 +++++++++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe1_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe3_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe3_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_st1_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_st1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_pe1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_pe3_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_st1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts | 16 +++++++++++++ 25 files changed, 408 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_st1_sdmmc.dts diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/i= ntel/socfpga/Makefile index 73a912ec6d95..8df0976da01c 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -2,6 +2,30 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ + socfpga_arria10_mercury_aa1_pe1_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe1_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe1_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe3_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_st1_emmc.dtb \ + socfpga_arria10_mercury_aa1_st1_qspi.dtb \ + socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_emmc.dts new file mode 100644 index 000000000000..b6cca0b5fd09 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_qspi.dts new file mode 100644 index 000000000000..6ad023477cd2 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_p= e1_sdmmc.dts new file mode 100644 index 000000000000..653c9a86516b --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_emmc.dts new file mode 100644 index 000000000000..ae9c7c6a2370 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_qspi.dts new file mode 100644 index 000000000000..c3a0c30a07a5 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_p= e3_sdmmc.dts new file mode 100644 index 000000000000..dc1e1ad20381 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_emmc.dts new file mode 100644 index 000000000000..61d5e4c85d9b --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_qspi.dts new file mode 100644 index 000000000000..a3b99c9b16fd --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_s= t1_sdmmc.dts new file mode 100644 index 000000000000..5deb289e2b55 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe1_emmc.dts new file mode 100644 index 000000000000..85d6146da0da --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe1_qspi.dts new file mode 100644 index 000000000000..770ab680a18c --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _pe1_sdmmc.dts new file mode 100644 index 000000000000..990ca0fec61e --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe3_emmc.dts new file mode 100644 index 000000000000..6c8fd5b0d6eb --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe3_qspi.dts new file mode 100644 index 000000000000..3292426078a1 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _pe3_sdmmc.dts new file mode 100644 index 000000000000..1eb10b5244dd --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= st1_emmc.dts new file mode 100644 index 000000000000..8c97b5b3adea --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= st1_qspi.dts new file mode 100644 index 000000000000..e6d14b22e41d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _st1_sdmmc.dts new file mode 100644 index 000000000000..beaeca94d4df --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= pe1_qspi.dts new file mode 100644 index 000000000000..6f79d9ed1d36 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _pe1_sdmmc.dts new file mode 100644 index 000000000000..b94bd8bafc26 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= pe3_qspi.dts new file mode 100644 index 000000000000..51fc4a22937a --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _pe3_sdmmc.dts new file mode 100644 index 000000000000..e4209209f4fa --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_s= t1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= st1_qspi.dts new file mode 100644 index 000000000000..ab4549a0d455 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_s= t1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _st1_sdmmc.dts new file mode 100644 index 000000000000..ebe62879c3fb --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; --=20 2.39.5