From nobody Sat Feb 7 17:41:20 2026 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7E6D28B415 for ; Fri, 17 Oct 2025 23:52:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760745139; cv=none; b=WAWj6Jo+C8nTgGMMqonlm7y4rd7ekiP0dGC9q2dod42LkDvCN52r6S1ulgW2o0G20gdv7f/QC0dnbVFKvp0f11jPI2Lig++Ejy2Wq2OOxoIwWPcLRLQpkXH0u67QCerR+WjDqEQbGZ+TWbTptL6z8P8T0li6m9cnOLs26OoTX+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760745139; c=relaxed/simple; bh=8bQcQXKOnjjGmI+q61EF/zlP1JyrJVr+At0emP3d0zo=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=WHfVHjKH3y50F1k5QMq1pWNKi5THfeH8YM8zM2AFVhlzGUz1JDeaAlR0SZ6y9O2kYdR0/vt0758mnlOpoeGCXKQZGWpCd773PzfI5M8ABNZ0gZbnVPKNcIz7HVpHF37pj/fbXkowxKMsMSksL52z23AVpw4XJ+J5TlKzyXq3DBI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--royluo.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=o3jvYXt0; arc=none smtp.client-ip=209.85.214.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--royluo.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="o3jvYXt0" Received: by mail-pl1-f202.google.com with SMTP id d9443c01a7336-28e538b5f23so27649575ad.3 for ; Fri, 17 Oct 2025 16:52:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1760745137; x=1761349937; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=rFUd4KPZzUTUCisRlC6z64P8M16hH71AE+17EZ2+Cpk=; b=o3jvYXt0e6G5GxPaSloyxEo9MMUna9Ts1UE0vKy9i8Vn8m3hf+jSnnzBPgu4Dv8bBF M7+P6Cvobau9GEzrs9d4J97SHbW9OCdHS1l2EwrsBMCIkTlLQee7tWw2zVW/xbfsXcdS 7amUn1m/31X98bkpjbDoiDV3aGv8t1hxSBnhu0cg58gsLmriZHax466d52jqd28miiGh uzXMR4s85+tH5pzCnittcagnsXSXq7x2hu2B0Qv1axPDWWGmb7m3Eckp/fS/vnPKCkoO s8TaAkQfF8wPEsR5cJ+UtJkmaNTCJp/IbKFCpvGm1MRV2MxhPwYJiZrwcQQM5ByAANB6 n+bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760745137; x=1761349937; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=rFUd4KPZzUTUCisRlC6z64P8M16hH71AE+17EZ2+Cpk=; b=v3KwDF7NrI7zzXf6u/DnktftbiJG2jPD4USCyNzvT7gPkroweKguq3LFbT5qR0YemF 06FSdYpShAhWS/v0WiXxLBiAn9jNhGgo6ROlBUDUg/h25B4TrDBwVsHbC/gC3HXJSLdy a4aLIZPFNAvIqYKrcALBwZQFnPMazB+sgCcKRbBxzjKNPXjesaACtzyTQeKcH1r7d76c r6pD4jmqf24V598flYEsqavcWoi8HBTFIDdpTC9PbK7uAvh+B/hMXc9BB766DrESGteB pLtefavvxodaLxbXeNwuoKeicT/qn5EJP0YeQM7g5E6VmT9xDfWJa0831aVxeg0X3fPh ds4w== X-Forwarded-Encrypted: i=1; AJvYcCXlqDDO2mucosZSBOFtsrOHn5aARZHyHrL4cl1OubPyjKgheclaqwKf+nAn/mubZ77tvREotPGql8aGSUY=@vger.kernel.org X-Gm-Message-State: AOJu0Yx9AzXwrYcqjMenwpdUbaY+78CqhtkPs1iMVX3yr5jiWVEO6WuN cQCRy+GRNfVZEXpW6JwNQedmDaxEZyP+ePtbnNdJvY5FC8XWqDEPMa8UYDecDwcWLA0eKOt5TOh oTMYgzg== X-Google-Smtp-Source: AGHT+IGtonGWIlL28ar3C4SMS3Z4eGNFhKCMbFqjIxEvFkEnJLs3JqhHMERukcTD3gq5IHrZVsg/cEtJU7Y= X-Received: from plbkg4.prod.google.com ([2002:a17:903:604:b0:290:be3d:aff6]) (user=royluo job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:384c:b0:27e:d9a0:ba08 with SMTP id d9443c01a7336-290cb27dae5mr68350725ad.43.1760745137248; Fri, 17 Oct 2025 16:52:17 -0700 (PDT) Date: Fri, 17 Oct 2025 23:51:58 +0000 In-Reply-To: <20251017235159.2417576-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251017235159.2417576-1-royluo@google.com> X-Mailer: git-send-email 2.51.0.858.gf9c4a03a3a-goog Message-ID: <20251017235159.2417576-2-royluo@google.com> Subject: [PATCH v4 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , Badhri Jagan Sridharan , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the device tree bindings for the USB PHY interfaces integrated with the DWC3 controller on Google Tensor SoCs, starting with G5 generation. The USB PHY on Tensor G5 includes two integrated Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. Due to a complete architectural overhaul in the Google Tensor G5, the existing Samsung/Exynos USB PHY binding for older generations of Google silicons such as gs101 are no longer compatible, necessitating this new device tree binding. Signed-off-by: Roy Luo --- .../bindings/phy/google,gs5-usb-phy.yaml | 104 ++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/google,gs5-usb-ph= y.yaml diff --git a/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml = b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml new file mode 100644 index 000000000000..c92c20eba1ea --- /dev/null +++ b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025, Google LLC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/google,gs5-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Tensor Series (G5+) USB PHY + +maintainers: + - Roy Luo + +description: | + Describes the USB PHY interfaces integrated with the DWC3 USB controller= on + Google Tensor SoCs, starting with the G5 generation. + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PH= Y IP + and USB 3.2/DisplayPort combo PHY IP. + The hardware can support three PHY interfaces, which are selected using = the + first phandle argument in the PHY specifier:: + 0 - USB high-speed. + 1 - USB super-speed. + 2 - DisplayPort + +properties: + compatible: + const: google,gs5-usb-phy + + reg: + items: + - description: USB2 PHY configuration registers. + - description: USB 3.2/DisplayPort combo PHY top-level registers. + + reg-names: + items: + - const: u2phy_cfg + - const: dp_top + + "#phy-cells": + const: 1 + + clocks: + items: + - description: USB2 PHY clock. + - description: USB2 PHY APB clock. + + clock-names: + items: + - const: usb2_phy + - const: u2phy_apb + + resets: + items: + - description: USB2 PHY reset. + - description: USB2 PHY APB reset. + + reset-names: + items: + - const: usb2_phy + - const: u2phy_apb + + power-domains: + maxItems: 1 + + orientation-switch: + type: boolean + description: + Indicates the PHY as a handler of USB Type-C orientation changes + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + - power-domains + - orientation-switch + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + usb_phy: usb_phy@c450014 { + compatible =3D "google,gs5-usb-phy"; + reg =3D <0 0x0c450014 0 0xc>, + <0 0x0c637000 0 0xa0>; + reg-names =3D "u2phy_cfg", "dp_top"; + #phy-cells =3D <1>; + clocks =3D <&hsion_usb2_phy_clk>, <&hsion_u2phy_apb_clk>; + clock-names =3D "usb2_phy", "u2phy_apb"; + resets =3D <&hsion_resets_usb2_phy>, + <&hsion_resets_u2phy_apb>; + reset-names =3D "usb2_phy", "u2phy_apb"; + power-domains =3D <&hsio_n_usb_pd>; + orientation-switch; + }; + }; +... --=20 2.51.0.858.gf9c4a03a3a-goog From nobody Sat Feb 7 17:41:20 2026 Received: from mail-yx1-f74.google.com (mail-yx1-f74.google.com [74.125.224.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3E5531282E for ; Fri, 17 Oct 2025 23:52:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.224.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Fri, 17 Oct 2025 16:52:20 -0700 (PDT) Date: Fri, 17 Oct 2025 23:51:59 +0000 In-Reply-To: <20251017235159.2417576-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251017235159.2417576-1-royluo@google.com> X-Mailer: git-send-email 2.51.0.858.gf9c4a03a3a-goog Message-ID: <20251017235159.2417576-3-royluo@google.com> Subject: [PATCH v4 2/2] phy: Add Google Tensor SoC USB PHY driver From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , Badhri Jagan Sridharan , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support the USB PHY found on Google Tensor G5. This particular USB PHY supports both high-speed and super-speed operations, and is integrated with the SNPS DWC3 controller that's also on the SoC. This initial patch specifically adds functionality for high-speed. Co-developed-by: Joy Chakraborty Signed-off-by: Joy Chakraborty Co-developed-by: Naveen Kumar Signed-off-by: Naveen Kumar Signed-off-by: Roy Luo --- drivers/phy/Kconfig | 13 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-google-usb.c | 271 +++++++++++++++++++++++++++++++++++ 3 files changed, 285 insertions(+) create mode 100644 drivers/phy/phy-google-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 58c911e1b2d2..fe32d1356002 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -101,6 +101,19 @@ config PHY_NXP_PTN3222 schemes. It supports all three USB 2.0 data rates: Low Speed, Full Speed and High Speed. =20 +config PHY_GOOGLE_USB + tristate "Google Tensor SoC USB PHY driver" + depends on HAS_IOMEM + depends on OF + depends on TYPEC + select GENERIC_PHY + help + Enable support for the USB PHY on Google Tensor SoCs, starting with + the G5 generation. This driver provides the PHY interfaces to + interact with the SNPS eUSB2 and USB 3.2/DisplayPort Combo PHY, both + of which are integrated with the DWC3 USB controller. + This driver currently supports USB high-speed. + source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index c670a8dac468..1d7a1331bd19 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) +=3D phy-snps-eusb2.o obj-$(CONFIG_USB_LGM_PHY) +=3D phy-lgm-usb.o obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o +obj-$(CONFIG_PHY_GOOGLE_USB) +=3D phy-google-usb.o obj-y +=3D allwinner/ \ amlogic/ \ broadcom/ \ diff --git a/drivers/phy/phy-google-usb.c b/drivers/phy/phy-google-usb.c new file mode 100644 index 000000000000..75e4233a5ab5 --- /dev/null +++ b/drivers/phy/phy-google-usb.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-google-usb.c - Google USB PHY driver + * + * Copyright (C) 2025, Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USBCS_USB2PHY_CFG19_OFFSET 0x0 +#define USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV GENMASK(19, 8) + +#define USBCS_USB2PHY_CFG21_OFFSET 0x8 +#define USBCS_USB2PHY_CFG21_PHY_ENABLE BIT(12) +#define USBCS_USB2PHY_CFG21_REF_FREQ_SEL GENMASK(15, 13) +#define USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL BIT(19) + +#define USBCS_PHY_CFG1_OFFSET 0x28 +#define USBCS_PHY_CFG1_SYS_VBUSVALID BIT(17) + +enum google_usb_phy_id { + GOOGLE_USB2_PHY, + GOOGLE_USB_PHY_NUM, +}; + +struct google_usb_phy_instance { + int index; + struct phy *phy; + int num_clks; + struct clk_bulk_data *clks; + struct reset_control *rsts; +}; + +struct google_usb_phy { + struct device *dev; + void __iomem *u2phy_cfg_base; + void __iomem *dp_top_base; + struct google_usb_phy_instance insts[GOOGLE_USB_PHY_NUM]; + /* serialize phy access */ + struct mutex phy_mutex; + struct typec_switch_dev *sw; + enum typec_orientation orientation; +}; + +static inline struct google_usb_phy *to_google_usb_phy(struct google_usb_p= hy_instance *inst) +{ + return container_of(inst, struct google_usb_phy, insts[inst->index]); +} + +static void set_vbus_valid(struct google_usb_phy *gphy) +{ + u32 reg; + + if (gphy->orientation =3D=3D TYPEC_ORIENTATION_NONE) { + reg =3D readl(gphy->dp_top_base + USBCS_PHY_CFG1_OFFSET); + reg &=3D ~USBCS_PHY_CFG1_SYS_VBUSVALID; + writel(reg, gphy->dp_top_base + USBCS_PHY_CFG1_OFFSET); + } else { + reg =3D readl(gphy->dp_top_base + USBCS_PHY_CFG1_OFFSET); + reg |=3D USBCS_PHY_CFG1_SYS_VBUSVALID; + writel(reg, gphy->dp_top_base + USBCS_PHY_CFG1_OFFSET); + } +} + +static int google_usb_set_orientation(struct typec_switch_dev *sw, + enum typec_orientation orientation) +{ + struct google_usb_phy *gphy =3D typec_switch_get_drvdata(sw); + + dev_dbg(gphy->dev, "set orientation %d\n", orientation); + + gphy->orientation =3D orientation; + + if (pm_runtime_suspended(gphy->dev)) + return 0; + + guard(mutex)(&gphy->phy_mutex); + + set_vbus_valid(gphy); + + return 0; +} + +static int google_usb2_phy_init(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D to_google_usb_phy(inst); + u32 reg; + int ret =3D 0; + + dev_dbg(gphy->dev, "initializing usb2 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + reg =3D readl(gphy->u2phy_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + reg &=3D ~USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL; + reg &=3D ~USBCS_USB2PHY_CFG21_REF_FREQ_SEL; + reg |=3D FIELD_PREP(USBCS_USB2PHY_CFG21_REF_FREQ_SEL, 0); + writel(reg, gphy->u2phy_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + + reg =3D readl(gphy->u2phy_cfg_base + USBCS_USB2PHY_CFG19_OFFSET); + reg &=3D ~USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV; + reg |=3D FIELD_PREP(USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV, 368); + writel(reg, gphy->u2phy_cfg_base + USBCS_USB2PHY_CFG19_OFFSET); + + set_vbus_valid(gphy); + + ret =3D clk_bulk_prepare_enable(inst->num_clks, inst->clks); + if (ret) + return ret; + + ret =3D reset_control_deassert(inst->rsts); + if (ret) { + clk_bulk_disable_unprepare(inst->num_clks, inst->clks); + return ret; + } + + reg =3D readl(gphy->u2phy_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + reg |=3D USBCS_USB2PHY_CFG21_PHY_ENABLE; + writel(reg, gphy->u2phy_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + + return ret; +} + +static int google_usb2_phy_exit(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D to_google_usb_phy(inst); + u32 reg; + + dev_dbg(gphy->dev, "exiting usb2 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + reg =3D readl(gphy->u2phy_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + reg &=3D ~USBCS_USB2PHY_CFG21_PHY_ENABLE; + writel(reg, gphy->u2phy_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + + reset_control_assert(inst->rsts); + clk_bulk_disable_unprepare(inst->num_clks, inst->clks); + + return 0; +} + +static const struct phy_ops google_usb2_phy_ops =3D { + .init =3D google_usb2_phy_init, + .exit =3D google_usb2_phy_exit, +}; + +static struct phy *google_usb_phy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct google_usb_phy *gphy =3D dev_get_drvdata(dev); + + if (args->args[0] >=3D GOOGLE_USB_PHY_NUM) { + dev_err(dev, "invalid PHY index requested from DT\n"); + return ERR_PTR(-ENODEV); + } + return gphy->insts[args->args[0]].phy; +} + +static int google_usb_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct google_usb_phy *gphy; + struct phy *phy; + struct google_usb_phy_instance *inst; + struct phy_provider *phy_provider; + struct typec_switch_desc sw_desc =3D { }; + int ret; + + gphy =3D devm_kzalloc(dev, sizeof(*gphy), GFP_KERNEL); + if (!gphy) + return -ENOMEM; + + dev_set_drvdata(dev, gphy); + gphy->dev =3D dev; + + ret =3D devm_mutex_init(dev, &gphy->phy_mutex); + if (ret) + return ret; + + gphy->u2phy_cfg_base =3D devm_platform_ioremap_resource_byname(pdev, + "u2phy_cfg"); + if (IS_ERR(gphy->u2phy_cfg_base)) + return dev_err_probe(dev, PTR_ERR(gphy->u2phy_cfg_base), + "invalid usb2 cfg\n"); + + gphy->dp_top_base =3D devm_platform_ioremap_resource_byname(pdev, + "dp_top"); + if (IS_ERR(gphy->dp_top_base)) + return dev_err_probe(dev, PTR_ERR(gphy->dp_top_base), + "invalid dp top\n"); + + inst =3D &gphy->insts[GOOGLE_USB2_PHY]; + inst->index =3D GOOGLE_USB2_PHY; + phy =3D devm_phy_create(dev, NULL, &google_usb2_phy_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), + "failed to create usb2 phy instance\n"); + inst->phy =3D phy; + phy_set_drvdata(phy, inst); + ret =3D devm_clk_bulk_get_all_enabled(dev, &inst->clks); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get u2 phy clks\n"); + inst->num_clks =3D ret; + + inst->rsts =3D devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(inst->rsts)) + return dev_err_probe(dev, PTR_ERR(inst->rsts), + "failed to get u2 phy resets\n"); + + phy_provider =3D devm_of_phy_provider_register(dev, google_usb_phy_xlate); + if (IS_ERR(phy_provider)) + return dev_err_probe(dev, PTR_ERR(phy_provider), + "failed to register phy provider\n"); + + pm_runtime_enable(dev); + + sw_desc.fwnode =3D dev_fwnode(dev); + sw_desc.drvdata =3D gphy; + sw_desc.name =3D fwnode_get_name(dev_fwnode(dev)); + sw_desc.set =3D google_usb_set_orientation; + + gphy->sw =3D typec_switch_register(dev, &sw_desc); + if (IS_ERR(gphy->sw)) + return dev_err_probe(dev, PTR_ERR(gphy->sw), + "failed to register typec switch\n"); + + return 0; +} + +static void google_usb_phy_remove(struct platform_device *pdev) +{ + struct google_usb_phy *gphy =3D dev_get_drvdata(&pdev->dev); + + typec_switch_unregister(gphy->sw); + pm_runtime_disable(&pdev->dev); +} + +static const struct of_device_id google_usb_phy_of_match[] =3D { + { + .compatible =3D "google,gs5-usb-phy", + }, + { } +}; +MODULE_DEVICE_TABLE(of, google_usb_phy_of_match); + +static struct platform_driver google_usb_phy =3D { + .probe =3D google_usb_phy_probe, + .remove =3D google_usb_phy_remove, + .driver =3D { + .name =3D "google-usb-phy", + .of_match_table =3D google_usb_phy_of_match, + } +}; + +module_platform_driver(google_usb_phy); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Google USB phy driver"); --=20 2.51.0.858.gf9c4a03a3a-goog