From nobody Sun Feb 8 17:43:46 2026 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E39612EA754 for ; Fri, 17 Oct 2025 23:35:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760744121; cv=none; b=Am5jR9asjcUrJXd63w+kExd4P8kfVgKwW8VUZuakiQsrviXfjgRAFRc9hVaseLlmFGzMN1ZGk9Kt9L0jiyhyAi1A7Ol28cAWaQIaB0V4s5G9dhHDNHz6EB5TJyzuLzXXyB70+A0fY38twCEsr/CS2KFZLDMCOVuTHD0eDYZzdz8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760744121; c=relaxed/simple; bh=S4DZWBuogJeYEeIqrhKi2NwzW+diVLjfguDpEobWolc=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=CBVwk9bbMpE4rPr1G3mhQuYT8eHjbwaMySoKwkOq/p+1LwVEd8j6cnAsbUSWoJyq+MKxW/KP7q2MlXvY6Evk8XuTjp/Cc3oKGrDgHaCaJlo0vz1JcVIqlRIFCm0/oyy2hIBoupqOO6P6hDIXbA39kb7774o03IlhbvYH9z/p97s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--royluo.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=T0Dug21R; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--royluo.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="T0Dug21R" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-336b9f3b5b0so2627326a91.3 for ; Fri, 17 Oct 2025 16:35:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1760744118; x=1761348918; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=uBtgf5vnEXmLQ0VM1QPw2ajUDmPAziTO20ovX0Hz/e4=; b=T0Dug21RBPacxuq9zoJRSUX0mjl+I0dwFbMLfFlo3Tu6F+8y9ItQuPXUksc1tuQwkG zxLCcwLkvbIA6Coh5hu4KF2bcD3ZSCHWWKLNG5C2jlXunxnS49AqV+4vOFM9nRD3tuwN zjYTvQUkDgtbK0rBkwXzbsm0E4xUA+3HJ/cXPb0k0TdXxcRGqDx4fRtAl6Iihy0cIy+R BZaWLS2OziWXrP6CkoFwArOvA44EmQrU1lgeQ8/E7b1YsMtDK8E4KaYRgZqw0UYh3OQ6 paDUJ+eOtZhYE2TNPPXsuUxKG351Wmj9hd381uLIkcMUddRNJsfbNb/rW8MC7oJvyQ3h ZLiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760744118; x=1761348918; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=uBtgf5vnEXmLQ0VM1QPw2ajUDmPAziTO20ovX0Hz/e4=; b=Z6xw0sJi3Y3N3LYDCv0M9HCmTUTDsGXa1BuP7YBCs8Jpcw0AQ/0dab2z+fcgOX/PLP KnDEW70E1+TZYZ6kndrMRxvi7fzXXVENo1BD8q8jhn5gggtHdbcnVLl009kfWGqGjhsG yrI00zOzN5ZJfa73F+Pak0ntYSsAOuafKqwMgNPKYn0x+bbet5wk2jTXDQbOT0qKrN85 W2E+0vbkHRw//NG1prEAosOaHi0gFDhMS5wT8wWb/kHbLCUNV7+qeyX/jOqgII8e7oYE jQ7SRzHPDDbQYHIg7WXVNxQ6GNAZbDGR2E9qVKgFlvM5Ehog6LKnLM5PcXKscyH6DvGL O7/w== X-Forwarded-Encrypted: i=1; AJvYcCVTRgNIO2gUST5UKp4agmsd9T6jbF8mxkEG+VPadKN+e1ZlPnGkcZHOmTcxTorwNxwRrCe653G1o7OO5Ng=@vger.kernel.org X-Gm-Message-State: AOJu0YzU9UKoKwGou/PI2OOQKQkPbWo0w53oLqZMZcU/EXR857q2IB19 nvpYSbfDbFZPapn9MQnAT9hsjriGfSHUBJhXd2oLPMoSsm6TCDPVHvt13/EcjYP943efzWBc3ec nwTFZIA== X-Google-Smtp-Source: AGHT+IFhiZ7zlyGtCjXNqejcRcaQZDSmUdfiNBTRmnq1ief791h4f8sHMX2o8msPyY/DXfgtDuAuhD1mh/U= X-Received: from pjbsj14.prod.google.com ([2002:a17:90b:2d8e:b0:33b:cfa0:dd8a]) (user=royluo job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:3144:b0:335:2b86:f319 with SMTP id 98e67ed59e1d1-33bcf919094mr7035036a91.35.1760744118117; Fri, 17 Oct 2025 16:35:18 -0700 (PDT) Date: Fri, 17 Oct 2025 23:34:58 +0000 In-Reply-To: <20251017233459.2409975-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251017233459.2409975-1-royluo@google.com> X-Mailer: git-send-email 2.51.0.858.gf9c4a03a3a-goog Message-ID: <20251017233459.2409975-2-royluo@google.com> Subject: [PATCH v4 1/2] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3 From: Roy Luo To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , Badhri Jagan Sridharan , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the device tree bindings for the DWC3 USB controller found in Google Tensor SoCs, starting with the G5 generation. The Tensor G5 silicon represents a complete architectural departure from previous generations (like gs101), including entirely new clock/reset schemes, top-level wrapper and register interface. Consequently, existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating this new device tree binding. The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features Dual-Role Device single port with hibernation support. Signed-off-by: Roy Luo Reviewed-by: Krzysztof Kozlowski --- .../bindings/usb/google,gs5-dwc3.yaml | 135 ++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/google,gs5-dwc3.y= aml diff --git a/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml b/D= ocumentation/devicetree/bindings/usb/google,gs5-dwc3.yaml new file mode 100644 index 000000000000..09756bf6fd3c --- /dev/null +++ b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2025, Google LLC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/google,gs5-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Tensor Series (G5+) DWC3 USB SoC Controller + +maintainers: + - Roy Luo + +description: + Describes the DWC3 USB controller block implemented on Google Tensor SoC= s, + starting with the G5 generation. Based on Synopsys DWC3 IP, the controll= er + features Dual-Role Device single port with hibernation add-on. + +properties: + compatible: + const: google,gs5-dwc3 + + reg: + items: + - description: Core DWC3 IP registers. + - description: USB host controller configuration registers. + - description: USB custom interrrupts control registers. + + reg-names: + items: + - const: dwc3_core + - const: host_cfg + - const: usbint_cfg + + interrupts: + items: + - description: Core DWC3 interrupt. + - description: High speed power management event for remote wakeup. + - description: Super speed power management event for remote wakeup. + + interrupt-names: + items: + - const: core + - const: hs_pme + - const: ss_pme + + clocks: + items: + - description: Non-sticky module clock. + - description: Sticky module clock. + + clock-names: + items: + - const: non_sticky + - const: sticky + + resets: + items: + - description: Non-sticky module reset. + - description: Sticky module reset. + - description: DRD bus reset. + - description: Top-level reset. + + reset-names: + items: + - const: non_sticky + - const: sticky + - const: drd_bus + - const: top + + power-domains: + items: + - description: Power switchable domain, the child of top domain. + Turning it on puts the controller into full power state, + turning it off puts the controller into power gated state. + - description: Top domain, the parent of power switchable domain. + Turning it on puts the controller into power gated state, + turning it off completely shuts off the controller. + + power-domain-names: + items: + - const: psw + - const: top + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - power-domain-names + +allOf: + - $ref: snps,dwc3-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + usb@c400000 { + compatible =3D "google,gs5-dwc3"; + reg =3D <0 0x0c400000 0 0xd060>, <0 0x0c450000 0 0x14>, <0 0x= 0c450020 0 0x43>; + reg-names =3D "dwc3_core", "host_cfg", "usbint_cfg"; + interrupts =3D , + , + ; + interrupt-names =3D "core", "hs_pme", "ss_pme"; + clocks =3D <&hsion_usbc_non_sticky_clk>, <&hsion_usbc_sticky_= clk>; + clock-names =3D "non_sticky", "sticky"; + resets =3D <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usb= c_sticky>, + <&hsion_resets_usb_drd_bus>, <&hsion_resets_usb_top>; + reset-names =3D "non_sticky", "sticky", "drd_bus", "top"; + power-domains =3D <&hsio_n_usb_psw>, <&hsio_n_usb>; + power-domain-names =3D "psw", "top"; + phys =3D <&usb_phy 0>; + phy-names =3D "usb2-phy"; + snps,quirk-frame-length-adjustment =3D <0x20>; + snps,gfladj-refclk-lpm-sel-quirk; + snps,incr-burst-type-adjustment =3D <4>; + }; + }; +... --=20 2.51.0.858.gf9c4a03a3a-goog