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charset="utf-8" On SAR2130P QXR Platform, the CC Lines are inverted and the lane programming is to be done reverse compared to other targets. As per the HW specifics, Bit-2 of TYPEC_CTRL register indicates port select polarity. This bit is to be set for SAR2130P. Signed-off-by: Krishna Kurapati Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 7b5af30f1d02..813c88f0a16f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -60,6 +60,7 @@ /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ #define SW_PORTSELECT_VAL BIT(0) #define SW_PORTSELECT_MUX BIT(1) +#define INVERT_CC_POLARITY BIT(2) =20 #define PHY_INIT_COMPLETE_TIMEOUT 10000 =20 @@ -1820,6 +1821,7 @@ struct qmp_phy_cfg { /* Offset from PCS to PCS_USB region */ unsigned int pcs_usb_offset; =20 + bool invert_cc_polarity; }; =20 struct qmp_combo { @@ -2010,6 +2012,7 @@ static const struct qmp_phy_cfg sar2130p_usb3dpphy_cf= g =3D { .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .invert_cc_polarity =3D true, }; =20 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg =3D { @@ -3046,6 +3049,10 @@ static int qmp_combo_com_init(struct qmp_combo *qmp,= bool force) val =3D SW_PORTSELECT_MUX; if (qmp->orientation =3D=3D TYPEC_ORIENTATION_REVERSE) val |=3D SW_PORTSELECT_VAL; + + if (cfg->invert_cc_polarity) + val |=3D INVERT_CC_POLARITY; + writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); =20 switch (qmp->qmpphy_mode) { --=20 2.34.1