From nobody Fri Dec 19 20:54:30 2025 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C071E33290A for ; Fri, 17 Oct 2025 15:19:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760714353; cv=none; b=tuii0s1PX0bCzYNKR2KmYPfqJGSaYkKSTjqBjY18w7Ux6DtHb0aHTM3wskiTc8/HT53Ckdp05/JfQhVExcmgQz/hHIlQB+xJYEcX/+iLY6sVrz7AL/rS587S/DC02XDqJ+uD+cQ0tY7eN3wgkZANMwCEp/6IFdL7Q3P9krgdwzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760714353; c=relaxed/simple; bh=Y3zs+7EWEpEspMjXG/tv7lz3qsoFqxSawHyRTh14OuU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ogcYmYYDAk6SQFCDF6PfamvQWw0b6Yi0K++aKI4CZ8GZxhEsNMjyBuxCT684F+i1vtSS7Q2F8/SAGC5rPIKmNce06ldE2yKzbYXAVwPE+n2LGVTQaRNtL8/SUC4lH5mFW84EiV/xS6iI+3avspYXRjGkyk9gX5qhVkHoSTTsFNM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=cEB+lmEg; arc=none smtp.client-ip=209.85.210.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cEB+lmEg" Received: by mail-pf1-f179.google.com with SMTP id d2e1a72fcca58-7835321bc98so1999666b3a.2 for ; Fri, 17 Oct 2025 08:19:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1760714351; x=1761319151; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eJTkF6pHkRbGTiu8sME46LOjNVi5j+piyfVUn5/1Bzo=; b=cEB+lmEg8kNIvbXTdD56Ue+49eRAmYxVRZToWjjebKvwZzhm3ViLKMyMM/XmZmtiQO QgNw7MSXaCSvokm6j8FkU0rrYH2llMjyHCubBPnkTx6wNZ45iMQwwpH0/EUyOogHPVeA rPB7BZB+EjGFdVzi/vVxZuGtojcYDJCCLsZhUgZvrrAJd4Aom7H54lBvistq1o4Ba1CO TNDf18lKqjatfmKnQtxGekDrtDgT6o3lsL1an0rTaN0NOJoRw7cNDpgPwJxKVjEYkdYL VhrLxOayJIflwyjLEAf/dlKzFq34rzwgMF00mGN9jli0oJVk9CQAP8tYXQVrosxd+Hdr F7Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760714351; x=1761319151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eJTkF6pHkRbGTiu8sME46LOjNVi5j+piyfVUn5/1Bzo=; b=CnE3g7ZURg88N6s8LsKTFgs4QwgEiP3pU6byEPdgrernmmEEC6wP4YirnR6ocUAHzK Ztp+u30ET/stXPcVwmsyJVeAxdwDhxn70Wv9oMfvvSLJDRT/e9nsa9SW5y5Jha7q5yO9 7/cHdJgQ+fiOvVHW7Nb1/1a79f5VCa56LahvDm9h75LA1FKsQoltgUbWWqNF3oV5ZZmY u1AQMy/maiSizWAaNyyLAxICmZAdAm7/Sso98UQYXaY8VcJLKdmMtaj06LFW35Dahl3M uZhtUyaxbmMFPHKufGBxWuFCWKMwlhcBNIeyG5GNEHwIXRpLGWBlwNX+Kxnc4VI1dzCq aPoA== X-Forwarded-Encrypted: i=1; AJvYcCUZNnvM+rUlVcx43LfLS65YR3fFoHCnT6Y98ny6GJX2I0qE3rWf//NMVvtZ8lAfBeJGvn2NoMmGHd/31/I=@vger.kernel.org X-Gm-Message-State: AOJu0YwWQ5ENTVFJ73t8HxcYYF4Ygt1MEKH4au4YoHzqbOM/8iGg9q83 xVLvhFqe/mbkoSyg8v7Lw7k/f4lw3CAH1hwg63pS3NtWzCubR7xqZLYS X-Gm-Gg: ASbGnct1RjzzH/IJLtQQ7WAKH0NejRYVeGcUsjym/EtoMsvYkk0jn8VGZnzBzfGl/Og y8/rNJPdvGsQbdhzNHgR6Dcpv+jW0SgDweFDlJmEHUmVrORSAv5zUupWrmGWv5kvdTmEJ/gGCkv c4TGc7JNqn/YMwase5f0aSVmK5u+I/KeARtotqrI3dHS4qEUKK8By3IlR5yx+rMrjKO7hPvx8rA luw4SEwHrxpTF8t+CbCm6Ueu5dyXsQ3y/ck1Q8yBmFB8qBPq/80Xr/z/zJkitCKu6QYX2zxbvW5 G8UTeI5FXkfsw9rpuLEGruKkvJAYGYJpwO71CJO7jwGjvV56FVWeKmGsseVGKE6qiHmutQE1Cbb cVsxOAoRmBuN4bOJHe8lwWeepoU59M9eM1Pwo1hKOQe+m1tHgrXnZypjBwuXnMBmfT6TIkFYE+9 exSClTaGMESuZYTZ51MxOG8w== X-Google-Smtp-Source: AGHT+IHOFgRPcJ1MQt4p4gojjUhnLxP/yD+ItR7pcwk09VIMA1XE/ri3q0HvKCSg10K8XvkIfs+w3w== X-Received: by 2002:a17:903:1a4c:b0:267:ba92:4d19 with SMTP id d9443c01a7336-290c99a8ed3mr52578495ad.0.1760714350743; Fri, 17 Oct 2025 08:19:10 -0700 (PDT) Received: from iku.. ([2401:4900:1c07:c7d3:fdc9:5e8f:28db:7f80]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2909930a756sm67193955ad.14.2025.10.17.08.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Oct 2025 08:19:10 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Niklas=20S=C3=B6derlund?= , Paul Barker , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Geert Uytterhoeven , Mitsuhiro Kimura Cc: netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar , stable@vger.kernel.org, =?UTF-8?q?Niklas=20S=C3=B6derlund?= Subject: [PATCH v2 1/4] net: ravb: Make DBAT entry count configurable per-SoC Date: Fri, 17 Oct 2025 16:18:27 +0100 Message-ID: <20251017151830.171062-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251017151830.171062-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251017151830.171062-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Lad Prabhakar The number of CDARq (Current Descriptor Address Register) registers is not fixed to 22 across all SoC variants. For example, the GBETH implementation uses only two entries. Hardcoding the value leads to incorrect resource allocation on such platforms. Pass the DBAT entry count through the per-SoC hardware info struct and use it during probe instead of relying on a fixed constant. This ensures correct descriptor table sizing and initialization across different SoCs. Fixes: feab85c7ccea ("ravb: Add support for RZ/G2L SoC") Cc: stable@vger.kernel.org Signed-off-by: Lad Prabhakar Reviewed-by: Niklas S=C3=B6derlund --- v1->v2: - Added Reviewed-by tag from Niklas. --- drivers/net/ethernet/renesas/ravb.h | 2 +- drivers/net/ethernet/renesas/ravb_main.c | 9 +++++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/ren= esas/ravb.h index 7b48060c250b..d65cd83ddd16 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -1017,7 +1017,6 @@ enum CSR2_BIT { #define CSR2_CSUM_ENABLE (CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4 | \ CSR2_RTCP6 | CSR2_RUDP6 | CSR2_RICMP6) =20 -#define DBAT_ENTRY_NUM 22 #define RX_QUEUE_OFFSET 4 #define NUM_RX_QUEUE 2 #define NUM_TX_QUEUE 2 @@ -1062,6 +1061,7 @@ struct ravb_hw_info { u32 rx_max_frame_size; u32 rx_buffer_size; u32 rx_desc_size; + u32 dbat_entry_num; unsigned aligned_tx: 1; unsigned coalesce_irqs:1; /* Needs software IRQ coalescing */ =20 diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/etherne= t/renesas/ravb_main.c index 9d3bd65b85ff..69d382e8757d 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2694,6 +2694,7 @@ static const struct ravb_hw_info ravb_gen2_hw_info = =3D { .rx_buffer_size =3D SZ_2K + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), .rx_desc_size =3D sizeof(struct ravb_ex_rx_desc), + .dbat_entry_num =3D 22, .aligned_tx =3D 1, .gptp =3D 1, .nc_queues =3D 1, @@ -2717,6 +2718,7 @@ static const struct ravb_hw_info ravb_gen3_hw_info = =3D { .rx_buffer_size =3D SZ_2K + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), .rx_desc_size =3D sizeof(struct ravb_ex_rx_desc), + .dbat_entry_num =3D 22, .internal_delay =3D 1, .tx_counters =3D 1, .multi_irqs =3D 1, @@ -2743,6 +2745,7 @@ static const struct ravb_hw_info ravb_gen4_hw_info = =3D { .rx_buffer_size =3D SZ_2K + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), .rx_desc_size =3D sizeof(struct ravb_ex_rx_desc), + .dbat_entry_num =3D 22, .internal_delay =3D 1, .tx_counters =3D 1, .multi_irqs =3D 1, @@ -2769,6 +2772,7 @@ static const struct ravb_hw_info ravb_rzv2m_hw_info = =3D { .rx_buffer_size =3D SZ_2K + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), .rx_desc_size =3D sizeof(struct ravb_ex_rx_desc), + .dbat_entry_num =3D 22, .multi_irqs =3D 1, .err_mgmt_irqs =3D 1, .gptp =3D 1, @@ -2794,6 +2798,7 @@ static const struct ravb_hw_info gbeth_hw_info =3D { .rx_max_frame_size =3D SZ_8K, .rx_buffer_size =3D SZ_2K, .rx_desc_size =3D sizeof(struct ravb_rx_desc), + .dbat_entry_num =3D 2, .aligned_tx =3D 1, .coalesce_irqs =3D 1, .tx_counters =3D 1, @@ -3025,7 +3030,7 @@ static int ravb_probe(struct platform_device *pdev) ravb_parse_delay_mode(np, ndev); =20 /* Allocate descriptor base address table */ - priv->desc_bat_size =3D sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; + priv->desc_bat_size =3D sizeof(struct ravb_desc) * info->dbat_entry_num; priv->desc_bat =3D dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_si= ze, &priv->desc_bat_dma, GFP_KERNEL); if (!priv->desc_bat) { @@ -3035,7 +3040,7 @@ static int ravb_probe(struct platform_device *pdev) error =3D -ENOMEM; goto out_rpm_put; } - for (q =3D RAVB_BE; q < DBAT_ENTRY_NUM; q++) + for (q =3D RAVB_BE; q < info->dbat_entry_num; q++) priv->desc_bat[q].die_dt =3D DT_EOS; =20 /* Initialise HW timestamp list */ --=20 2.43.0 From nobody Fri Dec 19 20:54:30 2025 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D37AD3328F2 for ; Fri, 17 Oct 2025 15:19:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([2401:4900:1c07:c7d3:fdc9:5e8f:28db:7f80]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2909930a756sm67193955ad.14.2025.10.17.08.19.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Oct 2025 08:19:24 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Niklas=20S=C3=B6derlund?= , Paul Barker , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Geert Uytterhoeven , Mitsuhiro Kimura Cc: netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar , stable@vger.kernel.org, =?UTF-8?q?Niklas=20S=C3=B6derlund?= Subject: [PATCH v2 2/4] net: ravb: Allocate correct number of queues based on SoC support Date: Fri, 17 Oct 2025 16:18:28 +0100 Message-ID: <20251017151830.171062-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251017151830.171062-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251017151830.171062-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Lad Prabhakar On SoCs that only support the best-effort queue and not the network control queue, calling alloc_etherdev_mqs() with fixed values for TX/RX queues is not appropriate. Use the nc_queues flag from the per-SoC match data to determine whether the network control queue is available, and fall back to a single TX/RX queue when it is not. This ensures correct queue allocation across all supported SoCs. Fixes: a92f4f0662bf ("ravb: Add nc_queue to struct ravb_hw_info") Cc: stable@vger.kernel.org Signed-off-by: Lad Prabhakar Reviewed-by: Niklas S=C3=B6derlund --- v1->v2: - Added Reviewed-by tag from Niklas. --- drivers/net/ethernet/renesas/ravb_main.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/etherne= t/renesas/ravb_main.c index 69d382e8757d..a200e205825a 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2926,13 +2926,14 @@ static int ravb_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(rstc), "failed to get cpg reset\n"); =20 + info =3D of_device_get_match_data(&pdev->dev); + ndev =3D alloc_etherdev_mqs(sizeof(struct ravb_private), - NUM_TX_QUEUE, NUM_RX_QUEUE); + info->nc_queues ? NUM_TX_QUEUE : 1, + info->nc_queues ? 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([2401:4900:1c07:c7d3:fdc9:5e8f:28db:7f80]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2909930a756sm67193955ad.14.2025.10.17.08.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Oct 2025 08:19:35 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Niklas=20S=C3=B6derlund?= , Paul Barker , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Geert Uytterhoeven , Mitsuhiro Kimura Cc: netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar , stable@vger.kernel.org Subject: [PATCH v2 3/4] net: ravb: Enforce descriptor type ordering Date: Fri, 17 Oct 2025 16:18:29 +0100 Message-ID: <20251017151830.171062-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251017151830.171062-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251017151830.171062-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Ensure the TX descriptor type fields are published in a safe order so the DMA engine never begins processing a descriptor chain before all descriptor fields are fully initialised. For multi-descriptor transmits the driver writes DT_FEND into the last descriptor and DT_FSTART into the first. The DMA engine begins processing when it observes DT_FSTART. Move the dma_wmb() barrier so it executes immediately after DT_FEND and immediately before writing DT_FSTART (and before DT_FSINGLE in the single-descriptor case). This guarantees that all prior CPU writes to the descriptor memory are visible to the device before DT_FSTART is seen. This avoids a situation where compiler/CPU reordering could publish DT_FSTART ahead of DT_FEND or other descriptor fields, allowing the DMA to start on a partially initialised chain and causing corrupted transmissions or TX timeouts. Such a failure was observed on RZ/G2L with an RT kernel as transmit queue timeouts and device resets. Fixes: 2f45d1902acf ("ravb: minimize TX data copying") Cc: stable@vger.kernel.org Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Niklas S=C3=B6derlund --- v1->v2: - Reflowed the code and updated the comment to clarify the ordering requirements. - Updated commit message. - Split up adding memory barrier change before ringing doorbell into a separate patch. --- drivers/net/ethernet/renesas/ravb_main.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/etherne= t/renesas/ravb_main.c index a200e205825a..0e40001f64b4 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2211,13 +2211,25 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *= skb, struct net_device *ndev) =20 skb_tx_timestamp(skb); } - /* Descriptor type must be set after all the above writes */ - dma_wmb(); + if (num_tx_desc > 1) { desc->die_dt =3D DT_FEND; desc--; + /* When using multi-descriptors, DT_FEND needs to get written + * before DT_FSTART, but the compiler may reorder the memory + * writes in an attempt to optimize the code. + * Use a dma_wmb() barrier to make sure DT_FEND and DT_FSTART + * are written exactly in the order shown in the code. + * This is particularly important for cases where the DMA engine + * is already running when we are running this code. If the DMA + * sees DT_FSTART without the corresponding DT_FEND it will enter + * an error condition. + */ + dma_wmb(); desc->die_dt =3D DT_FSTART; } else { + /* Descriptor type must be set after all the above writes */ + dma_wmb(); desc->die_dt =3D DT_FSINGLE; } ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); --=20 2.43.0 From nobody Fri Dec 19 20:54:30 2025 Received: from mail-pg1-f172.google.com (mail-pg1-f172.google.com [209.85.215.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34C0D32C94B for ; Fri, 17 Oct 2025 15:19:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760714394; cv=none; b=gn0WPMQQuVVI1hkYKmPTzixIVl0NZHRkvl2bJqs/qI1I4P6NEC8N2YNRPcsL5oQcTRK+Mn1b2pCYmnENDUXHElqXvCWGT1nyj4QqlYec7vgk1UF6dp4TRDTfAH/f3yxveq/QpmkSzeKu7uOnV3Zz1rcpt11dZTa5hVn79A8tEko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760714394; c=relaxed/simple; bh=7Ap1yiV2IvW5TscRyVekKp/pYADoMM25JQW9IdJTVB0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=q1HH8vRW/v8Y3N2nJ+gG99ppSfGnf0H7qdtKU70ZlSLl2ai9fMH8NFJHliZPDzfwGBx8NqCvihtPm+9eLJ/IWp8BakBlrcNWuLo4SYgwy4++lpx8gJd1vu30GEz7Tcavj1Gr1y3w4aWPCrDkSRrLEjBKL2PfeMj2P6+qizacgN0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hNOIULam; arc=none smtp.client-ip=209.85.215.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hNOIULam" Received: by mail-pg1-f172.google.com with SMTP id 41be03b00d2f7-b4fb8d3a2dbso1496789a12.3 for ; Fri, 17 Oct 2025 08:19:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1760714392; x=1761319192; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KXVefTb39Nse0uy+Bbk9GELviGijLUlE6DvoOutRIgk=; b=hNOIULamp4llWnj7/SyBAffjMi+1LQK5HtQ+YNgIcHDB/JEWGc14K74B8GXWT6ZoKN +5i83W9/K8xFvfeA41QhF3UH1A+sRfnN7uZcvXC0TUvgvSiPhWv9V2QykJ3O83PYXMeL lI+tOzMjL3RUKu8tqQPEPKumLlp+T9QKz23kZeoU7B9wndniCqxekdL/yLMzWuexvXal Izm2ailEk3hgE0Sx2wPJ9UYRs/BD4XLTAR81/IfS4dsasEry6sIaPaXIHfjSojtPeTa0 wbplohLXO2HaFha+EnLS8sxtIHS3YBTDbXs48hdGVyhLXK0CzhwIU9NYfzIxP2Yt3Y98 9gkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760714392; x=1761319192; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KXVefTb39Nse0uy+Bbk9GELviGijLUlE6DvoOutRIgk=; b=h8uhWdW1PohXjHBLv7to4SP8zpe5vnWpy0p6J/P+6eGFuPU+MME2oTiZ3z8sHWC/CX VG9UZ4XjdEvY/J2NiRDPuvyLK+l5TWcGFu+Qbz2lbNay7R6MBiX1RnhVS0XVbZFi/+0z K4qUgXvGnuNGkdvwtzjqNOD6BrkgVGIaCTQ0nssklyDGnCJj5JPsIBXfhJlV9e88wmkt Dfurn6ryKx0dbd08ZcW1BZhtM5iMFwkvlQZjJ+0/g4+2R6q0RCczp/kKkZD0/kXdOqfm zTzZamFVgxFYB4f6grxd6Dtb22SEKQu3DdwtKRFVPT8un+jQE3FwR9+OKCxf4zvgRvtF 9FDA== X-Forwarded-Encrypted: i=1; AJvYcCXO9miW9X32AN6Iaofxe3y2/fnzSQFjoFsLqgnN1amRfm6Hvwm++6yYgFrWORcIQseZ8vGcTLl3ZNCb8bQ=@vger.kernel.org X-Gm-Message-State: AOJu0YwbqAqZ9E0XjpKbX1kqWzFgYEgQolOmZ8w92i09yQF+7mAMqZf/ VBHcGe4Vh6kBYLD5x+WYrFrisisMfFSTa6XXpeT1xKjUBYD/D+Ec19sp X-Gm-Gg: ASbGnctHYQ+B91KRlX0YXyT+jJvsRbva0p892gv2emoeLebh7bBIuxi1JEcso4Y2Gmm NV3RcOQRqVKaKCNZ4BbQ6MdEXVP53xf/s3S5b9wJoggVxR9Be9LYVowQlPPhuF23punx4Xv9lnt oNbOzm7KVxLiYpDEZqbnU9kccK3sD22+CiNnOJOFVKJggnY15lritYexdJQOE/muliKvzknDejN /IAoS2wi85WTCUGDzC1bVb8gKvzqBE4I9aS00xgPY4cQLg024dhBNIsO/zBlvDMxb+1r2bpVr9J QUIVKeOd4e5XHeX4G9EnQIcX65gC3gtjStjdVwgHvLGVAhPiKfWuozF/6GHB7vDTC3tKD6hL+x4 O69i54qo/SZ+mSFxva0gij/jm+Dpd4zA/LZl/pyWcbnfAblvq7WKXBGHXcK/E0WHduDXvzirShd tLubxfIWAfMNMZVHILA3vSMhjZv24G9L6+ X-Google-Smtp-Source: AGHT+IHyIi9hV84N2xKmSAprgzQAB1rjUdqIYAvzNOIv45BdiAJRGsffALu2EyeoAjWoG6N3Yyv0/A== X-Received: by 2002:a17:902:e88e:b0:290:9332:eed1 with SMTP id d9443c01a7336-290ca12153emr45972955ad.34.1760714392396; Fri, 17 Oct 2025 08:19:52 -0700 (PDT) Received: from iku.. ([2401:4900:1c07:c7d3:fdc9:5e8f:28db:7f80]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2909930a756sm67193955ad.14.2025.10.17.08.19.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Oct 2025 08:19:51 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Niklas=20S=C3=B6derlund?= , Paul Barker , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Geert Uytterhoeven , Mitsuhiro Kimura Cc: netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar , stable@vger.kernel.org Subject: [PATCH v2 4/4] net: ravb: Ensure memory write completes before ringing TX doorbell Date: Fri, 17 Oct 2025 16:18:30 +0100 Message-ID: <20251017151830.171062-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251017151830.171062-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251017151830.171062-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add a final dma_wmb() barrier before triggering the transmit request (TCCR_TSRQ) to ensure all descriptor and buffer writes are visible to the DMA engine. According to the hardware manual, a read-back operation is required before writing to the doorbell register to guarantee completion of previous writes. Instead of performing a dummy read, a dma_wmb() is used to both enforce the same ordering semantics on the CPU side and also to ensure completion of writes. Fixes: c156633f1353 ("Renesas Ethernet AVB driver proper") Cc: stable@vger.kernel.org Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Niklas S=C3=B6derlund --- v1->v2: - New patch added to separate out the memory barrier change before ringing the doorbell. --- drivers/net/ethernet/renesas/ravb_main.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/etherne= t/renesas/ravb_main.c index 0e40001f64b4..c3fc15f9ec85 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2232,6 +2232,14 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *s= kb, struct net_device *ndev) dma_wmb(); desc->die_dt =3D DT_FSINGLE; } + + /* Before ringing the doorbell we need to make sure that the latest + * writes have been committed to memory, otherwise it could delay + * things until the doorbell is rang again. + * This is in replacement of the read operation mentioned in the HW + * manuals. + */ + dma_wmb(); ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); =20 priv->cur_tx[q] +=3D num_tx_desc; --=20 2.43.0