From nobody Mon Feb 9 16:35:23 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C518C4409; Fri, 17 Oct 2025 08:47:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760690838; cv=none; b=ibYZB/Uw+zmtKqamym2pff912Fe5kG0mO8DwtWPSN4J2cUNrlrQluMphls1Z+l1CvDSL/eHxr9DbD51B8KHXyw3bU4h0UmBSyWu/PCSx8lc68z5VZH/BxQ2juiX7ovd/MvP1gOINx0pYfW2mwCIyrSCntFr8Rq+ohGd7YgzfXKQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760690838; c=relaxed/simple; bh=yFQTGTsJVgWifl/ze/wbN/sUXL+l/jdq83GYwD97hto=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rGWfDaMDliR5hh0EI02ckNGIa+u2kFbSNRwfXbk5jXNwiXQ3OpDI34O87LTjtgaiAMqFQx+rpLYqbPuJOpuKi6GgaklJiInhJU446u/SMz2a7+XAfT6h4zn/ILUDRCQlzHI8CJwclqcgDvtUAapWVGHEwS33LpJl3hd2y4RIphg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=UezZHLE7; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="UezZHLE7" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 59H8l2Xg2228024; Fri, 17 Oct 2025 03:47:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1760690822; bh=2g/xZ+WFWVpJAkWMeTL4jcYilwFGoe++/3I8lL1RR2I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UezZHLE7UDV1NxYQo/rUY8qk7bKpUF9kTvQB7UcOO/OcDwrz64vnmtX6TO+v6NGYv HOXSi37W64hxPi7meaa0gK2kWt0LJexrNbAw2r70mxGEjyAjJRr5FVVA+/nmiqACG1 s0xsDQ2lYlYpvd0X6tnanmVF0vgPjAe7RTEpYye0= Received: from DLEE202.ent.ti.com (dlee202.ent.ti.com [157.170.170.77]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 59H8l2CJ2271065 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 17 Oct 2025 03:47:02 -0500 Received: from DLEE203.ent.ti.com (157.170.170.78) by DLEE202.ent.ti.com (157.170.170.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 17 Oct 2025 03:47:02 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE203.ent.ti.com (157.170.170.78) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Fri, 17 Oct 2025 03:47:02 -0500 Received: from hp-z2-tower.dhcp.ti.com (hp-z2-tower.dhcp.ti.com [172.24.231.157]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59H8ktEU1019203; Fri, 17 Oct 2025 03:46:59 -0500 From: Hrushikesh Salunke To: , , , , , CC: , , , , Subject: [PATCH 1/3] arm64: dts: ti: k3-j784s4-evm-pcie0-pcie1-ep: Add boot phase tag to "pcie1_ep" Date: Fri, 17 Oct 2025 14:16:52 +0530 Message-ID: <20251017084654.2929945-2-h-salunke@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251017084654.2929945-1-h-salunke@ti.com> References: <20251017084654.2929945-1-h-salunke@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" J784S4 SoC has two instances of PCIe which are PCIe0 and PCIe1. J784S4 SoC uses PCIe1 instance for PCIe boot process. So it needs to be in endpoint mode and it needs to be functional at all stages of PCIe boot process. Thus add the "bootph-all" boot phase tag to "pcie1_ep" device tree node. Signed-off-by: Hrushikesh Salunke --- arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso b/arc= h/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso index 685305092bd8..22533d678f79 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso @@ -75,5 +75,6 @@ pcie1_ep: pcie-ep@2910000 { dma-coherent; phys =3D <&serdes0_pcie1_link>; phy-names =3D "pcie-phy"; + bootph-all; }; }; --=20 2.34.1 From nobody Mon Feb 9 16:35:23 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1644264A65; Fri, 17 Oct 2025 08:47:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760690839; cv=none; b=J0lNKPau35+cS2kfrnG4zfiLCu26y2nB99kPOIgIRvHPjnfSBOgEumtit9/Gng0Xfl1sPsPEIv69p4nhxIoCcoAXMHyD1smtjk0eRON2xaJuS/JJCky2Cp0+U5i3V0EFtt24yHPef46D5THJnXvD1PhYUjuP+/wcqYNPfXeZDEg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760690839; c=relaxed/simple; bh=Lr6lO2Ly1pchMPtN3FAdcZ+RhOF711iRdOqXbtdjkQs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YCqf137sz0oe44hPzlHP6T0kdqkto513ciLJP7FK6jaD3F4NOKFW7epQS3p9hzaDpgj/ykX7HotyobV4Pl84ziYJc0GE/9T2ZbgJ68HJmOclJ7dK0hYzTvCqCeJWx9YB4yLjsNHH1uZ0qHZ+HmfKA0KImYuF+CMkIBs9n0Q3/gI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=tIKmWjWW; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="tIKmWjWW" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 59H8l6Vm2228036; Fri, 17 Oct 2025 03:47:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1760690826; bh=UqonKPjynlzAg2tpJmTeutIHA66gcJm6tk1HkkdCnUA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tIKmWjWWPrckJpT6AP4BauHl1WV5i42Jm9Za7VygCcGFPo4A4DxSxTUCGGfYO0AoQ xxZUpEJKqm2s4lCnkJ1x0tqfSygCovRBdRpR0WvOx6IUYkidmMAkG4ke4g+1kofO72 yIdHYXdRJbGYkSPMxJQ4Ye3SkubSFWR7eisLCR4s= Received: from DLEE207.ent.ti.com (dlee207.ent.ti.com [157.170.170.95]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 59H8l6YA2271184 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 17 Oct 2025 03:47:06 -0500 Received: from DLEE213.ent.ti.com (157.170.170.116) by DLEE207.ent.ti.com (157.170.170.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 17 Oct 2025 03:47:05 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE213.ent.ti.com (157.170.170.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Fri, 17 Oct 2025 03:47:05 -0500 Received: from hp-z2-tower.dhcp.ti.com (hp-z2-tower.dhcp.ti.com [172.24.231.157]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59H8ktEV1019203; Fri, 17 Oct 2025 03:47:02 -0500 From: Hrushikesh Salunke To: , , , , , CC: , , , , Subject: [PATCH 2/3] arm64: dts: ti: k3-j784s4-j742s2-evm-common: Add bootph-all tag to SERDES0 Date: Fri, 17 Oct 2025 14:16:53 +0530 Message-ID: <20251017084654.2929945-3-h-salunke@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251017084654.2929945-1-h-salunke@ti.com> References: <20251017084654.2929945-1-h-salunke@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" J784S4 SoC has two instances of PCIe which are PCIe0 and PCIe1. PCIe1 instance is used for PCIe boot process. J784S4 SoC has four instances of 4-lane SERDES. Out of which SERDES0 is used as PHY for PCIe1. So it needs to be functional at all stages of PCIe boot process. Thus add the "bootph-all" boot phase tag to nodes required to enable SERDES0 at all boot stages. Signed-off-by: Hrushikesh Salunke --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index 419c1a70e028..31a8dea2fa8f 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -970,6 +970,7 @@ adc { &serdes_refclk { status =3D "okay"; clock-frequency =3D <100000000>; + bootph-all; }; =20 &dss { @@ -984,6 +985,10 @@ &dss { <&k3_clks 218 22>; }; =20 +&serdes_ln_ctrl { + bootph-all; +}; + &serdes0 { status =3D "okay"; =20 @@ -993,6 +998,7 @@ serdes0_pcie1_link: phy@0 { #phy-cells =3D <0>; cdns,phy-type =3D ; resets =3D <&serdes_wiz0 1>, <&serdes_wiz0 2>; + bootph-all; }; =20 serdes0_usb_link: phy@3 { --=20 2.34.1 From nobody Mon Feb 9 16:35:23 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 913E829E0F8; Fri, 17 Oct 2025 08:47:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760690841; cv=none; b=fu+/3kJqTCPU/e34b2z+a2xMjrGvEtJ5uEd5hSJg09KfGW3Gt6T/Lz3XXzdPCFWS5PKstj6E2032d2gx1WlEWCs2P63w5VusN2Ha4Qd97kaJ5055w7MB34GWT8PI92ZrRF14pwXp/4mKFwx0xF9G5VyadGJIRjP2pCgz0rmX/Z8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760690841; c=relaxed/simple; bh=HKFIst/+5+52Qlo9B7h4MLHGqKPD38BAYCiWVJiIwhY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uyyahY+g2+0SAI5VPkqZsEDD2HCThyCFzW+pmOXU2+TUenci0YdMPowO0sp/mpbpuvEElUoAu72gkg2Wgnll3l21B+tk26bL5JJDRXjVo6VGj126uVdOUSmOKyl7E6ENlcG2pitoWC4kb0pszpnW23j0QlLjwVMAeOI3ZF2F1Ik= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=FfuNIUwn; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="FfuNIUwn" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 59H8l92U2320881; Fri, 17 Oct 2025 03:47:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1760690829; bh=9a2L6fDOfn1ihmucqn3ZAsprxTkzN4huoeiwg5B90Ds=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FfuNIUwnt+2vZjJRHTxSs87EfOpWeb5y3XwMqmqGdWpetnmimnNAMlhZd4MizybsB tyO1KSQQjpuTclGmNVfHsVrBdvzrDuTxkE+UMC2Rd91vl+gbr+y+S6Ucu1/HzU5zwI Ata9KP2bqd/WIzmEGMegPrTKFtW68Tr8VRq53xDQ= Received: from DFLE201.ent.ti.com (dfle201.ent.ti.com [10.64.6.59]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 59H8l95p2282517 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 17 Oct 2025 03:47:09 -0500 Received: from DFLE202.ent.ti.com (10.64.6.60) by DFLE201.ent.ti.com (10.64.6.59) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 17 Oct 2025 03:47:09 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE202.ent.ti.com (10.64.6.60) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Fri, 17 Oct 2025 03:47:09 -0500 Received: from hp-z2-tower.dhcp.ti.com (hp-z2-tower.dhcp.ti.com [172.24.231.157]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59H8ktEW1019203; Fri, 17 Oct 2025 03:47:06 -0500 From: Hrushikesh Salunke To: , , , , , CC: , , , , Subject: [PATCH 3/3] arm64: dts: ti: k3-j784s4-j742s2-evm-common: Add bootph-all tag to "pcie1_ctrl" Date: Fri, 17 Oct 2025 14:16:54 +0530 Message-ID: <20251017084654.2929945-4-h-salunke@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251017084654.2929945-1-h-salunke@ti.com> References: <20251017084654.2929945-1-h-salunke@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" J784S4 SoC has two instances of PCIe which are PCIe0 and PCIe1. J784S4 SoC uses PCIe1 instance for PCIe boot process. To configure PCIe1 at all boot stages "pcie1_ctrl" also needs to be present at all boot stages. Thus add the "bootph-all" boot phase tag to "pcie1_ctrl" device tree node. Signed-off-by: Hrushikesh Salunke --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index 31a8dea2fa8f..3a6e69f88126 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -985,6 +985,10 @@ &dss { <&k3_clks 218 22>; }; =20 +&pcie1_ctrl { + bootph-all; +}; + &serdes_ln_ctrl { bootph-all; }; --=20 2.34.1