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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 263eafd10; Fri, 17 Oct 2025 14:58:17 +0800 (GMT+08:00) From: Finley Xiao To: heiko@sntech.de Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, zhangqing@rock-chips.com, sugar.zhang@rock-chips.com, Finley Xiao Subject: [PATCH v3 1/2] dt-bindings: power: rockchip: Add support for RV1126B Date: Fri, 17 Oct 2025 14:56:45 +0800 Message-ID: <20251017065646.320643-2-finley.xiao@rock-chips.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251017065646.320643-1-finley.xiao@rock-chips.com> References: <20251017065646.320643-1-finley.xiao@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a99f0f64b5903a9kunmca707a471243fd X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQh9KSFYeSENMS0lPT0hCTh9WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=bm1RcU4I3s9QZiaX4EHeHpSbXrLwW+xKrblrpu4PH+lUmq95N8jynyNO6jbjdzFcmC3uwBw1fjFdPwBemRbTPh5C++0c6Y4DZZGsZKevsZdFFLF/gYRhQWVyznZoVL0fubtP2mSv+rkOJVTbidhlucI8c7RqX1rS0r+T2kwSTEw=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=OiKjnIH7axPYhQrFUMzaoOKSY3uvx+hrVR2YyHXGONM=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add power domain IDs for RV1126B SoC. Add a new compatible because register fields have changed. Signed-off-by: Finley Xiao --- Changes in v3: - modify the patch format Changes in v2: - update the commit message - update the license - rename AISP to AIISP .../power/rockchip,power-controller.yaml | 2 ++ .../dt-bindings/power/rockchip,rv1126b-power.h | 17 +++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 include/dt-bindings/power/rockchip,rv1126b-power.h diff --git a/Documentation/devicetree/bindings/power/rockchip,power-control= ler.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controlle= r.yaml index a884e49c995f..f9db602de258 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -46,6 +46,7 @@ properties: - rockchip,rk3576-power-controller - rockchip,rk3588-power-controller - rockchip,rv1126-power-controller + - rockchip,rv1126b-power-controller =20 "#power-domain-cells": const: 1 @@ -126,6 +127,7 @@ $defs: "include/dt-bindings/power/rk3568-power.h" "include/dt-bindings/power/rk3588-power.h" "include/dt-bindings/power/rockchip,rv1126-power.h" + "include/dt-bindings/power/rockchip,rv1126b-power.h" =20 clocks: minItems: 1 diff --git a/include/dt-bindings/power/rockchip,rv1126b-power.h b/include/d= t-bindings/power/rockchip,rv1126b-power.h new file mode 100644 index 000000000000..beb692bd8e72 --- /dev/null +++ b/include/dt-bindings/power/rockchip,rv1126b-power.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao + */ + +#ifndef __DT_BINDINGS_POWER_RV1126B_POWER_H__ +#define __DT_BINDINGS_POWER_RV1126B_POWER_H__ + +/* VD_NPU */ +#define RV1126B_PD_NPU 0 + +/* VD_LOGIC */ +#define RV1126B_PD_VDO 1 +#define RV1126B_PD_AIISP 2 + +#endif --=20 2.43.0 From nobody Sat Feb 7 08:55:18 2026 Received: from mail-m19731102.qiye.163.com (mail-m19731102.qiye.163.com [220.197.31.102]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA6C410F2; Fri, 17 Oct 2025 06:58:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.102 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760684308; cv=none; b=Q3lQNkZCmhf9IV97y1Op7vh9YfDvDzvzjGYCl7hX9bvxBmKw5/xAeUNk857ULJnoR4Cw4ESo2/cKzzefHMQ1MxFsFeXx+L8f568jkGfWfERSEgc4MmkD+zQI9vGXlftB1nRGlwGrqOFQzA/d18N0C4pwbmesXUWM8xtifPG0c+Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760684308; c=relaxed/simple; bh=BzP3BsnOhDOr6ZVUpGZWwsEMX/DaWnstBUxZMzi+7DI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sPqgvY04TuOYFk5eZynlExcLgJ/gJh3L1eQq7T9Ffw0FGqIPUv+TOwvzQCVCpIHvMmCZ2M0dYhXfbLpadfn/KpQSGBbdB2/N1kdzJo+6vmCyKRfjQhuW+CDsvQQXLJpsb16gIC3mlSDgC5LgB6z2ks+L9ZVx2lohRwYVvR9r3Yc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=L0UBp0++; arc=none smtp.client-ip=220.197.31.102 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="L0UBp0++" Received: from xf.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 263eafd29; Fri, 17 Oct 2025 14:58:21 +0800 (GMT+08:00) From: Finley Xiao To: heiko@sntech.de Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, zhangqing@rock-chips.com, sugar.zhang@rock-chips.com, Finley Xiao Subject: [PATCH v3 2/2] pmdomain: rockchip: Add support for RV1126B Date: Fri, 17 Oct 2025 14:56:46 +0800 Message-ID: <20251017065646.320643-3-finley.xiao@rock-chips.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251017065646.320643-1-finley.xiao@rock-chips.com> References: <20251017065646.320643-1-finley.xiao@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a99f0f65e1403a9kunmca707a4712448d X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGhofQ1ZMGhpNGEtDQkkeS0pWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=L0UBp0++FJ2reLvUj/7YrSIEYufL3GZhZ3vLVLXddZ6C4b5lZXYC6ttnIj29Gqd4tv+78H0OvUxNW8zOvJ/wqWje6uuD+F968w8mAtUaDS3xJyzlRieb5Ts6PmYqBkeHWc5S+/R1hJkGhiPjnGtD3zg1JUTnw4KNKDQNYab2ZnU=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=DAzFTU/MPkNJze0jgQJtJnOyq06axZG1FGEYccrKKHs=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add configuration and power domains for RV1126 SoC. Signed-off-by: Finley Xiao Reviewed-by: Heiko Stuebner --- Changes in v3: None Changes in v2: - rename AISP to AIISP - collect review tag drivers/pmdomain/rockchip/pm-domains.c | 41 ++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index 1955c6d453e4..281a76947a08 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -137,6 +138,20 @@ struct rockchip_pmu { .active_wakeup =3D wakeup, \ } =20 +#define DOMAIN_M_G(_name, pwr, status, req, idle, ack, g_mask, wakeup, kee= pon) \ +{ \ + .name =3D _name, \ + .pwr_w_mask =3D (pwr) << 16, \ + .pwr_mask =3D (pwr), \ + .status_mask =3D (status), \ + .req_w_mask =3D (req) << 16, \ + .req_mask =3D (req), \ + .idle_mask =3D (idle), \ + .ack_mask =3D (ack), \ + .clk_ungate_mask =3D (g_mask), \ + .active_wakeup =3D wakeup, \ +} + #define DOMAIN_M_G_SD(_name, pwr, status, req, idle, ack, g_mask, mem, wak= eup, keepon) \ { \ .name =3D _name, \ @@ -205,6 +220,9 @@ struct rockchip_pmu { #define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \ DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup) =20 +#define DOMAIN_RV1126B(name, pwr, req, wakeup) \ + DOMAIN_M_G(name, pwr, pwr, req, req, req, req, wakeup, true) + #define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) =20 @@ -1104,6 +1122,13 @@ static const struct rockchip_domain_info rv1126_pm_d= omains[] =3D { [RV1126_PD_USB] =3D DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), fals= e), }; =20 +static const struct rockchip_domain_info rv1126b_pm_domains[] =3D { + /* name pwr req wakeup */ + [RV1126B_PD_NPU] =3D DOMAIN_RV1126B("npu", BIT(0), BIT(8), false), + [RV1126B_PD_VDO] =3D DOMAIN_RV1126B("vdo", BIT(1), BIT(9), false), + [RV1126B_PD_AIISP] =3D DOMAIN_RV1126B("aiisp", BIT(2), BIT(10), false), +}; + static const struct rockchip_domain_info rk3036_pm_domains[] =3D { [RK3036_PD_MSCH] =3D DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), tru= e), [RK3036_PD_CORE] =3D DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), fal= se), @@ -1516,6 +1541,18 @@ static const struct rockchip_pmu_info rv1126_pmu =3D= { .domain_info =3D rv1126_pm_domains, }; =20 +static const struct rockchip_pmu_info rv1126b_pmu =3D { + .pwr_offset =3D 0x210, + .status_offset =3D 0x230, + .req_offset =3D 0x110, + .idle_offset =3D 0x128, + .ack_offset =3D 0x120, + .clk_ungate_offset =3D 0x140, + + .num_domains =3D ARRAY_SIZE(rv1126b_pm_domains), + .domain_info =3D rv1126b_pm_domains, +}; + static const struct of_device_id rockchip_pm_domain_dt_match[] =3D { { .compatible =3D "rockchip,px30-power-controller", @@ -1585,6 +1622,10 @@ static const struct of_device_id rockchip_pm_domain_= dt_match[] =3D { .compatible =3D "rockchip,rv1126-power-controller", .data =3D (void *)&rv1126_pmu, }, + { + .compatible =3D "rockchip,rv1126b-power-controller", + .data =3D (void *)&rv1126b_pmu, + }, { /* sentinel */ }, }; =20 --=20 2.43.0