From nobody Sun Dec 14 11:37:12 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6ED730FC02; Fri, 17 Oct 2025 06:50:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760683850; cv=none; b=s3hvAtcX7Tb4qlAx3UmeSPy/9ujMftJR38mM8xlLNlP9sQd9+/6RLcT+3McyTIF/VoqGX9Njr0c4y1T0qJHddX6BYq/a8lBhfHv1B67n8+/hhE/qmStSsjXxEkrU6zUTz3I5Yf5W/0UW2KJb2lFgLW32N74VNRCz7jZzrsc0njE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760683850; c=relaxed/simple; bh=JgiawxjGa4mn5DV8C4ye76MQ9N3LOng3NXFB8DUOUd8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Lwsy/Mpsj8TqDIUH2r1jyBrAeMQywM7ucchlP2Ll8HNX4C2O4FXXwTjEYzHqRPL0bY/nPiMgJfP/Dz10dgCN574bvmlAaNrJcS0p5YFG/k8kjBBxPrXpWiPhC9uswr1OUzlXxUtXcdQpJXIliFTwA46RUMsILjU+96cwgL14yBE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=EjSLDsBt; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="EjSLDsBt" X-UUID: 947c89b6ab2511f0ae1e63ff8927bad3-20251017 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zLZQqQLHnCY1mciH6dawkr2tdAgrTMLH7YO3yWKCWA4=; b=EjSLDsBtGJO62lEfusO+D5f0mJ/yFwbq3DBhJWxB1lZCk5sVp2VtqzIeICjgicpXmG3A5pVgi2NzUWtgSZDS3j97biuWHLrSuA5WWtSNUol4goiIOR4B6VnduBcm3mMLhcBEucX2S639Wh5P8rDeMz+JheExbKla4ExmT+Ic56s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:6b8cc2a3-752a-4724-968f-cdf81284b3e4,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:a9d874c,CLOUDID:0fc17d02-eaf8-4c8c-94de-0bc39887e077,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 947c89b6ab2511f0ae1e63ff8927bad3-20251017 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 578769566; Fri, 17 Oct 2025 14:50:34 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 17 Oct 2025 14:50:31 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 17 Oct 2025 14:50:31 +0800 From: Jason-JH Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno , Mauro Carvalho Chehab CC: Matthias Brugger , Nicolas Dufresne , Jason-JH Lin , Nancy Lin , Singo Chang , Paul-PL Chen , Moudy Ho , Xiandong Wang , Sirius Wang , Fei Shao , Chen-yu Tsai , , , , , , , Subject: [PATCH v8 14/20] media: platform: mtk-mdp3: Refactor CMDQ writes for CMDQ API change Date: Fri, 17 Oct 2025 14:44:39 +0800 Message-ID: <20251017065028.1676930-15-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251017065028.1676930-1-jason-jh.lin@mediatek.com> References: <20251017065028.1676930-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Update CMDQ register writes to use subsys-aware APIs, cmdq_pkt_write_subsys() and cmdq_pkt_write_mask_subsys(). This conforms to recent CMDQ API changes that split access by subsys ID support. Since all current MDP SoCs support subsys ID, and future MDP deployments will not run on SoCs without subsys ID, only subsys-specific API calls are needed. No logic for non-subsys ID hardware is required. Signed-off-by: Jason-JH Lin Reviewed-by: AngeloGioacchino Del Regno --- drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 4 ++-- drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index e5ccf673e152..d0b0b072f953 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -321,7 +321,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *= cmd, /* Enable mux settings */ for (index =3D 0; index < ctrl->num_sets; index++) { set =3D &ctrl->sets[index]; - cmdq_pkt_write(&cmd->pkt, set->subsys_id, set->reg, set->value); + cmdq_pkt_write_subsys(&cmd->pkt, set->subsys_id, set->reg, set->reg, set= ->value); } /* Config sub-frame information */ for (index =3D (num_comp - 1); index >=3D 0; index--) { @@ -376,7 +376,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *= cmd, /* Disable mux settings */ for (index =3D 0; index < ctrl->num_sets; index++) { set =3D &ctrl->sets[index]; - cmdq_pkt_write(&cmd->pkt, set->subsys_id, set->reg, 0); + cmdq_pkt_write_subsys(&cmd->pkt, set->subsys_id, set->reg, set->reg, 0); } =20 return 0; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-comp.h index 681906c16419..c6fc180950f2 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -12,14 +12,14 @@ #define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask) \ do { \ typeof(mask) (m) =3D (mask); \ - cmdq_pkt_write_mask(&((cmd)->pkt), id, (base) + (ofst), \ - (val), \ + cmdq_pkt_write_mask_subsys(&((cmd)->pkt), (id), (base), \ + (base) + (ofst), (val), \ (((m) & (ofst##_MASK)) =3D=3D (ofst##_MASK)) ? \ (0xffffffff) : (m)); \ } while (0) =20 #define MM_REG_WRITE(cmd, id, base, ofst, val) \ - cmdq_pkt_write(&((cmd)->pkt), id, (base) + (ofst), (val)) + cmdq_pkt_write_subsys(&((cmd)->pkt), (id), (base), (base) + (ofst), (val)) =20 #define MM_REG_WAIT(cmd, evt) \ do { \ --=20 2.43.0