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A612 falls under ADRENO_6XX_GEN1 family and is a cut down version of A615 GPU. A612 has a new IP called Reduced Graphics Management Unit or RGMU which is a small state machine which helps to toggle GX GDSC (connected to CX rail) to implement IFPC feature. It doesn't support any other features of a full fledged GMU like clock control, resource voting to rpmh etc. So we need linux clock driver support like other gmu-wrapper implementations to control gpu core clock and gpu GX gdsc. This patch skips RGMU core initialization and act more like a gmu-wrapper case. Co-developed-by: Akhil P Oommen Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 16 ++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 87 ++++++++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 143 ++++++++++++++++++++++++= ++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 3 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 16 +++- 7 files changed, 256 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 44df6410bce17613702d7d04906469de4dd021b5..5db01fa2ed441d3fc33b27f7c98= 68c591e08604e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -705,6 +705,22 @@ static const struct adreno_info a6xx_gpus[] =3D { { 157, 3 }, { 127, 4 }, ), + }, { + .chip_ids =3D ADRENO_CHIP_IDS(0x06010200), + .family =3D ADRENO_6XX_GEN1, + .fw =3D { + [ADRENO_FW_SQE] =3D "a630_sqe.fw", + [ADRENO_FW_GMU] =3D "a612_rgmu.bin", + }, + .gmem =3D (SZ_128K + SZ_4K), + .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, + .init =3D a6xx_gpu_init, + .a6xx =3D &(const struct a6xx_info) { + .hwcg =3D a612_hwcg, + .protect =3D &a630_protect, + .gmu_cgc_mode =3D 0x00000022, + .prim_fifo_threshold =3D 0x00080000, + }, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x06010500), .family =3D ADRENO_6XX_GEN1, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index fc62fef2fed87f065cb8fa4e997abefe4ff11cd5..9a11171ec8ad8252d9c7b89d752= d57b53651456e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -350,12 +350,18 @@ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bi= ts[] =3D { /* Trigger a OOB (out of band) request to the GMU */ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) { + struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; int ret; u32 val; int request, ack; =20 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); =20 + /* Skip OOB calls since RGMU is not enabled */ + if (adreno_has_rgmu(adreno_gpu)) + return 0; + if (state >=3D ARRAY_SIZE(a6xx_gmu_oob_bits)) return -EINVAL; =20 @@ -395,10 +401,16 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_= gmu_oob_state state) /* Clear a pending OOB state in the GMU */ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state stat= e) { + struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; int bit; =20 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); =20 + /* Skip OOB calls since RGMU is not enabled */ + if (adreno_has_rgmu(adreno_gpu)) + return; + if (state >=3D ARRAY_SIZE(a6xx_gmu_oob_bits)) return; =20 @@ -1897,7 +1909,8 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) gmu->mmio =3D NULL; gmu->rscc =3D NULL; =20 - if (!adreno_has_gmu_wrapper(adreno_gpu)) { + if (!adreno_has_gmu_wrapper(adreno_gpu) && + !adreno_has_rgmu(adreno_gpu)) { a6xx_gmu_memory_free(gmu); =20 free_irq(gmu->gmu_irq, gmu); @@ -1984,6 +1997,78 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu,= struct device_node *node) return ret; } =20 +int a6xx_rgmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) +{ + struct platform_device *pdev =3D of_find_device_by_node(node); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + int ret; + + if (!pdev) + return -ENODEV; + + gmu->dev =3D &pdev->dev; + + ret =3D of_dma_configure(gmu->dev, node, true); + if (ret) + return ret; + + pm_runtime_enable(gmu->dev); + + /* Mark legacy for manual SPTPRAC control */ + gmu->legacy =3D true; + + /* RGMU requires clocks */ + ret =3D devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); + if (ret < 1) + return ret; + + gmu->nr_clocks =3D ret; + + /* Map the GMU registers */ + gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu"); + if (IS_ERR(gmu->mmio)) { + ret =3D PTR_ERR(gmu->mmio); + goto err_mmio; + } + + gmu->cxpd =3D dev_pm_domain_attach_by_name(gmu->dev, "cx"); + if (IS_ERR(gmu->cxpd)) { + ret =3D PTR_ERR(gmu->cxpd); + goto err_mmio; + } + + if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) { + ret =3D -ENODEV; + goto detach_cxpd; + } + + init_completion(&gmu->pd_gate); + complete_all(&gmu->pd_gate); + gmu->pd_nb.notifier_call =3D cxpd_notifier_cb; + + /* Get a link to the GX power domain to reset the GPU */ + gmu->gxpd =3D dev_pm_domain_attach_by_name(gmu->dev, "gx"); + if (IS_ERR(gmu->gxpd)) { + ret =3D PTR_ERR(gmu->gxpd); + goto err_mmio; + } + + gmu->initialized =3D true; + + return 0; + +detach_cxpd: + dev_pm_domain_detach(gmu->cxpd, false); + +err_mmio: + iounmap(gmu->mmio); + + /* Drop reference taken in of_find_device_by_node */ + put_device(gmu->dev); + + return ret; +} + int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index b8f8ae940b55f5578abdbdec6bf1e90a53e721a5..b0494f1e331cfec3141922a0f0c= 6596934acf63e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -612,15 +612,26 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool s= tate) =20 if (adreno_is_a630(adreno_gpu)) clock_cntl_on =3D 0x8aa8aa02; - else if (adreno_is_a610(adreno_gpu)) + else if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) clock_cntl_on =3D 0xaaa8aa82; else if (adreno_is_a702(adreno_gpu)) clock_cntl_on =3D 0xaaaaaa82; else clock_cntl_on =3D 0x8aa8aa82; =20 - cgc_delay =3D adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111; - cgc_hyst =3D adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555; + if (adreno_is_a612(adreno_gpu)) + cgc_delay =3D 0x11; + else if (adreno_is_a615_family(adreno_gpu)) + cgc_delay =3D 0x111; + else + cgc_delay =3D 0x10111; + + if (adreno_is_a612(adreno_gpu)) + cgc_hyst =3D 0x55; + else if (adreno_is_a615_family(adreno_gpu)) + cgc_delay =3D 0x555; + else + cgc_delay =3D 0x5555; =20 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); @@ -714,6 +725,9 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) cfg->ubwc_swizzle =3D 0x7; } =20 + if (adreno_is_a612(gpu)) + cfg->highest_bank_bit =3D 14; + if (adreno_is_a618(gpu)) cfg->highest_bank_bit =3D 14; =20 @@ -1288,7 +1302,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); =20 /* Setting the mem pool size */ - if (adreno_is_a610(adreno_gpu)) { + if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); } else if (adreno_is_a702(adreno_gpu)) { @@ -1322,7 +1336,7 @@ static int hw_init(struct msm_gpu *gpu) =20 /* Enable fault detection */ if (adreno_is_a730(adreno_gpu) || - adreno_is_a740_family(adreno_gpu)) + adreno_is_a740_family(adreno_gpu) || adreno_is_a612(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfff= ff); else if (adreno_is_a690(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fff= ff); @@ -1576,7 +1590,7 @@ static void a6xx_recover(struct msm_gpu *gpu) */ gpu->active_submits =3D 0; =20 - if (adreno_has_gmu_wrapper(adreno_gpu)) { + if (adreno_has_gmu_wrapper(adreno_gpu) || adreno_has_rgmu(adreno_gpu)) { /* Drain the outstanding traffic on memory buses */ a6xx_bus_clear_pending_transactions(adreno_gpu, true); =20 @@ -2248,6 +2262,55 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) return ret; } =20 +static int a6xx_rgmu_pm_resume(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + unsigned long freq =3D gpu->fast_rate; + struct dev_pm_opp *opp; + int ret; + + gpu->needs_hw_init =3D true; + + trace_msm_gpu_resume(0); + + opp =3D dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + dev_pm_opp_put(opp); + + /* Set the core clock and bus bw, having VDD scaling in mind */ + dev_pm_opp_set_opp(&gpu->pdev->dev, opp); + + pm_runtime_resume_and_get(gmu->dev); + pm_runtime_resume_and_get(gmu->gxpd); + + ret =3D clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); + if (ret) + goto err_rpm_put; + + ret =3D clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); + if (ret) + goto err_bulk_clk; + + msm_devfreq_resume(gpu); + + a6xx_llc_activate(a6xx_gpu); + + return 0; + +err_bulk_clk: + clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); +err_rpm_put: + pm_runtime_put(gmu->gxpd); + pm_runtime_put(gmu->dev); + dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); + + return ret; +} + static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); @@ -2311,6 +2374,41 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) return 0; } =20 +static int a6xx_rgmu_pm_suspend(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + + trace_msm_gpu_suspend(0); + + a6xx_llc_deactivate(a6xx_gpu); + + msm_devfreq_suspend(gpu); + + mutex_lock(&a6xx_gpu->gmu.lock); + + /* Drain the outstanding traffic on memory buses */ + a6xx_bus_clear_pending_transactions(adreno_gpu, true); + + clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); + clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); + + pm_runtime_put_sync(gmu->gxpd); + dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); + pm_runtime_put_sync(gmu->dev); + + mutex_unlock(&a6xx_gpu->gmu.lock); + + if (a6xx_gpu->shadow_bo) + for (int i =3D 0; i < gpu->nr_rings; i++) + a6xx_gpu->shadow[i] =3D 0; + + gpu->suspend_count++; + + return 0; +} + static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); @@ -2588,6 +2686,35 @@ static const struct adreno_gpu_funcs funcs_gmuwrappe= r =3D { .get_timestamp =3D a6xx_get_timestamp, }; =20 +static const struct adreno_gpu_funcs funcs_rgmu =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a6xx_hw_init, + .ucode_load =3D a6xx_ucode_load, + .pm_suspend =3D a6xx_rgmu_pm_suspend, + .pm_resume =3D a6xx_rgmu_pm_resume, + .recover =3D a6xx_recover, + .submit =3D a6xx_submit, + .active_ring =3D a6xx_active_ring, + .irq =3D a6xx_irq, + .destroy =3D a6xx_destroy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .show =3D a6xx_show, +#endif + .gpu_busy =3D a6xx_gpu_busy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .gpu_state_get =3D a6xx_gpu_state_get, + .gpu_state_put =3D a6xx_gpu_state_put, +#endif + .create_vm =3D a6xx_create_vm, + .create_private_vm =3D a6xx_create_private_vm, + .get_rptr =3D a6xx_get_rptr, + .progress =3D a6xx_progress, + }, + .get_timestamp =3D a6xx_gmu_get_timestamp, +}; + static const struct adreno_gpu_funcs funcs_a7xx =3D { .base =3D { .get_param =3D adreno_get_param, @@ -2675,6 +2802,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); else if (adreno_has_gmu_wrapper(adreno_gpu)) ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); + else if (of_device_is_compatible(node, "qcom,adreno-rgmu")) + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_rgmu, 1); else ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); if (ret) { @@ -2691,6 +2820,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) =20 if (adreno_has_gmu_wrapper(adreno_gpu)) ret =3D a6xx_gmu_wrapper_init(a6xx_gpu, node); + else if (of_device_is_compatible(node, "qcom,adreno-rgmu")) + ret =3D a6xx_rgmu_init(a6xx_gpu, node); else ret =3D a6xx_gmu_init(a6xx_gpu, node); of_node_put(node); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 0b17d36c36a9567e6afa4269ae7783ed3578e40e..073e5766198d0ea96c71df34963= a354961f21b95 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -254,6 +254,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx= _gmu_oob_state state); =20 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode); +int a6xx_rgmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu); =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/= msm/adreno/a6xx_gpu_state.c index 4c7f3c642f6ac0a397ac3b282966d25cd4488d3e..838150ff49ab1877da97eecc63a= 5bc1ea5f1edfe 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -1596,7 +1596,8 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_g= pu *gpu) /* Get the generic state from the adreno core */ adreno_gpu_state_get(gpu, &a6xx_state->base); =20 - if (!adreno_has_gmu_wrapper(adreno_gpu)) { + if (!adreno_has_gmu_wrapper(adreno_gpu) && + !adreno_has_rgmu(adreno_gpu)) { a6xx_get_gmu_registers(gpu, a6xx_state); =20 a6xx_state->gmu_log =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.= log); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index afaa3cfefd357dc0230994c8b5830a14c6d7a352..60973c3ec021bcd15b7a180c93c= 05b171b21ebe0 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1196,6 +1196,7 @@ int adreno_gpu_init(struct drm_device *drm, struct pl= atform_device *pdev, =20 /* Only handle the core clock when GMU is not in use (or is absent). */ if (adreno_has_gmu_wrapper(adreno_gpu) || + adreno_has_rgmu(adreno_gpu) || adreno_gpu->info->family < ADRENO_6XX_GEN1) { /* * This can only be done before devm_pm_opp_of_add_table(), or diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 390fa6720d9b096f4fa7d1639645d453d43b153a..25ee6b277fe2db5950a057a92d3= 3244d76de299c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -392,6 +392,16 @@ static inline int adreno_is_a610(const struct adreno_g= pu *gpu) return adreno_is_revn(gpu, 610); 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But it doesn't do clock or voltage scaling. So we need the gpu core clock in the GPU node along with the power domain to do clock and voltage scaling from the kernel. Update the bindings to describe this GPU. Signed-off-by: Akhil P Oommen --- .../devicetree/bindings/display/msm/gpu.yaml | 31 ++++++++++++++++++= ++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Docum= entation/devicetree/bindings/display/msm/gpu.yaml index 3696b083e353031a496a1f299d8f373270ca562d..efc529e82bc198e7c3c89a5eecb= 6f929960a8de9 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -45,11 +45,11 @@ properties: - const: amd,imageon =20 clocks: - minItems: 2 + minItems: 1 maxItems: 7 =20 clock-names: - minItems: 2 + minItems: 1 maxItems: 7 =20 reg: @@ -388,6 +388,33 @@ allOf: required: - clocks - clock-names + + - if: + properties: + compatible: + contains: + const: qcom,adreno-612.0 + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + + clock-names: + items: + - const: core + description: GPU Core clock + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_dbgc + + required: + - clocks + - clock-names + else: if: properties: --=20 2.51.0 From nobody Sun Feb 8 16:12:20 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F340301034 for ; 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Compared to GMU, it doesn't manage GPU clock, voltage scaling, bw voting or any other functionalities. All it does is detect an idle GPU and toggle the GDSC switch. As it doesn't access DDR space, it doesn't require iommu. So far, only Adreno 612 GPU has an RGMU core. Document RGMU in the GMU's schema. Signed-off-by: Akhil P Oommen --- .../devicetree/bindings/display/msm/gmu.yaml | 98 +++++++++++++++++-= ---- 1 file changed, 79 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Docum= entation/devicetree/bindings/display/msm/gmu.yaml index afc1879357440c137cadeb2d9a74ae8459570a25..a262d41755f09f21f607bf7a1fd= 567f386595f39 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -26,6 +26,9 @@ properties: - items: - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$' - const: qcom,adreno-gmu + - items: + - const: qcom,adreno-rgmu-612.0 + - const: qcom,adreno-rgmu - const: qcom,adreno-gmu-wrapper =20 reg: @@ -45,24 +48,30 @@ properties: maxItems: 7 =20 interrupts: - items: - - description: GMU HFI interrupt - - description: GMU interrupt + minItems: 2 + maxItems: 2 =20 interrupt-names: - items: - - const: hfi - - const: gmu + oneOf: + - items: + - const: hfi + description: GMU HFI interrupt + - const: gmu + description: GMU interrupt + - items: + - const: oob + description: GMU OOB interrupt + - const: gmu + description: GMU interrupt + =20 power-domains: - items: - - description: CX power domain - - description: GX power domain + minItems: 2 + maxItems: 3 =20 power-domain-names: - items: - - const: cx - - const: gx + minItems: 2 + maxItems: 3 =20 iommus: maxItems: 1 @@ -86,6 +95,44 @@ required: additionalProperties: false =20 allOf: + - if: + properties: + compatible: + contains: + const: qcom,adreno-rgmu-612.0 + then: + properties: + reg: + items: + - description: Core RGMU registers + reg-names: + items: + - const: gmu + clocks: + items: + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GPU SMMU vote clock + clock-names: + items: + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: smmu_vote + power-domains: + items: + - description: CX power domain + - description: GX power domain + - description: VDD_CX power domain + power-domain-names: + items: + - const: cx + - const: gx + - const: vdd_cx + - if: properties: compatible: @@ -313,13 +360,26 @@ allOf: items: - const: gmu else: - required: - - clocks - - clock-names - - interrupts - - interrupt-names - - iommus - - operating-points-v2 + if: + properties: + compatible: + contains: + const: qcom,adreno-rgmu + then: + required: + - clocks + - clock-names + - interrupts + - interrupt-names + - operating-points-v2 + else: + required: + - clocks + - clock-names + - interrupts + - interrupt-names + - iommus + - operating-points-v2 =20 examples: - | --=20 2.51.0 From nobody Sun Feb 8 16:12:20 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 083A43016EA for ; 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Signed-off-by: Qingqing Zhou Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qco= m/sm6150.dtsi index 3d2a1cb02b628a5db7ca14bea784429be5a020f9..e62b062c543657b6fd8f9aba7ad= 595855d8134d6 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -1700,6 +1700,33 @@ gpucc: clock-controller@5090000 { #power-domain-cells =3D <1>; }; =20 + adreno_smmu: iommu@50a0000 { + compatible =3D "qcom,qcs615-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x50a0000 0x0 0x10000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + dma-coherent; + + power-domains =3D <&gpucc CX_GDSC>; + clocks =3D <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names =3D "mem", + "hlos", + "iface"; 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Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 112 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qco= m/sm6150.dtsi index e62b062c543657b6fd8f9aba7ad595855d8134d6..8181f63e4d6838b1d1989721997= 56271707e6e49 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -508,6 +508,11 @@ rproc_adsp_mem: rproc-adsp@95900000 { reg =3D <0x0 0x95900000 0x0 0x1e00000>; no-map; }; + + pil_gpu_mem: pil-gpu@97715000 { + reg =3D <0x0 0x97715000 0x0 0x2000>; + no-map; + }; }; =20 soc: soc@0 { @@ -1687,6 +1692,113 @@ data-pins { }; }; =20 + gpu: gpu@5000000 { + compatible =3D "qcom,adreno-612.0", "qcom,adreno"; + reg =3D <0x0 0x05000000 0x0 0x90000>; + reg-names =3D "kgsl_3d0_reg_memory"; + + clocks =3D <&gpucc GPU_CC_GX_GFX3D_CLK>; + clock-names =3D "core"; + + interrupts =3D ; + + interconnects =3D <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "gfx-mem"; + + iommus =3D <&adreno_smmu 0x0 0x401>; + + operating-points-v2 =3D <&gpu_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + qcom,gmu =3D <&rgmu>; + + #cooling-cells =3D <2>; + + status =3D "disabled"; + + gpu_zap_shader: zap-shader { + memory-region =3D <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-845000000 { + opp-hz =3D /bits/ 64 <845000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + opp-peak-kBps =3D <7050000>; + }; + + opp-745000000 { + opp-hz =3D /bits/ 64 <745000000>; + required-opps =3D <&rpmhpd_opp_nom_l1>; + opp-peak-kBps =3D <6075000>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <5287500>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + opp-peak-kBps =3D <3975000>; + }; + + opp-435000000 { + opp-hz =3D /bits/ 64 <435000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <3000000>; + }; + + opp-290000000 { + opp-hz =3D /bits/ 64 <290000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1762500>; + }; + }; + }; + + rgmu: rgmu@506a000 { + compatible =3D "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu"; + reg =3D <0x0 0x0506a000 0x0 0x34000>; + reg-names =3D "gmu"; + + clocks =3D <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "gmu", + "cxo", + "axi", + "memnoc", + "smmu_vote"; + + power-domains =3D <&gpucc CX_GDSC>, + <&gpucc GX_GDSC>, + <&rpmhpd RPMHPD_CX>; + power-domain-names =3D "cx", "gx", "vdd_cx"; + + interrupts =3D , + ; + interrupt-names =3D "oob", "gmu"; + + operating-points-v2 =3D <&rgmu_opp_table>; + + rgmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + }; + }; 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Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index 705ea71b07a10aea82b5789e8ab9f757683f678a..a1c87b925bf0052c6876db96a2d= 6e3c3ab8037c3 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -288,6 +288,14 @@ vreg_l17a: ldo17 { }; }; =20 +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/qcs615/a612_zap.mbn"; +}; + &pcie { perst-gpios =3D <&tlmm 101 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 100 GPIO_ACTIVE_HIGH>; --=20 2.51.0