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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-33d5ddf16bcsm791695a91.4.2025.10.17.18.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Oct 2025 18:33:51 -0700 (PDT) From: Qiang Yu Date: Fri, 17 Oct 2025 18:33:42 -0700 Subject: [PATCH v5 5/6] phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251017-glymur_pcie-v5-5-82d0c4bd402b@oss.qualcomm.com> References: <20251017-glymur_pcie-v5-0-82d0c4bd402b@oss.qualcomm.com> In-Reply-To: <20251017-glymur_pcie-v5-0-82d0c4bd402b@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Qiang Yu , Prudhvi Yarlagadda , Wenbin Yao , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760751221; l=2929; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=3I4+Hh02UK/6hCXFAJiGGjbIJsRvaSQpVywV9Q7zV1c=; b=dKOgcVx4w6ztqfdIQRHnQOd2o6aFzRsanH60UTNwCy92Yge+jRnAAJ0SEKuR8G3sBjmBVOMKr rZ9zpNrUYtpD1fRGewkb2hmXQyRE7yq4vYg0tLfkiQp72LU7mZfM/u3 X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=K88v3iWI c=1 sm=1 tr=0 ts=68f2ee81 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=cXB1dxBGfnZZ65A63A0A:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: cHTkbrAvvz4lhgWT04LdFuu8rWoeGTls X-Proofpoint-ORIG-GUID: cHTkbrAvvz4lhgWT04LdFuu8rWoeGTls X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDEzMDAzNSBTYWx0ZWRfX/7lzOCuBi8gP sbp9SvhMA3iycGQCWAKLyAwWXZRhpxnAiXJAKlAXOMDHoyRfDdNw3lcK1mFeQkSGIQyP+kUjG/S ngooGCh3Aj8YD0ADzh85EnpKLeT+ibNhDUuLMXAek+oOupv2F8j82L9zmMERQuIEBcehz4KPblu zdsMIB2hMuQ3epelci8eA4C0hEB3r3vAN4W+uXdQwznkz73gPcWyZqpOQyl8bCRZ4QCEDE8pC+W vqY4tmUGM5j6pGOH4N38ZhUJM7rAUqLSDOw9qHhTm3MsUN9lO2lrydXNqt3xChs3OMOqxCnZTPN 6VrK0AdaKpMeE4XEj+GNJNb5IGkeTSuUKui3qRjO0JrC0xeNrIvKdWUapeITHdOMboJ6BPllDEg j21NFRF5AFUMol/iud6//1vU3OYICg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-18_01,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 impostorscore=0 priorityscore=1501 phishscore=0 adultscore=0 clxscore=1015 bulkscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510130035 From: Prudhvi Yarlagadda Add support for Gen5 x4 PCIe QMP PHY found on Glymur platform. Signed-off-by: Prudhvi Yarlagadda Signed-off-by: Wenbin Yao Reviewed-by: Dmitry Baryshkov Acked-by: Manivannan Sadhasivam Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 32 ++++++++++++++++++++++++++++= ++++ 1 file changed, 32 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 62b1c845b6275d924fa501ac64e69db5f58844aa..86b1b7e2da86a8675e3e48e90b7= 82afb21cafd77 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -100,6 +100,12 @@ static const unsigned int pciephy_v7_regs_layout[QPHY_= LAYOUT_SIZE] =3D { [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V7_PCS_POWER_DOWN_CONTROL, }; =20 +static const unsigned int pciephy_v8_50_regs_layout[QPHY_LAYOUT_SIZE] =3D { + [QPHY_START_CTRL] =3D QPHY_V8_50_PCS_START_CONTROL, + [QPHY_PCS_STATUS] =3D QPHY_V8_50_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V8_50_PCS_POWER_DOWN_CONTROL, +}; + static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), @@ -3072,6 +3078,7 @@ struct qmp_pcie_offsets { u16 rx2; u16 txz; u16 rxz; + u16 txrxz; u16 ln_shrd; }; =20 @@ -3356,6 +3363,12 @@ static const struct qmp_pcie_offsets qmp_pcie_offset= s_v6_30 =3D { .ln_shrd =3D 0x8000, }; =20 +static const struct qmp_pcie_offsets qmp_pcie_offsets_v8_50 =3D { + .serdes =3D 0x8000, + .pcs =3D 0x9000, + .txrxz =3D 0xd000, +}; + static const struct qmp_phy_cfg ipq8074_pciephy_cfg =3D { .lanes =3D 1, =20 @@ -4412,6 +4425,22 @@ static const struct qmp_phy_cfg qmp_v6_gen4x4_pcieph= y_cfg =3D { .phy_status =3D PHYSTATUS_4_20, }; =20 +static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg =3D { + .lanes =3D 4, + + .offsets =3D &qmp_pcie_offsets_v8_50, + + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + + .regs =3D pciephy_v8_50_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS_4_20, +}; + static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_ph= y_cfg_tbls *tbls) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -5163,6 +5192,9 @@ static int qmp_pcie_probe(struct platform_device *pde= v) =20 static const struct of_device_id qmp_pcie_of_match_table[] =3D { { + .compatible =3D "qcom,glymur-qmp-gen5x4-pcie-phy", + .data =3D &glymur_qmp_gen5x4_pciephy_cfg, + }, { .compatible =3D "qcom,ipq6018-qmp-pcie-phy", .data =3D &ipq6018_pciephy_cfg, }, { --=20 2.34.1