From nobody Mon Feb 9 04:31:38 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D905E30DEA3 for ; Fri, 17 Oct 2025 05:06:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760677579; cv=none; b=Q1LFyFp8NCcK1KhklwxUplV+kSVK1s4FjoMS6xUT/Z1m5bGxSxu0BAX0LpbpWnP1KnjTrmFnr40NADrm48g6j6szSiXgv+gcZIasfB6yGOUnCZpnxWgDY5ZqD/Dt4vXJ9BwL85jFuamwV4X8pMADmXYt48A59yaBrBorp3memuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760677579; c=relaxed/simple; bh=GyByrX/SU0O+few+EwG8B0kFmCZ8Wrg4XSxHLmS+pV4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fm/UlGzy0KyN6mnLss4ADI4Rs9pTsoeHz3XdcHtqTn0KlOi9UsTCa9kdUNG5GDA3FjZCADA4n4pvk2bMJkp5FRvjmfsf0r6jWKnOakPpcVDlhp7i/STRnOoZrjKhhWVd+6AVcM2eYH0ZDsUCclZ3Wy+e9c0eh1I+nCcwlwb5EF0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=LEMqmH2h; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="LEMqmH2h" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 59GKLNoC022174 for ; Fri, 17 Oct 2025 05:06:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Z8fQboa7kH2ooxeNlcCWSoboGIwEnHH/IbLSmZ1wIGQ=; b=LEMqmH2hJ2MaNx+3 R/7c40SvFHl4RQC/SJrTKdlt3orUl3z7aRs9DPpTVIzxvJK+2Ot5a5Ls2XDkJUo7 q4VFebH6MmiMH1VSnc+y5/zkMemFrT6FFc48xpEeOUGOhKg/K5RMjfJK2gEyjkcB W1JK6dNXBr7/hDDTVR7tBZt5IESWB41IhlvCnALXuY8YS1QO/asFbkFVYxLpuVla ZpUVy/fUlZv+7BNqFpB2eXAh1iriaxpRWzMpJLA4GUnp04sMGC4TjtIUFLTsFJHz GbmjOPFfoj7S/5mCILjPRe2knnBNj4uBABj97bQQK+JNv1Yg31D3OoCULkJzms8Z ErNrPA== Received: from mail-qv1-f72.google.com (mail-qv1-f72.google.com [209.85.219.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 49rtrtfun2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 17 Oct 2025 05:06:15 +0000 (GMT) Received: by mail-qv1-f72.google.com with SMTP id 6a1803df08f44-79e48b76f68so67753856d6.3 for ; Thu, 16 Oct 2025 22:06:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760677575; x=1761282375; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z8fQboa7kH2ooxeNlcCWSoboGIwEnHH/IbLSmZ1wIGQ=; b=tosfZHbWJBFeaj1a9mQ4F+HD8w2hiS1fHLbSoxSTzUNfI7DS/W1NvrE92pxwm8HyWj 9o1DkZrlbkobR366mUOum7ImBfGAZMMIjDxvcfhNbLgjomEtrRLHyerIhnC17238b8rS d7b1dm8jm1AmVbg3dU4KrOPTg+2aeQwOo8GLKg0ixOfVSZZItdIf+HQhne8WW7Sx5VAq jJMW7+Y0JanAtCmpQPDOa5b8h0LKQNW+/95bCqeyVk71by8ghQxVPsqbdY/H55TxH33k It7ElZYZazwdO6kTH9jPnbcJ5s2GiGlrqNJuPP7MVtJ3rCkdVvdST791o9EYglSyEdFE htfA== X-Gm-Message-State: AOJu0YycEQJv65oh8hmldA0u+dLYwnxQ+E+OVvXA46AK3z+Sz03zFJVy OqLRfMc5ibw71reZmDR/Vrxl0NvuRte7DJM/4iHFmodKEG7djihVdL0pHsVXuQlMWBzfsc8LgD0 KGG5tALJix+p73s96RE94g4YP91OYZHXKQeqnKJODXXjtiLn4T5Lmyb5FusH+14GGBMI= X-Gm-Gg: ASbGncuYtBx4hSo2cxRAZqUh9IePBNAlSXP+O0k47s0XPOCpwsZTApDLDIzqkYHjtz4 TYsDzryQ2zAi47TjF9MUWATiK6JLhxZa3CqY9xYNDK/THSW9jZA/ftj9e0aUz/XmcIdbeMd8YVx FQKGOB+jssve2m1XLyr63kGnih3kEABTBQ8we2andug7KQdHbLB46r04gFWqo4tl0dG5qS9f9Gv zV3NagIgix2ggvnvlwyM2ggmN32GaxaUt+9wljxDvz4qHGg6ZfFIELUI7BCMXN9RWcYQIFQRlWh prERzFvx8l88TmD5Q54bMohW7iRyrSghg64SFeiI2L3oZyuhVjG/4rsBZaZshdLYmzFvPL0jh8E lV6kC2l66PPwRE0jw3dTnHZH+MtaRM0k6irEjNwVtP0hrBl6t15XFSy6BiQ+cNFdc6g== X-Received: by 2002:a05:6214:258c:b0:7a9:3d3b:fe95 with SMTP id 6a1803df08f44-87c2057df3bmr39191936d6.19.1760677574295; Thu, 16 Oct 2025 22:06:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGaBH1pH5LCCOh8aDT6MLEDhSWh9f8TeAMAFTND3J5UBdi6bTgzPXfbEIR/QSU3CaTkAMSJZA== X-Received: by 2002:a05:6214:258c:b0:7a9:3d3b:fe95 with SMTP id 6a1803df08f44-87c2057df3bmr39191576d6.19.1760677573728; Thu, 16 Oct 2025 22:06:13 -0700 (PDT) Received: from WENMLIU-LAB01.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-87c0128c9d8sm57641916d6.33.2025.10.16.22.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Oct 2025 22:06:13 -0700 (PDT) From: Wenmeng Liu Date: Fri, 17 Oct 2025 13:06:01 +0800 Subject: [PATCH v5 1/3] media: qcom: camss: Add common TPG support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251017-camss_tpg-v5-1-cafe3ad42163@oss.qualcomm.com> References: <20251017-camss_tpg-v5-0-cafe3ad42163@oss.qualcomm.com> In-Reply-To: <20251017-camss_tpg-v5-0-cafe3ad42163@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760677563; l=24051; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=GyByrX/SU0O+few+EwG8B0kFmCZ8Wrg4XSxHLmS+pV4=; b=ovWS+RSkprBdvnPFA/vjoGXhOFDfRKMumspVJ+qdgyM3r7uUkzmf+LXj+BlHF/WPZzhxtqATn jYofJmFTi0sDG1pq5UGRfcnGcw7P+RpUaBN9huIcab8n2lirYjVotE9 X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-ORIG-GUID: atWX0cqEp2q8UAIuLD44PPOvTIbXa6BA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDEzMDAyMiBTYWx0ZWRfXzv/0+obxOX7F 2ErmTnfph4mbsXDUHmmJuOEU29Q8wwfedMe0Jvbjefk3DOyLFstFfYFSBQ2gq3ZDKQuNQSPsGiC t6yn40LHaLH1HdyfvJn2MgQWTE7WhVLTJc1jX//n4BQ4TKif4E6mh6+vCOIK/2RjWjXGLOX6Ses 9lDmIGT1++I3LiANwc2KkyOzXGubhzccOnbraO/OEPpxJ+D0zKR4Xq9we2YH+H2wjoOOxfOtjp7 22lDO4wSWlVCXJRtGsO95B6EfoB+B5QqqOgNpbieJWMmkc6XthUuOOUudmWm292YLj6fCFcv57U Ut+TIK7fya0I3JITRCp1OSM4v+P8mJuR4wwZeEpNhTt+Dc0ql51wbWTAFGGzOBRptLAXxkdnycd 5yt+GOs6TVrXNcs9HRlnCaC/h65YFg== X-Authority-Analysis: v=2.4 cv=SfD6t/Ru c=1 sm=1 tr=0 ts=68f1cec7 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=9-4OygZIhI6akIEH2MEA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-GUID: atWX0cqEp2q8UAIuLD44PPOvTIbXa6BA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-17_02,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 adultscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510130022 Introduce a new common Test Pattern Generator (TPG) implementation for Qualcomm CAMSS. This module provides a generic interface for pattern generation that can be reused by multiple platforms. Unlike CSID-integrated TPG, this TPG acts as a standalone block that emulates both CSIPHY and sensor behavior, enabling flexible test patterns without external hardware. Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-tpg.c | 696 ++++++++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-tpg.h | 125 +++++ drivers/media/platform/qcom/camss/camss.h | 5 + 4 files changed, 827 insertions(+) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 23960d02877de132b63ebfe88affe55576256829..0eda4b18ad0e93f5e63135fabd5= a02ae67bcd5ad 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -26,5 +26,6 @@ qcom-camss-objs +=3D \ camss-vfe.o \ camss-video.o \ camss-format.o \ + camss-tpg.o \ =20 obj-$(CONFIG_VIDEO_QCOM_CAMSS) +=3D qcom-camss.o diff --git a/drivers/media/platform/qcom/camss/camss-tpg.c b/drivers/media/= platform/qcom/camss/camss-tpg.c new file mode 100644 index 0000000000000000000000000000000000000000..c436cdb7041b555ce9458270eb4= 6996e78f1d5eb --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg.c @@ -0,0 +1,696 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * + * Qualcomm MSM Camera Subsystem - TPG Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "camss-tpg.h" +#include "camss.h" + +const char * const testgen_payload_modes[] =3D { + "Disabled", + "Incrementing", + "Alternating 0x55/0xAA", + "Reserved", + "Reserved", + "Pseudo-random Data", + "User Specified", + "Reserved", + "Reserved", + "Color bars", + "Reserved" +}; + +static const struct tpg_format_info formats_gen1[] =3D { + { + MEDIA_BUS_FMT_SBGGR8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + }, + { + MEDIA_BUS_FMT_SGBRG8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + }, + { + MEDIA_BUS_FMT_SGRBG8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + }, + { + MEDIA_BUS_FMT_SRGGB8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + }, + { + MEDIA_BUS_FMT_SBGGR10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + }, + { + MEDIA_BUS_FMT_SGBRG10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + }, + { + MEDIA_BUS_FMT_SGRBG10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + }, + { + MEDIA_BUS_FMT_SRGGB10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + }, + { + MEDIA_BUS_FMT_SBGGR12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + }, + { + MEDIA_BUS_FMT_SGBRG12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + }, + { + MEDIA_BUS_FMT_SGRBG12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + }, + { + MEDIA_BUS_FMT_SRGGB12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + }, + { + MEDIA_BUS_FMT_Y8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + }, + { + MEDIA_BUS_FMT_Y10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + }, +}; + +const struct tpg_formats tpg_formats_gen1 =3D { + .nformats =3D ARRAY_SIZE(formats_gen1), + .formats =3D formats_gen1 +}; + +const struct tpg_format_info *tpg_get_fmt_entry(struct tpg_device *tpg, + const struct tpg_format_info *formats, + unsigned int nformats, + u32 code) +{ + struct device *dev =3D tpg->camss->dev; + size_t i; + + for (i =3D 0; i < nformats; i++) + if (code =3D=3D formats[i].code) + return &formats[i]; + + dev_warn_once(dev, "Unknown format\n"); + + return ERR_PTR(-EINVAL); +} + +/* + * tpg_set_clock_rates - set clock rates on tpg module + * @tpg: tpg device + */ +static int tpg_set_clock_rates(struct tpg_device *tpg) +{ + struct device *dev =3D tpg->camss->dev; + int ret; + int i; + + for (i =3D 0; i < tpg->nclocks; i++) { + struct camss_clock *clock =3D &tpg->clock[i]; + long round_rate; + + if (clock->freq[0] > 0) { + round_rate =3D clk_round_rate(clock->clk, clock->freq[0]); + if (round_rate < 0) { + dev_err(dev, "clk round rate failed: %ld\n", + round_rate); + return -EINVAL; + } + + ret =3D clk_set_rate(clock->clk, round_rate); + if (ret < 0) { + dev_err(dev, "clk set rate failed: %d\n", ret); + return ret; + } + } + } + + return 0; +} + +/* + * tpg_set_power - Power on/off tpg module + * @sd: tpg V4L2 subdevice + * @on: Requested power state + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_set_power(struct v4l2_subdev *sd, int on) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct device *dev =3D tpg->camss->dev; + + if (on) { + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + ret =3D tpg_set_clock_rates(tpg); + if (ret < 0) { + pm_runtime_put_sync(dev); + return ret; + } + + ret =3D camss_enable_clocks(tpg->nclocks, tpg->clock, dev); + if (ret < 0) { + pm_runtime_put_sync(dev); + return ret; + } + + tpg->res->hw_ops->reset(tpg); + + tpg->res->hw_ops->hw_version(tpg); + } else { + camss_disable_clocks(tpg->nclocks, tpg->clock); + + pm_runtime_put_sync(dev); + } + + return 0; +} + +/* + * tpg_set_stream - Enable/disable streaming on tpg module + * @sd: tpg V4L2 subdevice + * @enable: Requested streaming state + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + int ret =3D 0; + + if (enable) { + ret =3D v4l2_ctrl_handler_setup(&tpg->ctrls); + if (ret < 0) { + dev_err(tpg->camss->dev, + "could not sync v4l2 controls: %d\n", ret); + return ret; + } + } + + tpg->res->hw_ops->configure_stream(tpg, enable); + + return 0; +} + +/* + * __tpg_get_format - Get pointer to format structure + * @tpg: tpg device + * @cfg: V4L2 subdev pad configuration + * @pad: pad from which format is requested + * @which: TRY or ACTIVE format + * + * Return pointer to TRY or ACTIVE format structure + */ +static struct v4l2_mbus_framefmt * +__tpg_get_format(struct tpg_device *tpg, + struct v4l2_subdev_state *sd_state, + unsigned int pad, + enum v4l2_subdev_format_whence which) +{ + if (which =3D=3D V4L2_SUBDEV_FORMAT_TRY) + return v4l2_subdev_state_get_format(sd_state, + pad); + + return &tpg->fmt[pad]; +} + +/* + * tpg_try_format - Handle try format by pad subdev method + * @tpg: tpg device + * @cfg: V4L2 subdev pad configuration + * @pad: pad on which format is requested + * @fmt: pointer to v4l2 format structure + * @which: wanted subdev format + */ +static void tpg_try_format(struct tpg_device *tpg, + struct v4l2_subdev_state *sd_state, + unsigned int pad, + struct v4l2_mbus_framefmt *fmt, + enum v4l2_subdev_format_whence which) +{ + unsigned int i; + + switch (pad) { + case MSM_TPG_PAD_SINK: + for (i =3D 0; i < tpg->res->formats->nformats; i++) + if (tpg->res->formats->formats[i].code =3D=3D fmt->code) + break; + + /* If not found, use SBGGR8 as default */ + if (i >=3D tpg->res->formats->nformats) + fmt->code =3D MEDIA_BUS_FMT_SBGGR8_1X8; + + fmt->width =3D clamp_t(u32, fmt->width, 1, 8191); + fmt->height =3D clamp_t(u32, fmt->height, 1, 8191); + + fmt->field =3D V4L2_FIELD_NONE; + fmt->colorspace =3D V4L2_COLORSPACE_SRGB; + + break; + case MSM_TPG_PAD_SRC: + *fmt =3D *__tpg_get_format(tpg, sd_state, + MSM_TPG_PAD_SINK, + which); + + break; + } +} + +/* + * tpg_enum_mbus_code - Handle format enumeration + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @code: pointer to v4l2_subdev_mbus_code_enum structure + * return -EINVAL or zero on success + */ +static int tpg_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + if (code->pad =3D=3D MSM_TPG_PAD_SINK) { + if (code->index >=3D tpg->res->formats->nformats) + return -EINVAL; + + code->code =3D tpg->res->formats->formats[code->index].code; + } else { + if (code->index > 0) + return -EINVAL; + + format =3D __tpg_get_format(tpg, sd_state, + MSM_TPG_PAD_SINK, + code->which); + + code->code =3D format->code; + } + + return 0; +} + +/* + * tpg_enum_frame_size - Handle frame size enumeration + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @fse: pointer to v4l2_subdev_frame_size_enum structure + * return -EINVAL or zero on success + */ +static int tpg_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt format; + + if (fse->index !=3D 0) + return -EINVAL; + + format.code =3D fse->code; + format.width =3D 1; + format.height =3D 1; + tpg_try_format(tpg, sd_state, fse->pad, &format, fse->which); + fse->min_width =3D format.width; + fse->min_height =3D format.height; + + if (format.code !=3D fse->code) + return -EINVAL; + + format.code =3D fse->code; + format.width =3D -1; + format.height =3D -1; + tpg_try_format(tpg, sd_state, fse->pad, &format, fse->which); + fse->max_width =3D format.width; + fse->max_height =3D format.height; + + return 0; +} + +/* + * tpg_get_format - Handle get format by pads subdev method + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @fmt: pointer to v4l2 subdev format structure + * + * Return -EINVAL or zero on success + */ +static int tpg_get_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + format =3D __tpg_get_format(tpg, sd_state, fmt->pad, fmt->which); + if (!format) + return -EINVAL; + + fmt->format =3D *format; + + return 0; +} + +/* + * tpg_set_format - Handle set format by pads subdev method + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @fmt: pointer to v4l2 subdev format structure + * + * Return -EINVAL or zero on success + */ +static int tpg_set_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + format =3D __tpg_get_format(tpg, sd_state, fmt->pad, fmt->which); + if (!format) + return -EINVAL; + + tpg_try_format(tpg, sd_state, fmt->pad, &fmt->format, + fmt->which); + *format =3D fmt->format; + + if (fmt->pad =3D=3D MSM_TPG_PAD_SINK) { + format =3D __tpg_get_format(tpg, sd_state, + MSM_TPG_PAD_SRC, + fmt->which); + + *format =3D fmt->format; + tpg_try_format(tpg, sd_state, MSM_TPG_PAD_SRC, + format, + fmt->which); + } + return 0; +} + +/* + * tpg_init_formats - Initialize formats on all pads + * @sd: tpg V4L2 subdevice + * @fh: V4L2 subdev file handle + * + * Initialize all pad formats with default values. + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_init_formats(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct v4l2_subdev_format format =3D { + .pad =3D MSM_TPG_PAD_SINK, + .which =3D fh ? V4L2_SUBDEV_FORMAT_TRY : + V4L2_SUBDEV_FORMAT_ACTIVE, + .format =3D { + .code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .width =3D 1920, + .height =3D 1080 + } + }; + + return tpg_set_format(sd, fh ? fh->state : NULL, &format); +} + +/* + * tpg_set_test_pattern - Set test generator's pattern mode + * @tpg: TPG device + * @value: desired test pattern mode + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_set_test_pattern(struct tpg_device *tpg, s32 value) +{ + return tpg->res->hw_ops->configure_testgen_pattern(tpg, value); +} + +/* + * tpg_s_ctrl - Handle set control subdev method + * @ctrl: pointer to v4l2 control structure + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct tpg_device *tpg =3D container_of(ctrl->handler, + struct tpg_device, ctrls); + int ret =3D -EINVAL; + + switch (ctrl->id) { + case V4L2_CID_TEST_PATTERN: + ret =3D tpg_set_test_pattern(tpg, ctrl->val); + break; + } + + return ret; +} + +static const struct v4l2_ctrl_ops tpg_ctrl_ops =3D { + .s_ctrl =3D tpg_s_ctrl, +}; + +/* + * msm_tpg_subdev_init - Initialize tpg device structure and resources + * @tpg: tpg device + * @res: tpg module resources table + * @id: tpg module id + * + * Return 0 on success or a negative error code otherwise + */ +int msm_tpg_subdev_init(struct camss *camss, + struct tpg_device *tpg, + const struct camss_subdev_resources *res, u8 id) +{ + struct platform_device *pdev; + struct device *dev; + int i, j; + + dev =3D camss->dev; + pdev =3D to_platform_device(dev); + + tpg->camss =3D camss; + tpg->id =3D id; + tpg->res =3D &res->tpg; + tpg->res->hw_ops->subdev_init(tpg); + + tpg->base =3D devm_platform_ioremap_resource_byname(pdev, res->reg[0]); + if (IS_ERR(tpg->base)) + return PTR_ERR(tpg->base); + + tpg->nclocks =3D 0; + while (res->clock[tpg->nclocks]) + tpg->nclocks++; + + if (tpg->nclocks) { + tpg->clock =3D devm_kcalloc(dev, + tpg->nclocks, sizeof(*tpg->clock), + GFP_KERNEL); + if (!tpg->clock) + return -ENOMEM; + + for (i =3D 0; i < tpg->nclocks; i++) { + struct camss_clock *clock =3D &tpg->clock[i]; + + clock->clk =3D devm_clk_get(dev, res->clock[i]); + if (IS_ERR(clock->clk)) + return PTR_ERR(clock->clk); + + clock->name =3D res->clock[i]; + + clock->nfreqs =3D 0; + while (res->clock_rate[i][clock->nfreqs]) + clock->nfreqs++; + + if (!clock->nfreqs) { + clock->freq =3D NULL; + continue; + } + + clock->freq =3D devm_kcalloc(dev, + clock->nfreqs, + sizeof(*clock->freq), + GFP_KERNEL); + if (!clock->freq) + return -ENOMEM; + + for (j =3D 0; j < clock->nfreqs; j++) + clock->freq[j] =3D res->clock_rate[i][j]; + } + } + + return 0; +} + +/* + * tpg_link_setup - Setup tpg connections + * @entity: Pointer to media entity structure + * @local: Pointer to local pad + * @remote: Pointer to remote pad + * @flags: Link flags + * + * Rreturn 0 on success + */ +static int tpg_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + if (flags & MEDIA_LNK_FL_ENABLED) + if (media_pad_remote_pad_first(local)) + return -EBUSY; + + return 0; +} + +static const struct v4l2_subdev_core_ops tpg_core_ops =3D { + .s_power =3D tpg_set_power, +}; + +static const struct v4l2_subdev_video_ops tpg_video_ops =3D { + .s_stream =3D tpg_set_stream, +}; + +static const struct v4l2_subdev_pad_ops tpg_pad_ops =3D { + .enum_mbus_code =3D tpg_enum_mbus_code, + .enum_frame_size =3D tpg_enum_frame_size, + .get_fmt =3D tpg_get_format, + .set_fmt =3D tpg_set_format, +}; + +static const struct v4l2_subdev_ops tpg_v4l2_ops =3D { + .core =3D &tpg_core_ops, + .video =3D &tpg_video_ops, + .pad =3D &tpg_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops tpg_v4l2_internal_ops =3D { + .open =3D tpg_init_formats, +}; + +static const struct media_entity_operations tpg_media_ops =3D { + .link_setup =3D tpg_link_setup, + .link_validate =3D v4l2_subdev_link_validate, +}; + +/* + * msm_tpg_register_entity - Register subdev node for tpg module + * @tpg: tpg device + * @v4l2_dev: V4L2 device + * + * Return 0 on success or a negative error code otherwise + */ +int msm_tpg_register_entity(struct tpg_device *tpg, + struct v4l2_device *v4l2_dev) +{ + struct v4l2_subdev *sd =3D &tpg->subdev; + struct media_pad *pads =3D tpg->pads; + struct device *dev =3D tpg->camss->dev; + int ret; + + v4l2_subdev_init(sd, &tpg_v4l2_ops); + sd->internal_ops =3D &tpg_v4l2_internal_ops; + sd->flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; + snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", + MSM_TPG_NAME, tpg->id); + sd->grp_id =3D TPG_GUP_ID; + v4l2_set_subdevdata(sd, tpg); + + ret =3D v4l2_ctrl_handler_init(&tpg->ctrls, 1); + if (ret < 0) { + dev_err(dev, "Failed to init ctrl handler: %d\n", ret); + return ret; + } + + tpg->testgen_mode =3D v4l2_ctrl_new_std_menu_items(&tpg->ctrls, + &tpg_ctrl_ops, V4L2_CID_TEST_PATTERN, + tpg->testgen.nmodes, 0, 0, + tpg->testgen.modes); + + if (tpg->ctrls.error) { + dev_err(dev, "Failed to init ctrl: %d\n", tpg->ctrls.error); + ret =3D tpg->ctrls.error; + goto free_ctrl; + } + + tpg->subdev.ctrl_handler =3D &tpg->ctrls; + + ret =3D tpg_init_formats(sd, NULL); + if (ret < 0) { + dev_err(dev, "Failed to init format: %d\n", ret); + goto free_ctrl; + } + + pads[MSM_TPG_PAD_SINK].flags =3D MEDIA_PAD_FL_SINK; + pads[MSM_TPG_PAD_SRC].flags =3D MEDIA_PAD_FL_SOURCE; + + sd->entity.function =3D MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; + sd->entity.ops =3D &tpg_media_ops; + ret =3D media_entity_pads_init(&sd->entity, MSM_TPG_PADS_NUM, pads); + if (ret < 0) { + dev_err(dev, "Failed to init media entity: %d\n", ret); + goto free_ctrl; + } + + ret =3D v4l2_device_register_subdev(v4l2_dev, sd); + if (ret < 0) { + dev_err(dev, "Failed to register subdev: %d\n", ret); + media_entity_cleanup(&sd->entity); + goto free_ctrl; + } + + return 0; + +free_ctrl: + v4l2_ctrl_handler_free(&tpg->ctrls); + + return ret; +} + +/* + * msm_tpg_unregister_entity - Unregister tpg module subdev node + * @tpg: tpg device + */ +void msm_tpg_unregister_entity(struct tpg_device *tpg) +{ + v4l2_device_unregister_subdev(&tpg->subdev); + media_entity_cleanup(&tpg->subdev.entity); + v4l2_ctrl_handler_free(&tpg->ctrls); +} diff --git a/drivers/media/platform/qcom/camss/camss-tpg.h b/drivers/media/= platform/qcom/camss/camss-tpg.h new file mode 100644 index 0000000000000000000000000000000000000000..c40c10cc4ad1d7967c5d9dd878a= 8d69177b2281f --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * camss-tpg.h + * + * Qualcomm MSM Camera Subsystem - TPG Module + * + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef QC_MSM_CAMSS_TPG_H +#define QC_MSM_CAMSS_TPG_H + +#include +#include +#include +#include +#include +#include + +#define MSM_TPG_PAD_SINK 0 +#define MSM_TPG_PAD_SRC 1 +#define MSM_TPG_PADS_NUM 2 + +#define DATA_TYPE_RAW_8BIT 0x2a +#define DATA_TYPE_RAW_10BIT 0x2b +#define DATA_TYPE_RAW_12BIT 0x2c + +#define ENCODE_FORMAT_UNCOMPRESSED_8_BIT 0x1 +#define ENCODE_FORMAT_UNCOMPRESSED_10_BIT 0x2 +#define ENCODE_FORMAT_UNCOMPRESSED_12_BIT 0x3 +#define ENCODE_FORMAT_UNCOMPRESSED_14_BIT 0x4 +#define ENCODE_FORMAT_UNCOMPRESSED_16_BIT 0x5 +#define ENCODE_FORMAT_UNCOMPRESSED_20_BIT 0x6 +#define ENCODE_FORMAT_UNCOMPRESSED_24_BIT 0x7 + +#define TPG_GUP_ID 0 +#define MSM_TPG_NAME "msm_tpg" + +enum tpg_testgen_mode { + TPG_PAYLOAD_MODE_DISABLED =3D 0, + TPG_PAYLOAD_MODE_INCREMENTING =3D 1, + TPG_PAYLOAD_MODE_ALTERNATING_55_AA =3D 2, + TPG_PAYLOAD_MODE_RANDOM =3D 5, + TPG_PAYLOAD_MODE_USER_SPECIFIED =3D 6, + TPG_PAYLOAD_MODE_COLOR_BARS =3D 9, + TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1 =3D 9, +}; + +struct tpg_testgen_config { + enum tpg_testgen_mode mode; + const char * const*modes; + u8 nmodes; +}; + +struct tpg_format_info { + u32 code; + u8 data_type; + u8 encode_format; +}; + +struct tpg_formats { + unsigned int nformats; + const struct tpg_format_info *formats; +}; + +struct tpg_device; + +struct tpg_hw_ops { + void (*configure_stream)(struct tpg_device *tpg, u8 enable); + + int (*configure_testgen_pattern)(struct tpg_device *tpg, s32 val); + + u32 (*hw_version)(struct tpg_device *tpg); + + int (*reset)(struct tpg_device *tpg); + + void (*subdev_init)(struct tpg_device *tpg); +}; + +struct tpg_subdev_resources { + u8 lane_cnt; + u8 vc_cnt; + const struct tpg_formats *formats; + const struct tpg_hw_ops *hw_ops; +}; + +struct tpg_device { + struct camss *camss; + u8 id; + struct v4l2_subdev subdev; + struct media_pad pads[MSM_TPG_PADS_NUM]; + void __iomem *base; + struct camss_clock *clock; + int nclocks; + struct tpg_testgen_config testgen; + struct v4l2_mbus_framefmt fmt[MSM_TPG_PADS_NUM]; + struct v4l2_ctrl_handler ctrls; + struct v4l2_ctrl *testgen_mode; + const struct tpg_subdev_resources *res; + const struct tpg_format *formats; + unsigned int nformats; +}; + +struct camss_subdev_resources; + +const struct tpg_format_info *tpg_get_fmt_entry(struct tpg_device *tpg, + const struct tpg_format_info *formats, + unsigned int nformats, + u32 code); + +int msm_tpg_subdev_init(struct camss *camss, + struct tpg_device *tpg, + const struct camss_subdev_resources *res, u8 id); + +int msm_tpg_register_entity(struct tpg_device *tpg, + struct v4l2_device *v4l2_dev); + +void msm_tpg_unregister_entity(struct tpg_device *tpg); + +extern const char * const testgen_payload_modes[]; + +extern const struct tpg_formats tpg_formats_gen1; + +extern const struct tpg_hw_ops tpg_ops_gen1; + +#endif /* QC_MSM_CAMSS_TPG_H */ diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index a70fbc78ccc307c0abc2f3c834fb1e2dafd83c6b..9a66f3a90c02b4cc475c4d30332= 05feb7e98f5d3 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -21,6 +21,7 @@ #include "camss-csid.h" #include "camss-csiphy.h" #include "camss-ispif.h" +#include "camss-tpg.h" #include "camss-vfe.h" #include "camss-format.h" =20 @@ -51,6 +52,7 @@ struct camss_subdev_resources { char *interrupt[CAMSS_RES_MAX]; union { struct csiphy_subdev_resources csiphy; + struct tpg_subdev_resources tpg; struct csid_subdev_resources csid; struct vfe_subdev_resources vfe; }; @@ -101,6 +103,7 @@ struct camss_resources { enum camss_version version; const char *pd_name; const struct camss_subdev_resources *csiphy_res; + const struct camss_subdev_resources *tpg_res; const struct camss_subdev_resources *csid_res; const struct camss_subdev_resources *ispif_res; const struct camss_subdev_resources *vfe_res; @@ -108,6 +111,7 @@ struct camss_resources { const struct resources_icc *icc_res; const unsigned int icc_path_num; const unsigned int csiphy_num; + const unsigned int tpg_num; const unsigned int csid_num; const unsigned int vfe_num; }; @@ -118,6 +122,7 @@ struct camss { struct media_device media_dev; struct device *dev; struct csiphy_device *csiphy; + struct tpg_device *tpg; struct csid_device *csid; struct ispif_device *ispif; struct vfe_device *vfe; --=20 2.34.1 From nobody Mon Feb 9 04:31:38 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEE8130E83B for ; Fri, 17 Oct 2025 05:06:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760677582; cv=none; b=l2/REckvfB15aJNpLf8FneeHii8HmamixmAnuIjTG1U6HpyAvxeyRM4iU+CrDh/no/1WXUigcYxpHUIU8l3kOnLvK/Na2Av9s9l53fjyDv0Zdfhh5nyu7wrIB94o4cu72PRUYXTqZfDF4OmAG3JapkVuxr/T9+GSoei4SErZcts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760677582; c=relaxed/simple; bh=gcL/fGPQekLTQNIGUzZcdgTs72eyqB3Ncf8Yq2nY0h4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RP7mtIvbs9m8w9Ov/GjuBghUxIy7MfRyvZUarnth6ct3ohbjTKbZd28yeGCeuHegMWJBtnnt82KCqiTpBTgqAmjndX9HCxVl7xZULZjacrib/f0wLE67oQ++EB3jqUWiq2t0OjtXWUJM0cmdoEWdxLl4mZHECmURqvoIblSuFjI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cHiQ2Fo2; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cHiQ2Fo2" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 59GKLZ25009578 for ; Fri, 17 Oct 2025 05:06:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 25vQWjik0NkorLXRn5b4wPZ1S82r4D/v+C/waXiEV9Q=; b=cHiQ2Fo2xS7+oPKa NY5FJacszjQdOVgS44VvvuEy8IfPAPINeNIkQnehgP0b9mQvuOLO1aR9cvOR6V4T nyhPm60JdrtHIV58I1hTZ1JNkhOFLjF3ZHhQZgenA2n+HzXJFxkAxYzKhO4L3QfC gl2Rn+7bC4BGqrc5Fuu8DWyTRYHKNjaNkLMTztNGH6Vw1weQ8fVoG3IC5rw3nZ36 Uu1DndDm+6qPpu3aVSr1ffWX4t3Eq9z0Qbkr2+/vnPszVLniFf13XPIkMI+jiozI 6d7uwrbrNCAr/oAPxaBQpXaELCtbsqPhCBs/wzKHHHzd/fza5TALc5kuskqPQ4KD S2dg9A== Received: from mail-qv1-f71.google.com (mail-qv1-f71.google.com [209.85.219.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 49qg0caste-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 17 Oct 2025 05:06:19 +0000 (GMT) Received: by mail-qv1-f71.google.com with SMTP id 6a1803df08f44-87c14264340so26222536d6.2 for ; Thu, 16 Oct 2025 22:06:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760677578; x=1761282378; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=25vQWjik0NkorLXRn5b4wPZ1S82r4D/v+C/waXiEV9Q=; b=RkcpcGPHZ0KBMJpT38C6majC14Tbe4Qpk5sYuSmkmqFM968IMRnhuoiGu50gsTBbFY Jj6EfadnrcP+DU4CUTyps1rNHmGxfccb/JXxJMMz7NW5uPtpBXqHifrMP805RKpfJIFK RsLYoUKJcnaRSRn6mxVCvabEJrZ4tl+bHe0AEAlVWIJQO67tgo1mcvZdQRAXuHTX7jyL kjBNdsBWQjfBAfQ8X0Pjmrqju5xUBpyUFhJmZxzDcI66xtRoAuKX9YjpgTLyd/L42Rwo uwdWsnNgCqrPaa53SOhIHKritMTjmZsevzgQbg/ygvOXdn+R+ygIvXXyP2EyrQmBB6+e /mkw== X-Gm-Message-State: AOJu0YwaeaeX2BMDgmiQzuvJgF/GfDNgDv4rYIOVsbShgV/dhvNvb5X/ pDnvfOi/e43ugOXMzKvOdTwhYolcu/CF6u8lHs3ZctgN9H8FSTfkfJhE8CRHngUhHtNuizw6jhc gFgg5/xNulTcuZGg4czlbChswL1sn/vThKSHRcMrZn6GbSQAbOd0Esj+AjJOzMj08dXM= X-Gm-Gg: ASbGncv2J6ogEyZhoEywoFFVeTu4klf07Z0Fc8kIAY1qkP95Y5Y2x0PfDzpzp/nIPx+ 756tYo4yg5bx9RSZfHh+yJ1ixAz5bWDh0iOAusS5bJf6MrG+yr4c+zi5T2mMGbvhY62smbHbqf5 zVx00pECXuu7V1dWaLI+6CD6YTSCVLpFwukZuAPyZXOC/QEvmUWtVh9dWU8SPOzmeUb6fY2E7Ik gqaz25xs3Eukn2Kfz0d35TcMvRbZcGLYQDxxDsfhdDSbsEKNkaH6E8ewYRcFwymJUQH1g8NOw3G WKcdZeDyB7ByMYGvchH1x+wCbL3q6Q0Ek42vzmfDYlOf3Obj0piKCWTUym6xOyEAHeJ+1LQgYBN Nshlx0/z4R1HUDXGB1KGGse73EOqDZWt5jLHj/FI0MbecSzlXh9KRZJvhquTcaw6CAQ== X-Received: by 2002:ac8:578b:0:b0:4e5:6c5e:430a with SMTP id d75a77b69052e-4e89d3a47c8mr36061821cf.64.1760677578241; Thu, 16 Oct 2025 22:06:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGWoFJ0er3XmNA2MfPambnFGk+UHtKnSzrmBzbda9gHXA03fZsIi/ofXmuuwW4bOSbI87KnLg== X-Received: by 2002:ac8:578b:0:b0:4e5:6c5e:430a with SMTP id d75a77b69052e-4e89d3a47c8mr36061541cf.64.1760677577565; Thu, 16 Oct 2025 22:06:17 -0700 (PDT) Received: from WENMLIU-LAB01.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-87c0128c9d8sm57641916d6.33.2025.10.16.22.06.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Oct 2025 22:06:17 -0700 (PDT) From: Wenmeng Liu Date: Fri, 17 Oct 2025 13:06:02 +0800 Subject: [PATCH v5 2/3] media: qcom: camss: Add link support for TPG Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251017-camss_tpg-v5-2-cafe3ad42163@oss.qualcomm.com> References: <20251017-camss_tpg-v5-0-cafe3ad42163@oss.qualcomm.com> In-Reply-To: <20251017-camss_tpg-v5-0-cafe3ad42163@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760677563; l=7448; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=gcL/fGPQekLTQNIGUzZcdgTs72eyqB3Ncf8Yq2nY0h4=; b=Heo9ljOtLQ/JcSwEKehl45lcRkeQ9+98sYsrLAB3G/8XiHBm9U+DwtH61jDTyI40g6e7sT+wo 8OwvzboEzMbA7s6sM5EwqbQ3iH2aUibjcUR5/u2OjohrU5/ysKmnPW5 X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-GUID: l3rIh5RbszEBhmH7tBit6O-8J353Nozj X-Proofpoint-ORIG-GUID: l3rIh5RbszEBhmH7tBit6O-8J353Nozj X-Authority-Analysis: v=2.4 cv=eaIwvrEH c=1 sm=1 tr=0 ts=68f1cecb cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=D-OMaI2VJto731AKaP4A:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDExMDAyMiBTYWx0ZWRfX1AD7gLncPDqL ckFrPk/82gGaOSbl5tndrgKHjuImzECgfckj2p88iDBoxRgE/mizYa12bH+Ka4CGLUXaLWbuYRl /sOfSUNSsnEG3KmZDTw3yGHdjYF7A/nAuO1km34AkLubIeHZCtNrMld1w6CJ3lNEKBs5XExWRiN loJ1ET5qujQzrM3ViL9xwqrrY/p7rm2CREUjlDB8u+G1LDy+BgQcKpgd5coFVghcdscqyGpOVea ci5vD3vjmPe3UnAhBUCn0Nfxs3K5qldvV7ri85esg9yJ7Np1R8jCZgZRRFenbt6Dz0r/GXrH785 ZTcUdqZ5eNg7fpzh8uccZLPXHYEeklT8CYIfN6QpHI1psVmgogYTaPoBkCK2I0Qic4Q4d70Xp6L v0XongX6nB3PngnbXMRfvaZy5hB1Ug== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-17_02,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510110022 TPG is connected to the csid as an entity, the link needs to be adapted. Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/camss-csid.c | 43 +++++++++++++------- drivers/media/platform/qcom/camss/camss-csiphy.c | 1 + drivers/media/platform/qcom/camss/camss-csiphy.h | 2 + drivers/media/platform/qcom/camss/camss.c | 52 ++++++++++++++++++++= ++++ 4 files changed, 84 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media= /platform/qcom/camss/camss-csid.c index 5284b5857368c37c202cd89dad6ae8042b637537..196cbc0b60e9bf95a06b053c69c= 967e345ffcd4b 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -35,6 +35,8 @@ #define HW_VERSION_REVISION 16 #define HW_VERSION_GENERATION 28 =20 +#define LANE_CFG_BITWIDTH 4 + #define MSM_CSID_NAME "msm_csid" =20 const char * const csid_testgen_modes[] =3D { @@ -1227,18 +1229,22 @@ void msm_csid_get_csid_id(struct media_entity *enti= ty, u8 *id) } =20 /* - * csid_get_lane_assign - Calculate CSI2 lane assign configuration paramet= er - * @lane_cfg - CSI2 lane configuration + * csid_get_lane_assign - Calculate lane assign by csiphy/tpg lane num + * @num: lane num + * @pos_array: Array of lane positions * * Return lane assign */ -static u32 csid_get_lane_assign(struct csiphy_lanes_cfg *lane_cfg) +static u32 csid_get_lane_assign(int num, struct csiphy_lanes_cfg *lane_cfg) { u32 lane_assign =3D 0; + int pos; int i; =20 - for (i =3D 0; i < lane_cfg->num_data; i++) - lane_assign |=3D lane_cfg->data[i].pos << (i * 4); + for (i =3D 0; i < num; i++) { + pos =3D lane_cfg ? lane_cfg->data[i].pos : i; + lane_assign |=3D pos << (i * LANE_CFG_BITWIDTH); + } =20 return lane_assign; } @@ -1266,6 +1272,7 @@ static int csid_link_setup(struct media_entity *entit= y, struct csid_device *csid; struct csiphy_device *csiphy; struct csiphy_lanes_cfg *lane_cfg; + struct tpg_device *tpg; =20 sd =3D media_entity_to_v4l2_subdev(entity); csid =3D v4l2_get_subdevdata(sd); @@ -1277,18 +1284,26 @@ static int csid_link_setup(struct media_entity *ent= ity, return -EBUSY; =20 sd =3D media_entity_to_v4l2_subdev(remote->entity); - csiphy =3D v4l2_get_subdevdata(sd); + if (sd->grp_id =3D=3D TPG_GUP_ID) { + tpg =3D v4l2_get_subdevdata(sd); =20 - /* If a sensor is not linked to CSIPHY */ - /* do no allow a link from CSIPHY to CSID */ - if (!csiphy->cfg.csi2) - return -EPERM; + csid->phy.lane_cnt =3D tpg->res->lane_cnt; + csid->phy.csiphy_id =3D tpg->id; + csid->phy.lane_assign =3D csid_get_lane_assign(csid->phy.lane_cnt, NULL= ); + } else { + csiphy =3D v4l2_get_subdevdata(sd); =20 - csid->phy.csiphy_id =3D csiphy->id; + /* If a sensor is not linked to CSIPHY */ + /* do no allow a link from CSIPHY to CSID */ + if (!csiphy->cfg.csi2) + return -EPERM; =20 - lane_cfg =3D &csiphy->cfg.csi2->lane_cfg; - csid->phy.lane_cnt =3D lane_cfg->num_data; - csid->phy.lane_assign =3D csid_get_lane_assign(lane_cfg); + csid->phy.csiphy_id =3D csiphy->id; + + lane_cfg =3D &csiphy->cfg.csi2->lane_cfg; + csid->phy.lane_cnt =3D lane_cfg->num_data; + csid->phy.lane_assign =3D csid_get_lane_assign(lane_cfg->num_data, lane= _cfg); + } } /* Decide which virtual channels to enable based on which source pads are= enabled */ if (local->flags & MEDIA_PAD_FL_SOURCE) { diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/med= ia/platform/qcom/camss/camss-csiphy.c index 2de97f58f9ae4f91e8bba39dcadf92bea8cf6f73..680580d7fe46a215777f3fa1b34= 7f4297deea024 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -799,6 +799,7 @@ int msm_csiphy_register_entity(struct csiphy_device *cs= iphy, sd->flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE; snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", MSM_CSIPHY_NAME, csiphy->id); + sd->grp_id =3D CSIPHY_GUP_ID; v4l2_set_subdevdata(sd, csiphy); =20 ret =3D csiphy_init_formats(sd, NULL); diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/med= ia/platform/qcom/camss/camss-csiphy.h index 895f80003c441dcacf98435f91567f90afa29279..b7bcf2bdd2124f77b5354b15b33= aa1e0983143e8 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -21,6 +21,8 @@ #define MSM_CSIPHY_PAD_SRC 1 #define MSM_CSIPHY_PADS_NUM 2 =20 +#define CSIPHY_GUP_ID 1 + struct csiphy_lane { u8 pos; u8 pol; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 2fbcd0e343aac9620a5a30719c42e1b887cf34ed..2ede19e1347ae32f2f6919905b5= 35352bcd134be 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -3691,6 +3691,19 @@ static int camss_init_subdevices(struct camss *camss) } } =20 + if (camss->tpg) { + for (i =3D 0; i < camss->res->tpg_num; i++) { + ret =3D msm_tpg_subdev_init(camss, &camss->tpg[i], + &res->tpg_res[i], i); + if (ret < 0) { + dev_err(camss->dev, + "Failed to init tpg%d sub-device: %d\n", + i, ret); + return ret; + } + } + } + /* note: SM8250 requires VFE to be initialized before CSID */ for (i =3D 0; i < camss->res->vfe_num; i++) { ret =3D msm_vfe_subdev_init(camss, &camss->vfe[i], @@ -3779,6 +3792,23 @@ static int camss_link_entities(struct camss *camss) } } =20 + for (i =3D 0; i < camss->res->tpg_num; i++) { + for (j =3D 0; j < camss->res->csid_num; j++) { + ret =3D media_create_pad_link(&camss->tpg[i].subdev.entity, + MSM_TPG_PAD_SRC, + &camss->csid[j].subdev.entity, + MSM_CSID_PAD_SINK, + 0); + if (ret < 0) { + camss_link_err(camss, + camss->tpg[i].subdev.entity.name, + camss->csid[j].subdev.entity.name, + ret); + return ret; + } + } + } + if (camss->ispif) { for (i =3D 0; i < camss->res->csid_num; i++) { for (j =3D 0; j < camss->ispif->line_num; j++) { @@ -3883,6 +3913,19 @@ static int camss_register_entities(struct camss *cam= ss) } } =20 + if (camss->tpg) { + for (i =3D 0; i < camss->res->tpg_num; i++) { + ret =3D msm_tpg_register_entity(&camss->tpg[i], + &camss->v4l2_dev); + if (ret < 0) { + dev_err(camss->dev, + "Failed to register tpg%d entity: %d\n", + i, ret); + goto err_reg_tpg; + } + } + } + for (i =3D 0; i < camss->res->csid_num; i++) { ret =3D msm_csid_register_entity(&camss->csid[i], &camss->v4l2_dev); @@ -3926,6 +3969,10 @@ static int camss_register_entities(struct camss *cam= ss) for (i--; i >=3D 0; i--) msm_csid_unregister_entity(&camss->csid[i]); =20 + i =3D camss->res->tpg_num; +err_reg_tpg: + for (i--; i >=3D 0; i--) + msm_tpg_unregister_entity(&camss->tpg[i]); i =3D camss->res->csiphy_num; err_reg_csiphy: for (i--; i >=3D 0; i--) @@ -3947,6 +3994,11 @@ static void camss_unregister_entities(struct camss *= camss) for (i =3D 0; i < camss->res->csiphy_num; i++) msm_csiphy_unregister_entity(&camss->csiphy[i]); =20 + if (camss->tpg) { + for (i =3D 0; i < camss->res->tpg_num; i++) + msm_tpg_unregister_entity(&camss->tpg[i]); + } + for (i =3D 0; i < camss->res->csid_num; i++) msm_csid_unregister_entity(&camss->csid[i]); =20 --=20 2.34.1 From nobody Mon Feb 9 04:31:38 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5707D30F53E for ; Fri, 17 Oct 2025 05:06:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760677586; cv=none; b=hC+wdBVswCgCzhaVX6cDXbQFVyuD3Gom/Mde6+9TsRWycI+ryX+ONm+IkWkmnt3KKhjzY/9PY/xX8gcfBi9HbKnX9KBTzLLvUGafNToBcT1UKmwL8yt3aFvCGkEJ2o1ggb37vHCQL2MHYGKFyJWSG0+KeBpr/OqV54s5eWdfaTI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760677586; c=relaxed/simple; bh=BbxqArpZujgief7ydqM3Itr2/h7C8RDvqE3q8AqcUrU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fv9Flx6UQjlbg/6nrTnjEvMAgSnSEHwsFFpQLKqjWTVoxAIDzs+6eU/5EpPNOqjb35uMSdNkgLAEhf6Yd2i2UNiN2Ki0TobvJL5ZSu+Y4SvfAGqZRTt00hw2+i8kDtxGigOjlW6VLLIabPXthvStLbB3+EK+06+s4SBp6d4DRVc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=UkzfYaF0; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="UkzfYaF0" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 59GKLQi1025265 for ; Fri, 17 Oct 2025 05:06:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= J/v4quuUw+RjaUbXDOUK+PnQy+lYXBpTQGM+trB+qdg=; b=UkzfYaF0oKxMNmZf LoRPRRf+OFWN2Z8+/ig/GRbRav2dTCjHKzUJOi37bM2MMcI9PhrZDfKQo486701R oSn82Fwhy+GMqcp4vzOwztCgudZW1X3SfgtkMct46NoanTT1w5ipWk+Dcz4viN5r ol9/5377bVbHjXhQFKkfvOcfnklUiF7eZKjfioIGZlLJZ2u82T8XF1oA24AYJZzW QQojDL1Zx32NhW6rXIOL9stNw6Xnffyujijkq1Vfqz1WXt+NQx6M9UKT7AwbdLL+ O9EA3AJZu4f/oCwL0CeBIiE0fAQE1eiZOBxUNYlEUxz9sDKKBlx879UpH9ZDsBHn qxazng== Received: from mail-qv1-f70.google.com (mail-qv1-f70.google.com [209.85.219.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 49qfdkjvjs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 17 Oct 2025 05:06:23 +0000 (GMT) Received: by mail-qv1-f70.google.com with SMTP id 6a1803df08f44-87c14264340so26223046d6.2 for ; Thu, 16 Oct 2025 22:06:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760677582; x=1761282382; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J/v4quuUw+RjaUbXDOUK+PnQy+lYXBpTQGM+trB+qdg=; b=o7SMAohDBAasbe6wKcSap6Xc2eq9LFlujKO6gG5i6Rb0IPHda7aO7fxcHKTD+RPjIs K1ONTWBRpTNM0CAiaOjqsvAcdMI+KTk78SyemKAKvPloELERqV9EM0R2Gi4uTX0DhF/N y8uD7uzogYzKgYimlMKYWlt/OGqIopfagoR3FnuaCOnnGmabQ2hMxUhPHQ4YF8/j43q/ TCWCk8XHj0r8ejRaRsFlsAxCC1SgvNO6kl+3xc43vHGuumWev84fViNV5f9ZRqLJ/9EB ksBqOEA+iYZ270MUomvktPPxvwOAvCnC+MXPksk0fZMdOFNn3iaHB3RrvlKLJKg/2cpv ltEw== X-Gm-Message-State: AOJu0Yy3Fk4WHU45iVXFCmSikkg6ptSMzb8dIFq7Xn4GdthTxGxj144Z oYZQx2DwpRyeUH+gd1dbICo81VRTuP1lH4EMt0VicUe5eVv1NScya49/Zq338BGG0zQISvZDxJf u5yXfQ4A3JR7l0S7ETYbWeJQJp96jjm2mRaHyzeMhapNPl55nB4ih2zuPbHKHGb777hU= X-Gm-Gg: ASbGncuL/f85OZKrvMcOqP7oYBxYgseb2IbR5g3wkOgPTtT7TXXlOpGQOeBtwWTAYh/ J7qrXRrzLmndjibRTFUCqpWAU5KgYrj3/uGUplRMq2YtjmChbV3HTO3TKkUidRXmMV8DnGywzWY 7U10vw8lEOSPDqsQFKzlgn447VQIXGSRZLJnvXLtr47snL6JVbQfnueRw+oae9PGHL03Vw7yfFO WV5EOWtn2/n5jfqFIWxFpaddP0hO6TrtnOfvrbMGGqA5V6YFqkA2yPmcBLYZfm7JyLUtbq9f+HK 7iXo8zvsexKpXA5FKBCx4vZ1aHu2WGyLfyVcOYj0BSgk0uUG0Xc9j5AAgGsOYLxNhwpDa0vTR3B 4ekvRDME932mYYmBO/VVjy2RNAUw3g6qPBpNFXlWb6Bd4qCBzALe4FjpugPAlpYZvQg== X-Received: by 2002:a05:6214:43c4:b0:87c:20f5:84e2 with SMTP id 6a1803df08f44-87c20f5873cmr44080136d6.25.1760677582127; Thu, 16 Oct 2025 22:06:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IELAxtIRSGqAXjFQy6MLCXx7B0d3VbWr1P43dLXizUbawOPzNA9SL/c/9A4nSOwErpS2MY2Fw== X-Received: by 2002:a05:6214:43c4:b0:87c:20f5:84e2 with SMTP id 6a1803df08f44-87c20f5873cmr44079796d6.25.1760677581662; Thu, 16 Oct 2025 22:06:21 -0700 (PDT) Received: from WENMLIU-LAB01.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-87c0128c9d8sm57641916d6.33.2025.10.16.22.06.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Oct 2025 22:06:21 -0700 (PDT) From: Wenmeng Liu Date: Fri, 17 Oct 2025 13:06:03 +0800 Subject: [PATCH v5 3/3] media: qcom: camss: tpg: Add TPG support for LeMans and Monaco Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251017-camss_tpg-v5-3-cafe3ad42163@oss.qualcomm.com> References: <20251017-camss_tpg-v5-0-cafe3ad42163@oss.qualcomm.com> In-Reply-To: <20251017-camss_tpg-v5-0-cafe3ad42163@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760677563; l=13291; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=BbxqArpZujgief7ydqM3Itr2/h7C8RDvqE3q8AqcUrU=; b=yMccrbq6PzHNcW6Lh4WshmaLlphd82ewzRpsPgwQ5b1d0Z+rB5t19VffkbrY7zogfn+l8qnHO lg/ThrnPOXeCNNaBFJQriwLtiewBWjAfUzDbiRT6FcHguAw/fPnGQoK X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-ORIG-GUID: K-_7TbaNgXG1rl3WX_Z3XdjGg73NPiM8 X-Authority-Analysis: v=2.4 cv=MrNfKmae c=1 sm=1 tr=0 ts=68f1cecf cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=PpfPPmXnh0snnf3BrX0A:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-GUID: K-_7TbaNgXG1rl3WX_Z3XdjGg73NPiM8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDExMDAxOCBTYWx0ZWRfX2V7qEbl8Weli EcRPhj464V1cl2ddaD/EEmYYafnkwkNBKN7uDO5+v7NIk6twAMbo6TRCCawJNBYxqnR7UFV6R4j Yzn+jbumnGqsUfWno+sUTryqv8WBK2nGCDOzPq9qqg2b0REHpDiFq0guNcHBY29iUaG+P75rx8q UKNJl1n5nCk4DAhclQ/vwMeMVn4FOv8C70Tp5c+WgviTi/m6XKMU42Yo2CueZ0AsS3iPNMD4hte 7hCeMzEM3/LSAKzuwEhaC77bvrAE+vOpWOrQO76Ikpdf71FBzA0vqQG1jaxET78dMbIe4gngfR+ 1ngFLdiExqdReTH6eNP+wDZEU0xmlkPGVhGaue0NjeXtrNdbFQu++BK148tRP/Po/WNn6reoOg3 nM2Z1kzbtxskql9S3jRWFYYzdm6Nfg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-17_02,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 clxscore=1015 adultscore=0 phishscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510110018 Add support for TPG found on LeMans and Monaco. Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/Makefile | 1 + .../media/platform/qcom/camss/camss-csid-gen3.c | 17 ++ drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 220 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss.c | 67 +++++++ 4 files changed, 305 insertions(+) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 0eda4b18ad0e93f5e63135fabd5a02ae67bcd5ad..28bc3d9ba16dfa34a8fd35973be= ed0c3f2b67e00 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -27,5 +27,6 @@ qcom-camss-objs +=3D \ camss-video.o \ camss-format.o \ camss-tpg.o \ + camss-tpg-gen1.o \ =20 obj-$(CONFIG_VIDEO_QCOM_CAMSS) +=3D qcom-camss.o diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/= media/platform/qcom/camss/camss-csid-gen3.c index 664245cf6eb0cac662b02f8b920cd1c72db0aeb2..8e0b0cbaa0010f4b4a156877ac2= fe805e5c4422e 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -66,6 +66,8 @@ #define CSI2_RX_CFG0_VC_MODE 3 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSI2_RX_CFG0_TPG_NUM_EN 27 +#define CSI2_RX_CFG0_TPG_NUM_SEL 28 =20 #define CSID_CSI2_RX_CFG1 0x204 #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) @@ -109,11 +111,26 @@ static void __csid_configure_rx(struct csid_device *c= sid, struct csid_phy_config *phy, int vc) { int val; + struct camss *camss; + struct tpg_device *tpg; =20 + camss =3D csid->camss; val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0= _PHY_NUM_SEL; =20 + if (camss->tpg) { + tpg =3D &camss->tpg[phy->csiphy_id]; + + if (tpg->testgen.mode > 0) { + val |=3D (phy->csiphy_id + 1) << CSI2_RX_CFG0_TPG_NUM_SEL; + val |=3D 1 << CSI2_RX_CFG0_TPG_NUM_EN; + } else { + val |=3D 0 << CSI2_RX_CFG0_TPG_NUM_SEL; + val |=3D 0 << CSI2_RX_CFG0_TPG_NUM_EN; + } + } + writel(val, csid->base + CSID_CSI2_RX_CFG0); =20 val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; diff --git a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c b/drivers/m= edia/platform/qcom/camss/camss-tpg-gen1.c new file mode 100644 index 0000000000000000000000000000000000000000..ba463c16a8436cb40c61d1b483c= 6343c010b9744 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * + * Qualcomm MSM Camera Subsystem - TPG (Test Patter Generator) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include + +#include "camss-tpg.h" +#include "camss.h" + +#define TPG_HW_VERSION 0x0 +# define HW_VERSION_STEPPING GENMASK(15, 0) +# define HW_VERSION_REVISION GENMASK(27, 16) +# define HW_VERSION_GENERATION GENMASK(31, 28) + +#define TPG_HW_STATUS 0x4 + +#define TPG_VC_n_GAIN_CFG(n) (0x60 + (n) * 0x60) + +#define TPG_CTRL 0x64 +# define TPG_CTRL_TEST_EN BIT(0) +# define TPG_CTRL_PHY_SEL BIT(3) +# define TPG_CTRL_NUM_ACTIVE_LANES GENMASK(5, 4) +# define TPG_CTRL_VC_DT_PATTERN_ID GENMASK(8, 6) +# define TPG_CTRL_OVERLAP_SHDR_EN BIT(10) +# define TPG_CTRL_NUM_ACTIVE_VC GENMASK(31, 30) +# define NUM_ACTIVE_VC_0_ENABLED 0 +# define NUM_ACTIVE_VC_0_1_ENABLED 1 +# define NUM_ACTIVE_VC_0_1_2_ENABLED 2 +# define NUM_ACTIVE_VC_0_1_3_ENABLED 3 + +#define TPG_VC_n_CFG0(n) (0x68 + (n) * 0x60) +# define TPG_VC_n_CFG0_VC_NUM GENMASK(4, 0) +# define TPG_VC_n_CFG0_NUM_ACTIVE_DT GENMASK(9, 8) +# define NUM_ACTIVE_SLOTS_0_ENABLED 0 +# define NUM_ACTIVE_SLOTS_0_1_ENABLED 1 +# define NUM_ACTIVE_SLOTS_0_1_2_ENABLED 2 +# define NUM_ACTIVE_SLOTS_0_1_3_ENABLED 3 +# define TPG_VC_n_CFG0_NUM_BATCH GENMASK(15, 12) +# define TPG_VC_n_CFG0_NUM_FRAMES GENMASK(31, 16) + +#define TPG_VC_n_LSFR_SEED(n) (0x6C + (n) * 0x60) + +#define TPG_VC_n_HBI_CFG(n) (0x70 + (n) * 0x60) + +#define TPG_VC_n_VBI_CFG(n) (0x74 + (n) * 0x60) + +#define TPG_VC_n_COLOR_BARS_CFG(n) (0x78 + (n) * 0x60) +# define TPG_VC_n_COLOR_BARS_CFG_PIX_PATTERN GENMASK(2, 0) +# define TPG_VC_n_COLOR_BARS_CFG_QCFA_EN BIT(3) +# define TPG_VC_n_COLOR_BARS_CFG_SPLIT_EN BIT(4) +# define TPG_VC_n_COLOR_BARS_CFG_NOISE_EN BIT(5) +# define TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD GENMASK(13, 8) +# define TPG_VC_n_COLOR_BARS_CFG_XCFA_EN BIT(16) +# define TPG_VC_n_COLOR_BARS_CFG_SIZE_X GENMASK(26, 24) +# define TPG_VC_n_COLOR_BARS_CFG_SIZE_Y GENMASK(30, 28) + +#define TPG_VC_m_DT_n_CFG_0(m, n) (0x7C + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT GENMASK(15, 0) +# define TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH GENMASK(31, 16) + +#define TPG_VC_m_DT_n_CFG_1(m, n) (0x80 + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_1_DATA_TYPE GENMASK(5, 0) +# define TPG_VC_m_DT_n_CFG_1_ECC_XOR_MASK GENMASK(13, 8) +# define TPG_VC_m_DT_n_CFG_1_CRC_XOR_MASK GENMASK(31, 16) + +#define TPG_VC_m_DT_n_CFG_2(m, n) (0x84 + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE GENMASK(3, 0) +# define TPG_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD GENMASK(27, 4) +# define TPG_VC_m_DT_n_CFG_2_ENCODE_FORMAT GENMASK(31, 28) + +#define TPG_VC_n_COLOR_BAR_CFA_COLOR0(n) (0xB0 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR1(n) (0xB4 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR2(n) (0xB8 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR3(n) (0xBC + (n) * 0x60) + +/* Line offset between VC(n) and VC(n-1), n form 1 to 3 */ +#define TPG_VC_n_SHDR_CFG (0x84 + (n) * 0x60) + +#define TPG_CLEAR 0x1F4 + +#define TPG_USER_SPECIFIED_PAYLOAD_DEFAULT 0xBE +#define TPG_HBI_CFG_DEFAULT 0x4701 +#define TPG_VBI_CFG_DEFAULT 0x438 +#define TPG_LFSR_SEED_DEFAULT 0x12345678 +#define TPG_COLOR_BARS_CFG_STANDARD \ + FIELD_PREP(TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD, 0xA) + +static int tpg_stream_on(struct tpg_device *tpg) +{ + struct tpg_testgen_config *tg =3D &tpg->testgen; + struct v4l2_mbus_framefmt *input_format; + const struct tpg_format_info *format; + u8 lane_cnt =3D tpg->res->lane_cnt; + u8 dt_cnt =3D 0; + u8 i; + u32 val; + + /* Loop through all enabled VCs and configure stream for each */ + for (i =3D 0; i < tpg->res->vc_cnt; i++) { + input_format =3D &tpg->fmt[MSM_TPG_PAD_SRC + i]; + format =3D tpg_get_fmt_entry(tpg, + tpg->res->formats->formats, + tpg->res->formats->nformats, + input_format->code); + + val =3D FIELD_PREP(TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT, input_format->heigh= t & 0xffff) | + FIELD_PREP(TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH, input_format->width & = 0xffff); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_0(i, dt_cnt)); + + val =3D FIELD_PREP(TPG_VC_m_DT_n_CFG_1_DATA_TYPE, format->data_type); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_1(i, dt_cnt)); + + val =3D FIELD_PREP(TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE, tg->mode - 1) | + FIELD_PREP(TPG_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD, + TPG_USER_SPECIFIED_PAYLOAD_DEFAULT) | + FIELD_PREP(TPG_VC_m_DT_n_CFG_2_ENCODE_FORMAT, format->encode_forma= t); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_2(i, dt_cnt)); + + writel(TPG_COLOR_BARS_CFG_STANDARD, tpg->base + TPG_VC_n_COLOR_BARS_CFG(= i)); + + writel(TPG_HBI_CFG_DEFAULT, tpg->base + TPG_VC_n_HBI_CFG(i)); + writel(TPG_VBI_CFG_DEFAULT, tpg->base + TPG_VC_n_VBI_CFG(i)); + + writel(TPG_LFSR_SEED_DEFAULT, tpg->base + TPG_VC_n_LSFR_SEED(i)); + + /* configure one DT, infinite frames */ + val =3D FIELD_PREP(TPG_VC_n_CFG0_VC_NUM, i) | + FIELD_PREP(TPG_VC_n_CFG0_NUM_FRAMES, 0); + writel(val, tpg->base + TPG_VC_n_CFG0(i)); + } + + val =3D FIELD_PREP(TPG_CTRL_TEST_EN, 1) | + FIELD_PREP(TPG_CTRL_PHY_SEL, 0) | + FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) | + FIELD_PREP(TPG_CTRL_VC_DT_PATTERN_ID, 0) | + FIELD_PREP(TPG_CTRL_NUM_ACTIVE_VC, tpg->res->vc_cnt - 1); + writel(val, tpg->base + TPG_CTRL); + + return 0; +} + +static void tpg_stream_off(struct tpg_device *tpg) +{ + writel(0, tpg->base + TPG_CTRL); + writel(1, tpg->base + TPG_CLEAR); +} + +static void tpg_configure_stream(struct tpg_device *tpg, u8 enable) +{ + if (enable) + tpg_stream_on(tpg); + else + tpg_stream_off(tpg); +} + +static int tpg_configure_testgen_pattern(struct tpg_device *tpg, s32 val) +{ + if (val > 0 && val <=3D TPG_PAYLOAD_MODE_COLOR_BARS) + tpg->testgen.mode =3D val; + + return 0; +} + +/* + * tpg_hw_version - tpg hardware version query + * @tpg: tpg device + * + * Return HW version or error + */ +static u32 tpg_hw_version(struct tpg_device *tpg) +{ + u32 hw_version; + u32 hw_gen; + u32 hw_rev; + u32 hw_step; + + hw_version =3D readl(tpg->base + TPG_HW_VERSION); + hw_gen =3D FIELD_GET(HW_VERSION_GENERATION, hw_version); + hw_rev =3D FIELD_GET(HW_VERSION_REVISION, hw_version); + hw_step =3D FIELD_GET(HW_VERSION_STEPPING, hw_version); + dev_dbg_once(tpg->camss->dev, "tpg HW Version =3D %u.%u.%u\n", + hw_gen, hw_rev, hw_step); + + return hw_version; +} + +/* + * tpg_reset - Trigger reset on tpg module and wait to complete + * @tpg: tpg device + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_reset(struct tpg_device *tpg) +{ + writel(0, tpg->base + TPG_CTRL); + writel(1, tpg->base + TPG_CLEAR); + + return 0; +} + +static void tpg_subdev_init(struct tpg_device *tpg) +{ + tpg->testgen.modes =3D testgen_payload_modes; + tpg->testgen.nmodes =3D TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1; +} + +const struct tpg_hw_ops tpg_ops_gen1 =3D { + .configure_stream =3D tpg_configure_stream, + .configure_testgen_pattern =3D tpg_configure_testgen_pattern, + .hw_version =3D tpg_hw_version, + .reset =3D tpg_reset, + .subdev_init =3D tpg_subdev_init, +}; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 2ede19e1347ae32f2f6919905b535352bcd134be..446d3fb94f35412178b72c80327= 4a5159c57c852 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2745,6 +2745,62 @@ static const struct camss_subdev_resources csiphy_re= s_8775p[] =3D { }, }; =20 +static const struct camss_subdev_resources tpg_res_8775p[] =3D { + /* TPG0 */ + { + .regulators =3D { }, + .clock =3D { "csiphy_rx", "camnoc_axi" }, + .clock_rate =3D { + { 400000000 }, + { 400000000 }, + }, + .reg =3D { "tpg0" }, + .interrupt =3D { "tpg0" }, + .tpg =3D { + .lane_cnt =3D 4, + .vc_cnt =3D 1, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, + + /* TPG1 */ + { + .regulators =3D { }, + .clock =3D { "csiphy_rx", "camnoc_axi" }, + .clock_rate =3D { + { 400000000 }, + { 400000000 }, + }, + .reg =3D { "tpg1" }, + .interrupt =3D { "tpg1" }, + .tpg =3D { + .lane_cnt =3D 4, + .vc_cnt =3D 1, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, + + /* TPG2 */ + { + .regulators =3D { }, + .clock =3D { "csiphy_rx", "camnoc_axi" }, + .clock_rate =3D { + { 400000000 }, + { 400000000 }, + }, + .reg =3D { "tpg2" }, + .interrupt =3D { "tpg2" }, + .tpg =3D { + .lane_cnt =3D 4, + .vc_cnt =3D 1, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, +}; + static const struct camss_subdev_resources csid_res_8775p[] =3D { /* CSID0 */ { @@ -4217,6 +4273,13 @@ static int camss_probe(struct platform_device *pdev) if (!camss->csiphy) return -ENOMEM; =20 + if (camss->res->tpg_num > 0) { + camss->tpg =3D devm_kcalloc(dev, camss->res->tpg_num, + sizeof(*camss->tpg), GFP_KERNEL); + if (!camss->tpg) + return -ENOMEM; + } + camss->csid =3D devm_kcalloc(dev, camss->res->csid_num, sizeof(*camss->cs= id), GFP_KERNEL); if (!camss->csid) @@ -4394,11 +4457,13 @@ static const struct camss_resources qcs8300_resourc= es =3D { .version =3D CAMSS_8300, .pd_name =3D "top", .csiphy_res =3D csiphy_res_8300, + .tpg_res =3D tpg_res_8775p, .csid_res =3D csid_res_8775p, .csid_wrapper_res =3D &csid_wrapper_res_sm8550, .vfe_res =3D vfe_res_8775p, .icc_res =3D icc_res_qcs8300, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8300), + .tpg_num =3D ARRAY_SIZE(tpg_res_8775p), .csid_num =3D ARRAY_SIZE(csid_res_8775p), .vfe_num =3D ARRAY_SIZE(vfe_res_8775p), .icc_path_num =3D ARRAY_SIZE(icc_res_qcs8300), @@ -4408,11 +4473,13 @@ static const struct camss_resources sa8775p_resourc= es =3D { .version =3D CAMSS_8775P, .pd_name =3D "top", .csiphy_res =3D csiphy_res_8775p, + .tpg_res =3D tpg_res_8775p, .csid_res =3D csid_res_8775p, .csid_wrapper_res =3D &csid_wrapper_res_sm8550, .vfe_res =3D vfe_res_8775p, .icc_res =3D icc_res_sa8775p, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8775p), + .tpg_num =3D ARRAY_SIZE(tpg_res_8775p), .csid_num =3D ARRAY_SIZE(csid_res_8775p), .vfe_num =3D ARRAY_SIZE(vfe_res_8775p), .icc_path_num =3D ARRAY_SIZE(icc_res_sa8775p), --=20 2.34.1