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Enable per-channel power domain management to facilitate runtime suspend and resume operations. Implement runtime suspend and resume functions for the eDMA engine and individual channels. Link per-channel power domain device to eDMA per-channel device instead of eDMA engine device. So Power Manage framework manage power state of linked domain device when per-channel device request runtime resume/suspend. Trigger the eDMA engine's runtime suspend when all channels are suspended, disabling all common clocks through the runtime PM framework. Signed-off-by: Joy Zou Signed-off-by: Frank Li Reviewed-by: Frank Li --- Changes for V4: - fix a typo dmaegnine/dmaengine in the subject. - Link to v3: https://lore.kernel.org/imx/20250912-b4-edma-runtime-v3-1-be2= 2f7161745@nxp.com/ Changes for V3: - rebased onto commit 8f21d9da4670 ("Add linux-next specific files for 2025= 0911") to align with latest changes. - Remove pm_runtime_dont_use_autosuspend() from fsl_edma3_detach_pd(). because the autosuspend is not used. - Move some edma channel registers initialization after the chan_dev pm_runtime_enable(). - Add clk_prepare_enable() return check in fsl_edma_runtime_resume. - Add flag FSL_EDMA_DRV_HAS_DMACLK check in fsl_edma_runtime_resume/suspend= (). - Link to v2: https://lore.kernel.org/imx/20241226052643.1951886-1-joy.zou@= nxp.com/ Changes for V2: - drop ret from fsl_edma_chan_runtime_suspend(). - drop ret from fsl_edma_chan_runtime_resume() and return clk_prepare_enabl= e(). - add review tag - Link to v1: https://lore.kernel.org/imx/20241220021109.2102294-1-joy.zou@= nxp.com/ --- drivers/dma/fsl-edma-common.c | 15 ++--- drivers/dma/fsl-edma-main.c | 129 +++++++++++++++++++++++++++++++++++---= ---- 2 files changed, 116 insertions(+), 28 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index 4976d7dde08090d16277af4b9f784b9745485320..55cb094088d569b87cde78a3673= 4a1fc7e251b73 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -243,9 +243,6 @@ int fsl_edma_terminate_all(struct dma_chan *chan) spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); vchan_dma_desc_free_list(&fsl_chan->vchan, &head); =20 - if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_PD) - pm_runtime_allow(fsl_chan->pd_dev); - return 0; } =20 @@ -823,8 +820,12 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *cha= n) struct fsl_edma_chan *fsl_chan =3D to_fsl_edma_chan(chan); int ret =3D 0; =20 - if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK) - clk_prepare_enable(fsl_chan->clk); + ret =3D pm_runtime_get_sync(&fsl_chan->vchan.chan.dev->device); + if (ret < 0) { + dev_err(&fsl_chan->vchan.chan.dev->device, "pm_runtime_get_sync() failed= \n"); + pm_runtime_disable(&fsl_chan->vchan.chan.dev->device); + return ret; + } =20 fsl_chan->tcd_pool =3D dma_pool_create("tcd_pool", chan->device->dev, fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_TCD64 ? @@ -852,6 +853,7 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan) free_irq(fsl_chan->txirq, fsl_chan); err_txirq: dma_pool_destroy(fsl_chan->tcd_pool); + pm_runtime_put_sync_suspend(&fsl_chan->vchan.chan.dev->device); =20 return ret; } @@ -883,8 +885,7 @@ void fsl_edma_free_chan_resources(struct dma_chan *chan) fsl_chan->is_sw =3D false; fsl_chan->srcid =3D 0; fsl_chan->is_remote =3D false; - if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK) - clk_disable_unprepare(fsl_chan->clk); + pm_runtime_put_sync_suspend(&fsl_chan->vchan.chan.dev->device); } =20 void fsl_edma_cleanup_vchan(struct dma_device *dmadev) diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 97583c7d51a2e8e7a50c7eb4f5ff0582ac95798d..e06f4240fdeb8839493f00c63b6= 40eb3aa795b91 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -642,7 +642,6 @@ static void fsl_edma3_detach_pd(struct fsl_edma_engine = *fsl_edma) device_link_del(fsl_chan->pd_dev_link); if (fsl_chan->pd_dev) { dev_pm_domain_detach(fsl_chan->pd_dev, false); - pm_runtime_dont_use_autosuspend(fsl_chan->pd_dev); pm_runtime_set_suspended(fsl_chan->pd_dev); } } @@ -673,23 +672,8 @@ static int fsl_edma3_attach_pd(struct platform_device = *pdev, struct fsl_edma_eng dev_err(dev, "Failed attach pd %d\n", i); goto detach; } - - fsl_chan->pd_dev_link =3D device_link_add(dev, pd_chan, DL_FLAG_STATELES= S | - DL_FLAG_PM_RUNTIME | - DL_FLAG_RPM_ACTIVE); - if (!fsl_chan->pd_dev_link) { - dev_err(dev, "Failed to add device_link to %d\n", i); - dev_pm_domain_detach(pd_chan, false); - goto detach; - } - fsl_chan->pd_dev =3D pd_chan; - - pm_runtime_use_autosuspend(fsl_chan->pd_dev); - pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); - pm_runtime_set_active(fsl_chan->pd_dev); } - return 0; =20 detach: @@ -697,6 +681,29 @@ static int fsl_edma3_attach_pd(struct platform_device = *pdev, struct fsl_edma_eng return -EINVAL; } =20 +/* Per channel dma power domain */ +static int fsl_edma_chan_runtime_suspend(struct device *dev) +{ + struct fsl_edma_chan *fsl_chan =3D dev_get_drvdata(dev); + + clk_disable_unprepare(fsl_chan->clk); + + return 0; +} + +static int fsl_edma_chan_runtime_resume(struct device *dev) +{ + struct fsl_edma_chan *fsl_chan =3D dev_get_drvdata(dev); + + return clk_prepare_enable(fsl_chan->clk); +} + +static struct dev_pm_domain fsl_edma_chan_pm_domain =3D { + .ops =3D { + RUNTIME_PM_OPS(fsl_edma_chan_runtime_suspend, fsl_edma_chan_runtim= e_resume, NULL) + } +}; + static int fsl_edma_probe(struct platform_device *pdev) { struct device_node *np =3D pdev->dev.of_node; @@ -826,11 +833,6 @@ static int fsl_edma_probe(struct platform_device *pdev) } fsl_chan->pdev =3D pdev; vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); - - edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr); - fsl_edma_chan_mux(fsl_chan, 0, false); - if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) - clk_disable_unprepare(fsl_chan->clk); } =20 ret =3D fsl_edma->drvdata->setup_irq(pdev, fsl_edma); @@ -889,6 +891,45 @@ static int fsl_edma_probe(struct platform_device *pdev) return ret; } =20 + pm_runtime_enable(&pdev->dev); + + for (i =3D 0; i < fsl_edma->n_chans; i++) { + struct fsl_edma_chan *fsl_chan =3D &fsl_edma->chans[i]; + struct device *chan_dev; + + if (fsl_edma->chan_masked & BIT(i)) + continue; + + chan_dev =3D &fsl_chan->vchan.chan.dev->device; + dev_set_drvdata(chan_dev, fsl_chan); + dev_pm_domain_set(chan_dev, &fsl_edma_chan_pm_domain); + + if (fsl_chan->pd_dev) { + fsl_chan->pd_dev_link =3D device_link_add(chan_dev, fsl_chan->pd_dev, + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (!fsl_chan->pd_dev_link) { + dev_pm_domain_detach(fsl_chan->pd_dev, false); + fsl_edma3_detach_pd(fsl_edma); + return dev_err_probe(&pdev->dev, -EINVAL, + "Failed to add device_link to %d\n", i); + } + pm_runtime_put_sync_suspend(fsl_chan->pd_dev); + } + pm_runtime_enable(chan_dev); + + if (fsl_chan->pd_dev) + pm_runtime_get_sync(fsl_chan->pd_dev); + + edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr); + fsl_edma_chan_mux(fsl_chan, 0, false); + if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) + clk_disable_unprepare(fsl_chan->clk); + if (fsl_chan->pd_dev) + pm_runtime_put_sync_suspend(fsl_chan->pd_dev); + } + ret =3D of_dma_controller_register(np, drvdata->dmamuxs ? fsl_edma_xlate : fsl_edma3_xlate, fsl_edma); @@ -929,6 +970,13 @@ static int fsl_edma_suspend_late(struct device *dev) fsl_chan =3D &fsl_edma->chans[i]; if (fsl_edma->chan_masked & BIT(i)) continue; + + if (pm_runtime_status_suspended(&fsl_chan->vchan.chan.dev->device) || + (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_PD) && + (fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) && + !fsl_chan->srcid)) + continue; + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); /* Make sure chan is idle or will force disable. */ if (unlikely(fsl_chan->status =3D=3D DMA_IN_PROGRESS)) { @@ -955,6 +1003,13 @@ static int fsl_edma_resume_early(struct device *dev) fsl_chan =3D &fsl_edma->chans[i]; if (fsl_edma->chan_masked & BIT(i)) continue; + + if (pm_runtime_status_suspended(&fsl_chan->vchan.chan.dev->device) || + (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_PD) && + (fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) && + !fsl_chan->srcid)) + continue; + fsl_chan->pm_state =3D RUNNING; edma_write_tcdreg(fsl_chan, 0, csr); if (fsl_chan->srcid !=3D 0) @@ -967,6 +1022,37 @@ static int fsl_edma_resume_early(struct device *dev) return 0; } =20 +/* edma engine runtime system/resume */ +static int fsl_edma_runtime_suspend(struct device *dev) +{ + struct fsl_edma_engine *fsl_edma =3D dev_get_drvdata(dev); + int i; + + for (i =3D 0; i < fsl_edma->drvdata->dmamuxs; i++) + clk_disable_unprepare(fsl_edma->muxclk[i]); + + if (fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) + clk_disable_unprepare(fsl_edma->dmaclk); + + return 0; +} + +static int fsl_edma_runtime_resume(struct device *dev) +{ + struct fsl_edma_engine *fsl_edma =3D dev_get_drvdata(dev); + int i, ret; + + for (i =3D 0; i < fsl_edma->drvdata->dmamuxs; i++) { + ret =3D clk_prepare_enable(fsl_edma->muxclk[i]); + if (ret) + return ret; + } + + if (fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) + return clk_prepare_enable(fsl_edma->dmaclk); + return 0; +} + /* * eDMA provides the service to others, so it should be suspend late * and resume early. When eDMA suspend, all of the clients should stop @@ -975,6 +1061,7 @@ static int fsl_edma_resume_early(struct device *dev) static const struct dev_pm_ops fsl_edma_pm_ops =3D { .suspend_late =3D fsl_edma_suspend_late, .resume_early =3D fsl_edma_resume_early, + RUNTIME_PM_OPS(fsl_edma_runtime_suspend, fsl_edma_runtime_resume, NULL) }; =20 static struct platform_driver fsl_edma_driver =3D { --- base-commit: 1fdbb3ff1233e204e26f9f6821ae9c125a055229 change-id: 20250912-b4-edma-runtime-23f744a0527b Best regards, --=20 Joy Zou