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Thu, 16 Oct 2025 14:02:58 -0700 From: Zhi Wang To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 4/5] rust: pci: add config space read/write support Date: Thu, 16 Oct 2025 21:02:49 +0000 Message-ID: <20251016210250.15932-5-zhiw@nvidia.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251016210250.15932-1-zhiw@nvidia.com> References: <20251016210250.15932-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A8:EE_|BY5PR12MB4132:EE_ X-MS-Office365-Filtering-Correlation-Id: 9cbf7484-06a0-43a2-0ef1-08de0cf77864 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?N9eKjraKStAmB/kOPI+KmUwxvpkvBPgNkicQGwcBbYIu1Z3eMu9sJMinHRW/?= =?us-ascii?Q?eaBPn8sViKU/pp6/RGSqzvMkUkUMp6zZSFXulR0XS4IBZiwTNBxjyxoPf5e5?= =?us-ascii?Q?6AaDZXvZFozFu2nI/l/Bpo7CbgeLI6XRpiv8uqDznuh85AyAhKb4sD/YpWyl?= =?us-ascii?Q?JQ+SBnszU24DuSL5pMZy17z+1WSQKjGOh70HQUFVcTCiT1vEYnx4MWQdkp02?= =?us-ascii?Q?OVd9AS5rFeYwpBjhGN2g3lHhxdxDsst+FTMuKgO8UVIt4d1+OeL8ksF+7G6P?= =?us-ascii?Q?8moD9DtKN7l9ii6BGsl17Pbe4E2Rl2ZfStWye07WjQSm9+nvqDhUqoRvPjlf?= =?us-ascii?Q?whEqZxbNMaq+EGFqS2Nt0dl501oT1Lz8+zolghjiq1JKUXFoXMm+icAqUN9p?= =?us-ascii?Q?0KBBslODMsLunzbv/57yeUs90+vx37ZfpkcTZUtWWA5VZJEFm8LLcpezHvcM?= =?us-ascii?Q?KFRbjopDc9F1OuEwLTj5esJbnZqeUSZt+3yoJkYdXBwb8usS90B2CpNZolOb?= =?us-ascii?Q?m8EmhdE5kuV2Zk16GrHNhhHesIEKoAgW+CQzqf+V8saLZieODGBPgnLTGklq?= =?us-ascii?Q?+x+rFz+XdqvgDeUWyruqsgAKGW1I/j3A0EitqcMd/tSC4VI82g/HVyiOlstg?= =?us-ascii?Q?G6C4LW/G3jpzkbzMEWu7krFHUataedt7C6+sRYkWIbs2Rs8LBpcAaxBz/KJF?= =?us-ascii?Q?5B5GXFn6b9yD6GwDqCuppJ7jd4nAXFsAH/UF0CeezqLYjNhikEjWx2bihToX?= =?us-ascii?Q?6/S+6O3I6PnrvpvdBpwPIHAmvJXKTmTv5EiMcoTzGo5z+jDGR/eHMV/yUJkn?= =?us-ascii?Q?PQvX07liAIdfWvTxI1ciRYO9oWEGhNOrr17P0DbxwjItI/VgxJJdNUnTRP2k?= =?us-ascii?Q?sNV2bE3cX+MLv+KRX9AjaAH++edUQlgjHiU0os4GmzgW3uz8PM/Wd/u9Adr9?= =?us-ascii?Q?qBo6NMmBm/WDNkiu/LYngPou4gGQLxva4hPqV61SubDVzTNhjHsttafSGsuW?= =?us-ascii?Q?96135Wr8FatsDa+q12Yg8s2rPSBgN+t8ehoIRmeQqYj2G3/k+0bhSvKlI0k5?= =?us-ascii?Q?W88bsOZNJEUd9sMNOuSBKA9McRfsBI/Z+aHLZD2Y715jYfO7A9Z9k56eMw7x?= =?us-ascii?Q?EZ+3H89LGkZHq3leseYr2qqwKHZZnUSjUdWjyT5EH0FGVadcCLEJSC1v4AX9?= =?us-ascii?Q?2uiuoZ2U6bSMo+Vli9LZ5FSYpJnL/KksOFLTmWjFW0wtlOqfCwVl+A5gfuWG?= =?us-ascii?Q?wwKDp+yk+A0Nht85SYClkwUz+OU/ZwuN9G7VtFJusfH47OgBXLyQii2RhZ6X?= =?us-ascii?Q?C8O/xl3lwanoYkHxrMJBkhq1Ss91Ra3rNm9nFn7QIhA5U+RUZl0swINKDU5e?= =?us-ascii?Q?SULCVJuHHcwXLgbEANISW8E+6aCL7dNY74tzQ0ewsCMAgCb5W59AQ+/cW+dl?= =?us-ascii?Q?isAnsvNBF2WiN+ZB1mAJ6c6Juy/EBFFxmdaoeaJzqyWPBLppqnf/RPvrObNp?= =?us-ascii?Q?LHutxuYrkS2Ov/ZzfokeEP+ODiSvZTANThaGbJslZm1PFLIS8g7KjZuV6ZTY?= =?us-ascii?Q?LvIdz+PSZwhmQ2X6P/Y=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2025 21:03:34.8540 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9cbf7484-06a0-43a2-0ef1-08de0cf77864 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4132 Content-Type: text/plain; charset="utf-8" Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to provide safe accessors for PCI configuration space. The new type implements the `Io` trait to share offset validation and bound-checking logic with others. Cc: Danilo Krummrich Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 65 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 34729c6f5665..d7e0f18169d7 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -10,7 +10,8 @@ devres::Devres, driver, error::{from_result, to_result, Result}, - io::{Mmio, MmioRaw}, + io::{define_read, define_write}, + io::{Io, Mmio, MmioRaw}, irq::{self, IrqRequest}, str::CStr, sync::aref::ARef, @@ -305,6 +306,63 @@ pub struct Device( PhantomData, ); =20 +/// Represents the PCI configuration space of a device. +/// +/// Provides typed read and write accessors for configuration registers +/// using the standard `pci_read_config_*` and `pci_write_config_*` helper= s. +/// +/// The generic const parameter `SIZE` can be used to indicate the +/// maximum size of the configuration space (e.g. 256 bytes for legacy, +/// 4096 bytes for extended config space). The actual size is obtained +/// from the underlying `struct pci_dev` via [`Device::cfg_size`]. +pub struct ConfigSpace<'a, const SIZE: usize =3D 4096> { + pdev: &'a Device, +} + +impl<'a, const SIZE: usize> Io for ConfigSpace<'a, SIZE> { + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + 0 + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.pdev.cfg_size() as usize + } +} + +macro_rules! call_config_read { + ($c_fn:ident, $self:ident, $offset:expr, $ty:ty, $_addr:expr) =3D> {{ + let mut val: $ty =3D 0; + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $offset = as i32, &mut val) }; + (ret =3D=3D 0) + .then_some(Ok(val)) + .unwrap_or_else(|| Err(Error::from_errno(ret))) + }}; +} + +macro_rules! call_config_write { + ($c_fn:ident, $self:ident, $offset:expr, $ty:ty, $_addr:expr, $value:e= xpr) =3D> {{ + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $offset = as i32, $value) }; + (ret =3D=3D 0) + .then_some(Ok(())) + .unwrap_or_else(|| Err(Error::from_errno(ret))) + }}; +} + +#[allow(dead_code)] +impl<'a, const SIZE: usize> ConfigSpace<'a, SIZE> { + define_read!(read8, try_read8, call_config_read, pci_read_config_byte = -> u8); + define_read!(read16, try_read16, call_config_read, pci_read_config_wor= d -> u16); + define_read!(read32, try_read32, call_config_read, pci_read_config_dwo= rd -> u32); + + define_write!(write8, try_write8, call_config_write, pci_write_config_= byte <- u8); + define_write!(write16, try_write16, call_config_write, pci_write_confi= g_word <- u16); + define_write!(write32, try_write32, call_config_write, pci_write_confi= g_dword <- u32); +} + /// A PCI BAR to perform I/O-Operations on. /// /// # Invariants @@ -582,6 +640,11 @@ pub fn request_threaded_irq<'a, T: crate::irq::Threade= dHandler + 'static>( request, flags, name, handler, )) } + + /// Return an initialized object. + pub fn config_space<'a>(&'a self) -> Result> { + Ok(ConfigSpace { pdev: self }) + } } =20 impl Device { --=20 2.47.3