From nobody Sun Feb 8 05:20:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 774A433EAF1; Thu, 16 Oct 2025 14:22:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760624565; cv=none; b=qMVdfcuPs4usHVxTlxkRTkwITROiCd7got/bYzKQbyHUJJFXk0QRZtmK3qGaabUZ1rQ3lQ66rXJqmo/ci3Tx7VlIrco77NVxvuqdtqdXOqRYjw5M/WPVfBZEXMQwkRsJ8tDnC7iBLE0xb5QVXqGO97ZeVisGHW6cZxc1ZuumqjY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760624565; c=relaxed/simple; bh=hf/ZkPsMGv4tCh0i/1+WvqD+gv9TtsDwMhs3GkSqp5o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PIU3zXFWBqWTTGME5LQulQoJMN8O4L0INn1JSuAbqOjqwe+Sc2IqVeAzDDlJPRIacvLuUzEMP3AnAJAzAmWmAHY8XCxxTU10zyljh3mhmCDzpB1FlTxHjXXAV3FF3hP1nFcXPuyu1CC6MdjxQFO/S2jixJsjlhm0yCIEEfXNgqM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ScXdSumI; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ScXdSumI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1760624561; bh=hf/ZkPsMGv4tCh0i/1+WvqD+gv9TtsDwMhs3GkSqp5o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ScXdSumIIFFLjVNSgxVB6Bem46SaWqmvrYOM/Je3B0gqzmfU4g2K9bWb3JE+M74EI hAJseDftw1nFC3FS38byL8uB5x2z4r8SNH8O50WhWn5jkamwMkZBaB+lK86QheZKhF X7QU8izXtWvTmi7sqop1DEvbCPtG40Z9GloA10TLp8tov+NdkNOu8eoX02TyzFhN0Z Y01TyOM4gtMuoltAHsdv2v7VBSXazFkmJ8/8mcZRU2iQ4GYJ+pk2CYEIQ30f+/PzyJ PTWh8iifAyeW4JDxQGFO15S5iy/9ZN8wQ6/pWZldeQ+aQbqmVuo8ExSVBVP+1qFxjG A85eCUiNe8U6Q== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:655a:5eaa:d2ad:4ee4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9412017E0CF8; Thu, 16 Oct 2025 16:22:40 +0200 (CEST) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, Laura Nao , Krzysztof Kozlowski Subject: [PATCH RESEND v3 1/9] dt-bindings: thermal: mediatek: Add LVTS thermal controller support for MT8196 Date: Thu, 16 Oct 2025 16:21:50 +0200 Message-Id: <20251016142158.740242-2-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251016142158.740242-1-laura.nao@collabora.com> References: <20251016142158.740242-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add LVTS thermal controller binding for MediaTek MT8196. Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Tested-by: Frank Wunderlich --- .../thermal/mediatek,lvts-thermal.yaml | 2 ++ .../thermal/mediatek,lvts-thermal.h | 26 +++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-therma= l.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.ya= ml index 0259cd3ce9c5..beccdabe110b 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml @@ -26,6 +26,8 @@ properties: - mediatek,mt8192-lvts-mcu - mediatek,mt8195-lvts-ap - mediatek,mt8195-lvts-mcu + - mediatek,mt8196-lvts-ap + - mediatek,mt8196-lvts-mcu =20 reg: maxItems: 1 diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/= dt-bindings/thermal/mediatek,lvts-thermal.h index ddc7302a510a..0ec8ad184d47 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -80,4 +80,30 @@ #define MT8192_AP_MD1 15 #define MT8192_AP_MD2 16 =20 +#define MT8196_MCU_MEDIUM_CPU6_0 0 +#define MT8196_MCU_MEDIUM_CPU6_1 1 +#define MT8196_MCU_DSU2 2 +#define MT8196_MCU_DSU3 3 +#define MT8196_MCU_LITTLE_CPU3 4 +#define MT8196_MCU_LITTLE_CPU0 5 +#define MT8196_MCU_LITTLE_CPU1 6 +#define MT8196_MCU_LITTLE_CPU2 7 +#define MT8196_MCU_MEDIUM_CPU4_0 8 +#define MT8196_MCU_MEDIUM_CPU4_1 9 +#define MT8196_MCU_MEDIUM_CPU5_0 10 +#define MT8196_MCU_MEDIUM_CPU5_1 11 +#define MT8196_MCU_DSU0 12 +#define MT8196_MCU_DSU1 13 +#define MT8196_MCU_BIG_CPU7_0 14 +#define MT8196_MCU_BIG_CPU7_1 15 + +#define MT8196_AP_TOP0 0 +#define MT8196_AP_TOP1 1 +#define MT8196_AP_TOP2 2 +#define MT8196_AP_TOP3 3 +#define MT8196_AP_BOT0 4 +#define MT8196_AP_BOT1 5 +#define MT8196_AP_BOT2 6 +#define MT8196_AP_BOT3 7 + #endif /* __MEDIATEK_LVTS_DT_H */ --=20 2.39.5 From nobody Sun Feb 8 05:20:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10BD633EB0E; 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Thu, 16 Oct 2025 16:22:41 +0200 (CEST) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, Laura Nao , Fei Shao Subject: [PATCH RESEND v3 2/9] thermal/drivers/mediatek/lvts: Make number of calibration offsets configurable Date: Thu, 16 Oct 2025 16:21:51 +0200 Message-Id: <20251016142158.740242-3-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251016142158.740242-1-laura.nao@collabora.com> References: <20251016142158.740242-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8196/MT6991 use 2-byte eFuse calibration data, whereas other SoCs supported by the driver rely on 3 bytes. Make the number of calibration bytes per sensor configurable, enabling support for SoCs with varying calibration formats. Reviewed-by: Fei Shao Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Tested-by: Frank Wunderlich --- drivers/thermal/mediatek/lvts_thermal.c | 32 +++++++++++++++++-------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index ab55b20cda47..1c54d0b75b1a 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -96,12 +96,14 @@ =20 #define LVTS_MINIMUM_THRESHOLD 20000 =20 +#define LVTS_MAX_CAL_OFFSETS 3 + static int golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT; static int golden_temp_offset; =20 struct lvts_sensor_data { int dt_id; - u8 cal_offsets[3]; + u8 cal_offsets[LVTS_MAX_CAL_OFFSETS]; }; =20 struct lvts_ctrl_data { @@ -127,6 +129,7 @@ struct lvts_data { const struct lvts_ctrl_data *lvts_ctrl; const u32 *conn_cmd; const u32 *init_cmd; + int num_cal_offsets; int num_lvts_ctrl; int num_conn_cmd; int num_init_cmd; @@ -711,7 +714,7 @@ static int lvts_calibration_init(struct device *dev, st= ruct lvts_ctrl *lvts_ctrl u8 *efuse_calibration, size_t calib_len) { - int i; + int i, j; u32 gt; =20 /* A zero value for gt means that device has invalid efuse data */ @@ -720,17 +723,18 @@ static int lvts_calibration_init(struct device *dev, = struct lvts_ctrl *lvts_ctrl lvts_for_each_valid_sensor(i, lvts_ctrl_data) { const struct lvts_sensor_data *sensor =3D &lvts_ctrl_data->lvts_sensor[i]; + u32 calib =3D 0; =20 - if (sensor->cal_offsets[0] >=3D calib_len || - sensor->cal_offsets[1] >=3D calib_len || - sensor->cal_offsets[2] >=3D calib_len) - return -EINVAL; + for (j =3D 0; j < lvts_ctrl->lvts_data->num_cal_offsets; j++) { + u8 offset =3D sensor->cal_offsets[j]; + + if (offset >=3D calib_len) + return -EINVAL; + calib |=3D efuse_calibration[offset] << (8 * j); + } =20 if (gt) { - lvts_ctrl->calibration[i] =3D - (efuse_calibration[sensor->cal_offsets[0]] << 0) + - (efuse_calibration[sensor->cal_offsets[1]] << 8) + - (efuse_calibration[sensor->cal_offsets[2]] << 16); + lvts_ctrl->calibration[i] =3D calib; } else if (lvts_ctrl->lvts_data->def_calibration) { lvts_ctrl->calibration[i] =3D lvts_ctrl->lvts_data->def_calibration; } else { @@ -1763,6 +1767,7 @@ static const struct lvts_data mt7988_lvts_ap_data =3D= { .temp_factor =3D LVTS_COEFF_A_MT7988, .temp_offset =3D LVTS_COEFF_B_MT7988, .gt_calib_bit_offset =3D 24, + .num_cal_offsets =3D 3, }; =20 static const struct lvts_data mt8186_lvts_data =3D { @@ -1776,6 +1781,7 @@ static const struct lvts_data mt8186_lvts_data =3D { .temp_offset =3D LVTS_COEFF_B_MT7988, .gt_calib_bit_offset =3D 24, .def_calibration =3D 19000, + .num_cal_offsets =3D 3, }; =20 static const struct lvts_data mt8188_lvts_mcu_data =3D { @@ -1789,6 +1795,7 @@ static const struct lvts_data mt8188_lvts_mcu_data = =3D { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 20, .def_calibration =3D 35000, + .num_cal_offsets =3D 3, }; =20 static const struct lvts_data mt8188_lvts_ap_data =3D { @@ -1802,6 +1809,7 @@ static const struct lvts_data mt8188_lvts_ap_data =3D= { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 20, .def_calibration =3D 35000, + .num_cal_offsets =3D 3, }; =20 static const struct lvts_data mt8192_lvts_mcu_data =3D { @@ -1815,6 +1823,7 @@ static const struct lvts_data mt8192_lvts_mcu_data = =3D { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, + .num_cal_offsets =3D 3, }; =20 static const struct lvts_data mt8192_lvts_ap_data =3D { @@ -1828,6 +1837,7 @@ static const struct lvts_data mt8192_lvts_ap_data =3D= { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, + .num_cal_offsets =3D 3, }; =20 static const struct lvts_data mt8195_lvts_mcu_data =3D { @@ -1841,6 +1851,7 @@ static const struct lvts_data mt8195_lvts_mcu_data = =3D { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, + .num_cal_offsets =3D 3, }; =20 static const struct lvts_data mt8195_lvts_ap_data =3D { @@ -1854,6 +1865,7 @@ static const struct lvts_data mt8195_lvts_ap_data =3D= { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, + .num_cal_offsets =3D 3, }; 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Thu, 16 Oct 2025 16:22:43 +0200 (CEST) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, Laura Nao , Chen-Yu Tsai , Fei Shao Subject: [PATCH RESEND v3 3/9] thermal/drivers/mediatek/lvts: Guard against zero temp_factor in lvts_raw_to_temp Date: Thu, 16 Oct 2025 16:21:52 +0200 Message-Id: <20251016142158.740242-4-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251016142158.740242-1-laura.nao@collabora.com> References: <20251016142158.740242-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a guard against zero temp_factor in lvts_raw_to_temp() to prevent division by zero and ensure safe conversion. Fixes: 6725a29321e4 ("thermal/drivers/mediatek/lvts_thermal: Make coeff con= figurable") Reviewed-by: Chen-Yu Tsai Reviewed-by: Fei Shao Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Tested-by: Frank Wunderlich --- drivers/thermal/mediatek/lvts_thermal.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 1c54d0b75b1a..4ef549386add 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -284,11 +284,14 @@ static int lvts_raw_to_temp(u32 raw_temp, int temp_fa= ctor) =20 static u32 lvts_temp_to_raw(int temperature, int temp_factor) { - u32 raw_temp =3D ((s64)(golden_temp_offset - temperature)) << 14; + u32 raw_temp; =20 - raw_temp =3D div_s64(raw_temp, -temp_factor); + if (temp_factor =3D=3D 0) + return temperature; =20 - return raw_temp; + raw_temp =3D ((s64)(golden_temp_offset - temperature)) << 14; + + return div_s64(raw_temp, -temp_factor); } =20 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) @@ -1346,6 +1349,9 @@ static int lvts_probe(struct platform_device *pdev) if (irq < 0) return irq; =20 + if (!lvts_data->temp_factor) + dev_warn(dev, "temp_factor should never be zero; check platform data.\n"= ); + golden_temp_offset =3D lvts_data->temp_offset; =20 ret =3D lvts_domain_init(dev, lvts_td, lvts_data); --=20 2.39.5 From nobody Sun Feb 8 05:20:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2363340DB3; Thu, 16 Oct 2025 14:22:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760624569; cv=none; b=P6O849HhucfxtXctn0qn/KdaGRDmr9Z3EIj7nNCcwV5DKRqF9aV+73DlEdbUToMTLm+OWi3K2zvQx3KYU2EoCDyybnaWuO5y3q0mpGAdbZsDp4nnQRgTRcNT4qGwj9fqHnHY5kh6t8CgkLTKsKCqhhXLP6andrmVKDSa+0WXOfg= ARC-Message-Signature: i=1; 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charset="utf-8" Introduce lvts_platform_ops struct to support SoC-specific versions of lvts_raw_to_temp() and lvts_temp_to_raw() conversion functions. This is in preparation for supporting SoCs like MT8196/MT6991, which require a different lvts_temp_to_raw() implementation. Reviewed-by: Fei Shao Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Tested-by: Frank Wunderlich --- drivers/thermal/mediatek/lvts_thermal.c | 27 ++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 4ef549386add..df1c0f059ad0 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -125,8 +125,14 @@ struct lvts_ctrl_data { continue; \ else =20 +struct lvts_platform_ops { + int (*lvts_raw_to_temp)(u32 raw_temp, int temp_factor); + u32 (*lvts_temp_to_raw)(int temperature, int temp_factor); +}; + struct lvts_data { const struct lvts_ctrl_data *lvts_ctrl; + const struct lvts_platform_ops *ops; const u32 *conn_cmd; const u32 *init_cmd; int num_cal_offsets; @@ -300,6 +306,7 @@ static int lvts_get_temp(struct thermal_zone_device *tz= , int *temp) struct lvts_ctrl *lvts_ctrl =3D container_of(lvts_sensor, struct lvts_ctr= l, sensors[lvts_sensor->id]); const struct lvts_data *lvts_data =3D lvts_ctrl->lvts_data; + const struct lvts_platform_ops *ops =3D lvts_data->ops; void __iomem *msr =3D lvts_sensor->msr; u32 value; int rc; @@ -332,7 +339,7 @@ static int lvts_get_temp(struct thermal_zone_device *tz= , int *temp) if (rc) return -EAGAIN; =20 - *temp =3D lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); + *temp =3D ops->lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); =20 return 0; } @@ -400,10 +407,11 @@ static int lvts_set_trips(struct thermal_zone_device = *tz, int low, int high) struct lvts_ctrl *lvts_ctrl =3D container_of(lvts_sensor, struct lvts_ctr= l, sensors[lvts_sensor->id]); const struct lvts_data *lvts_data =3D lvts_ctrl->lvts_data; + const struct lvts_platform_ops *ops =3D lvts_data->ops; void __iomem *base =3D lvts_sensor->base; - u32 raw_low =3D lvts_temp_to_raw(low !=3D -INT_MAX ? low : LVTS_MINIMUM_T= HRESHOLD, + u32 raw_low =3D ops->lvts_temp_to_raw(low !=3D -INT_MAX ? low : LVTS_MINI= MUM_THRESHOLD, lvts_data->temp_factor); - u32 raw_high =3D lvts_temp_to_raw(high, lvts_data->temp_factor); + u32 raw_high =3D ops->lvts_temp_to_raw(high, lvts_data->temp_factor); bool should_update_thresh; =20 lvts_sensor->low_thresh =3D low; @@ -1763,6 +1771,11 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_da= ta_ctrl[] =3D { } }; =20 +static const struct lvts_platform_ops lvts_platform_ops_v1 =3D { + .lvts_raw_to_temp =3D lvts_raw_to_temp, + .lvts_temp_to_raw =3D lvts_temp_to_raw, +}; + static const struct lvts_data mt7988_lvts_ap_data =3D { .lvts_ctrl =3D mt7988_lvts_ap_data_ctrl, .conn_cmd =3D mt7988_conn_cmds, @@ -1774,6 +1787,7 @@ static const struct lvts_data mt7988_lvts_ap_data =3D= { .temp_offset =3D LVTS_COEFF_B_MT7988, .gt_calib_bit_offset =3D 24, .num_cal_offsets =3D 3, + .ops =3D &lvts_platform_ops_v1, }; =20 static const struct lvts_data mt8186_lvts_data =3D { @@ -1788,6 +1802,7 @@ static const struct lvts_data mt8186_lvts_data =3D { .gt_calib_bit_offset =3D 24, .def_calibration =3D 19000, .num_cal_offsets =3D 3, + .ops =3D &lvts_platform_ops_v1, }; =20 static const struct lvts_data mt8188_lvts_mcu_data =3D { @@ -1802,6 +1817,7 @@ static const struct lvts_data mt8188_lvts_mcu_data = =3D { .gt_calib_bit_offset =3D 20, .def_calibration =3D 35000, .num_cal_offsets =3D 3, + .ops =3D &lvts_platform_ops_v1, }; =20 static const struct lvts_data mt8188_lvts_ap_data =3D { @@ -1816,6 +1832,7 @@ static const struct lvts_data mt8188_lvts_ap_data =3D= { .gt_calib_bit_offset =3D 20, .def_calibration =3D 35000, .num_cal_offsets =3D 3, + .ops =3D &lvts_platform_ops_v1, }; =20 static const struct lvts_data mt8192_lvts_mcu_data =3D { @@ -1830,6 +1847,7 @@ static const struct lvts_data mt8192_lvts_mcu_data = =3D { .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, .num_cal_offsets =3D 3, + .ops =3D &lvts_platform_ops_v1, }; =20 static const struct lvts_data mt8192_lvts_ap_data =3D { @@ -1844,6 +1862,7 @@ static const struct lvts_data mt8192_lvts_ap_data =3D= { .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, .num_cal_offsets =3D 3, + .ops =3D &lvts_platform_ops_v1, }; =20 static const struct lvts_data mt8195_lvts_mcu_data =3D { @@ -1858,6 +1877,7 @@ static const struct lvts_data mt8195_lvts_mcu_data = =3D { .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, .num_cal_offsets =3D 3, + .ops =3D &lvts_platform_ops_v1, }; =20 static const struct lvts_data mt8195_lvts_ap_data =3D { @@ -1872,6 +1892,7 @@ static const struct lvts_data mt8195_lvts_ap_data =3D= { .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, .num_cal_offsets =3D 3, + .ops =3D &lvts_platform_ops_v1, }; =20 static const struct of_device_id lvts_of_match[] =3D { --=20 2.39.5 From nobody Sun Feb 8 05:20:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ABED341653; Thu, 16 Oct 2025 14:22:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; 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Thu, 16 Oct 2025 16:22:46 +0200 (CEST) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, Laura Nao , Chen-Yu Tsai , Fei Shao Subject: [PATCH RESEND v3 5/9] thermal/drivers/mediatek/lvts: Add lvts_temp_to_raw variant Date: Thu, 16 Oct 2025 16:21:54 +0200 Message-Id: <20251016142158.740242-6-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251016142158.740242-1-laura.nao@collabora.com> References: <20251016142158.740242-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8196/MT6991 require a different version of lvts_temp_to_raw(), specifically the multiplicative inverse of the existing implementation. Introduce a variant of the function with inverted calculation logic to match this requirement. This ensures accurate raw value generation for temperature thresholds, avoiding spurious thermal interrupts or unintended hardware resets on MT8196/MT6991. Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Tested-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Tested-by: Frank Wunderlich --- drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index df1c0f059ad0..31796a5b8858 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -300,6 +300,18 @@ static u32 lvts_temp_to_raw(int temperature, int temp_= factor) return div_s64(raw_temp, -temp_factor); } =20 +static u32 lvts_temp_to_raw_v2(int temperature, int temp_factor) +{ + u32 raw_temp; + + if (temp_factor =3D=3D 0) + return temperature; + + raw_temp =3D temperature - golden_temp_offset; + + return div_s64((s64)temp_factor << 14, raw_temp); +} + static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) { struct lvts_sensor *lvts_sensor =3D thermal_zone_device_priv(tz); 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Thu, 16 Oct 2025 16:22:47 +0200 (CEST) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, Laura Nao , Chen-Yu Tsai , Fei Shao Subject: [PATCH RESEND v3 6/9] thermal/drivers/mediatek/lvts: Add support for ATP mode Date: Thu, 16 Oct 2025 16:21:55 +0200 Message-Id: <20251016142158.740242-7-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251016142158.740242-1-laura.nao@collabora.com> References: <20251016142158.740242-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8196/MT6991 uses ATP (Abnormal Temperature Prevention) mode to detect abnormal temperature conditions, which involves reading temperature data from a dedicated set of registers separate from the ones used for immediate and filtered modes. Add support for ATP mode and its relative registers to ensure accurate temperature readings and proper thermal management on MT8196/MT6991 devices. While at it, convert mode defines to enum. Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Tested-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Tested-by: Frank Wunderlich --- drivers/thermal/mediatek/lvts_thermal.c | 44 +++++++++++++++++++++---- 1 file changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 31796a5b8858..574e45400214 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -44,6 +44,10 @@ #define LVTS_EDATA01(__base) (__base + 0x0058) #define LVTS_EDATA02(__base) (__base + 0x005C) #define LVTS_EDATA03(__base) (__base + 0x0060) +#define LVTS_ATP0(__base) (__base + 0x0070) +#define LVTS_ATP1(__base) (__base + 0x0074) +#define LVTS_ATP2(__base) (__base + 0x0078) +#define LVTS_ATP3(__base) (__base + 0x007C) #define LVTS_MSR0(__base) (__base + 0x0090) #define LVTS_MSR1(__base) (__base + 0x0094) #define LVTS_MSR2(__base) (__base + 0x0098) @@ -88,9 +92,6 @@ #define LVTS_COEFF_A_MT7988 -204650 #define LVTS_COEFF_B_MT7988 204650 =20 -#define LVTS_MSR_IMMEDIATE_MODE 0 -#define LVTS_MSR_FILTERED_MODE 1 - #define LVTS_MSR_READ_TIMEOUT_US 400 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) =20 @@ -101,6 +102,12 @@ static int golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT; static int golden_temp_offset; =20 +enum lvts_msr_mode { + LVTS_MSR_IMMEDIATE_MODE, + LVTS_MSR_FILTERED_MODE, + LVTS_MSR_ATP_MODE, +}; + struct lvts_sensor_data { int dt_id; u8 cal_offsets[LVTS_MAX_CAL_OFFSETS]; @@ -110,7 +117,7 @@ struct lvts_ctrl_data { struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; u8 valid_sensor_mask; int offset; - int mode; + enum lvts_msr_mode mode; }; =20 #define VALID_SENSOR_MAP(s0, s1, s2, s3) \ @@ -211,6 +218,10 @@ static const struct debugfs_reg32 lvts_regs[] =3D { LVTS_DEBUG_FS_REGS(LVTS_EDATA01), LVTS_DEBUG_FS_REGS(LVTS_EDATA02), LVTS_DEBUG_FS_REGS(LVTS_EDATA03), + LVTS_DEBUG_FS_REGS(LVTS_ATP0), + LVTS_DEBUG_FS_REGS(LVTS_ATP1), + LVTS_DEBUG_FS_REGS(LVTS_ATP2), + LVTS_DEBUG_FS_REGS(LVTS_ATP3), LVTS_DEBUG_FS_REGS(LVTS_MSR0), LVTS_DEBUG_FS_REGS(LVTS_MSR1), LVTS_DEBUG_FS_REGS(LVTS_MSR2), @@ -625,6 +636,13 @@ static int lvts_sensor_init(struct device *dev, struct= lvts_ctrl *lvts_ctrl, LVTS_IMMD3(lvts_ctrl->base) }; =20 + void __iomem *atp_regs[] =3D { + LVTS_ATP0(lvts_ctrl->base), + LVTS_ATP1(lvts_ctrl->base), + LVTS_ATP2(lvts_ctrl->base), + LVTS_ATP3(lvts_ctrl->base) + }; + int i; =20 lvts_for_each_valid_sensor(i, lvts_ctrl_data) { @@ -660,8 +678,20 @@ static int lvts_sensor_init(struct device *dev, struct= lvts_ctrl *lvts_ctrl, /* * Each sensor has its own register address to read from. */ - lvts_sensor[i].msr =3D lvts_ctrl_data->mode =3D=3D LVTS_MSR_IMMEDIATE_MO= DE ? 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When the LVTS controller operates in 16-bit mode, a fixed offset must be added to MSR values during post-processing to obtain correct temperature readings. Introduce a new msr_offset field in lvts_data, program the respective register and apply the offset to the calibration data read from eFuses. Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Tested-by: Frank Wunderlich --- drivers/thermal/mediatek/lvts_thermal.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 574e45400214..8ca5760cbb76 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -44,6 +44,7 @@ #define LVTS_EDATA01(__base) (__base + 0x0058) #define LVTS_EDATA02(__base) (__base + 0x005C) #define LVTS_EDATA03(__base) (__base + 0x0060) +#define LVTS_MSROFT(__base) (__base + 0x006C) #define LVTS_ATP0(__base) (__base + 0x0070) #define LVTS_ATP1(__base) (__base + 0x0074) #define LVTS_ATP2(__base) (__base + 0x0078) @@ -150,6 +151,7 @@ struct lvts_data { int temp_offset; int gt_calib_bit_offset; unsigned int def_calibration; + u16 msr_offset; }; =20 struct lvts_sensor { @@ -218,6 +220,7 @@ static const struct debugfs_reg32 lvts_regs[] =3D { LVTS_DEBUG_FS_REGS(LVTS_EDATA01), LVTS_DEBUG_FS_REGS(LVTS_EDATA02), LVTS_DEBUG_FS_REGS(LVTS_EDATA03), + LVTS_DEBUG_FS_REGS(LVTS_MSROFT), LVTS_DEBUG_FS_REGS(LVTS_ATP0), LVTS_DEBUG_FS_REGS(LVTS_ATP1), LVTS_DEBUG_FS_REGS(LVTS_ATP2), @@ -788,6 +791,8 @@ static int lvts_calibration_init(struct device *dev, st= ruct lvts_ctrl *lvts_ctrl =20 if (gt) { lvts_ctrl->calibration[i] =3D calib; + if (lvts_ctrl->lvts_data->msr_offset) + lvts_ctrl->calibration[i] +=3D lvts_ctrl->lvts_data->msr_offset; } else if (lvts_ctrl->lvts_data->def_calibration) { lvts_ctrl->calibration[i] =3D lvts_ctrl->lvts_data->def_calibration; } else { @@ -1095,6 +1100,17 @@ static int lvts_ctrl_calibrate(struct device *dev, s= truct lvts_ctrl *lvts_ctrl) for (i =3D 0; i < LVTS_SENSOR_MAX; i++) writel(lvts_ctrl->calibration[i], lvts_edata[i]); =20 + /* LVTS_MSROFT : Constant offset applied to MSR values + * for post-processing + * + * Bits: + * + * 20-0 : Constant data added to MSR values + */ + if (lvts_ctrl->lvts_data->msr_offset) + writel(lvts_ctrl->lvts_data->msr_offset, + LVTS_MSROFT(lvts_ctrl->base)); + return 0; } =20 --=20 2.39.5 From nobody Sun Feb 8 05:20:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71272342C81; 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Thu, 16 Oct 2025 16:22:50 +0200 (CEST) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, Laura Nao Subject: [PATCH RESEND v3 8/9] thermal/drivers/mediatek/lvts_thermal: Add MT8196 support Date: Thu, 16 Oct 2025 16:21:57 +0200 Message-Id: <20251016142158.740242-9-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251016142158.740242-1-laura.nao@collabora.com> References: <20251016142158.740242-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add LVTS driver support for MT8196. Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Tested-by: Frank Wunderlich --- drivers/thermal/mediatek/lvts_thermal.c | 164 ++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 8ca5760cbb76..33f68697d1e3 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -92,6 +92,10 @@ #define LVTS_COEFF_B_MT8195 250460 #define LVTS_COEFF_A_MT7988 -204650 #define LVTS_COEFF_B_MT7988 204650 +#define LVTS_COEFF_A_MT8196 391460 +#define LVTS_COEFF_B_MT8196 -391460 + +#define LVTS_MSR_OFFSET_MT8196 -984 =20 #define LVTS_MSR_READ_TIMEOUT_US 400 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) @@ -761,6 +765,39 @@ static int lvts_sensor_init(struct device *dev, struct= lvts_ctrl *lvts_ctrl, * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 * + * MT8196 : + * Stream index map for MCU Domain mt8196 : + * + * <-sensor#1--> <-sensor#0--> <-sensor#3--> <-sensor#2--> + * 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B + * + * <-sensor#5--> <-sensor#4--> <-sensor#7--> <-sensor#6--> + * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 + * + * <-sensor#9--> <-sensor#8--> <-sensor#11-> <-sensor#10-> + * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0X1B + * + * <-sensor#13-> <-sensor#12-> <-sensor#15-> <-sensor#14-> + * 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 + * + * Stream index map for APU Domain mt8196 : + * + * <-sensor#1--> <-sensor#0--> <-sensor#3--> <-sensor#2--> + * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B + * + * Stream index map for GPU Domain mt8196 : + * + * <-sensor#1--> <-sensor#0--> + * 0x2C | 0x2D | 0x2E | 0x2F + * + * Stream index map for AP Domain mt8196 : + * + * <-sensor#1--> <-sensor#0--> <-sensor#3--> <-sensor#2--> + * 0x30 | 0x31 | 0x32 | 0x33 | 0x34 | 0x35 | 0x36 | 0x37 + * + * <-sensor#5--> <-sensor#4--> <-sensor#6--> <-sensor#7--> + * 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F + * * Note: In some cases, values don't strictly follow a little endian order= ing. * The data description gives byte offsets constituting each calibration v= alue * for each sensor. @@ -1829,11 +1866,112 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_= data_ctrl[] =3D { } }; =20 +static const struct lvts_ctrl_data mt8196_lvts_mcu_data_ctrl[] =3D { + { + .lvts_sensor =3D { + { .dt_id =3D MT8196_MCU_MEDIUM_CPU6_0, + .cal_offsets =3D { 0x06, 0x07 } }, + { .dt_id =3D MT8196_MCU_MEDIUM_CPU6_1, + .cal_offsets =3D { 0x04, 0x05 } }, + { .dt_id =3D MT8196_MCU_DSU2, + .cal_offsets =3D { 0x0A, 0x0B } }, + { .dt_id =3D MT8196_MCU_DSU3, + .cal_offsets =3D { 0x08, 0x09 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x0, + .mode =3D LVTS_MSR_ATP_MODE, + }, + { + .lvts_sensor =3D { + { .dt_id =3D MT8196_MCU_LITTLE_CPU3, + .cal_offsets =3D { 0x0E, 0x0F } }, + { .dt_id =3D MT8196_MCU_LITTLE_CPU0, + .cal_offsets =3D { 0x0C, 0x0D } }, + { .dt_id =3D MT8196_MCU_LITTLE_CPU1, + .cal_offsets =3D { 0x12, 0x13 } }, + { .dt_id =3D MT8196_MCU_LITTLE_CPU2, + .cal_offsets =3D { 0x10, 0x11 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x100, + .mode =3D LVTS_MSR_ATP_MODE, + }, + { + .lvts_sensor =3D { + { .dt_id =3D MT8196_MCU_MEDIUM_CPU4_0, + .cal_offsets =3D { 0x16, 0x17 } }, + { .dt_id =3D MT8196_MCU_MEDIUM_CPU4_1, + .cal_offsets =3D { 0x14, 0x15 } }, + { .dt_id =3D MT8196_MCU_MEDIUM_CPU5_0, + .cal_offsets =3D { 0x1A, 0x1B } }, + { .dt_id =3D MT8196_MCU_MEDIUM_CPU5_1, + .cal_offsets =3D { 0x18, 0x19 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x200, + .mode =3D LVTS_MSR_ATP_MODE, + }, + { + .lvts_sensor =3D { + { .dt_id =3D MT8196_MCU_DSU0, + .cal_offsets =3D { 0x1E, 0x1F } }, + { .dt_id =3D MT8196_MCU_DSU1, + .cal_offsets =3D { 0x1C, 0x1D } }, + { .dt_id =3D MT8196_MCU_BIG_CPU7_0, + .cal_offsets =3D { 0x22, 0x23 } }, + { .dt_id =3D MT8196_MCU_BIG_CPU7_1, + .cal_offsets =3D { 0x20, 0x21 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x300, + .mode =3D LVTS_MSR_ATP_MODE, + } +}; + +static const struct lvts_ctrl_data mt8196_lvts_ap_data_ctrl[] =3D { + { + .lvts_sensor =3D { + { .dt_id =3D MT8196_AP_TOP0, + .cal_offsets =3D { 0x32, 0x33 } }, + { .dt_id =3D MT8196_AP_TOP1, + .cal_offsets =3D { 0x30, 0x31 } }, + { .dt_id =3D MT8196_AP_TOP2, + .cal_offsets =3D { 0x36, 0x37 } }, + { .dt_id =3D MT8196_AP_TOP3, + .cal_offsets =3D { 0x34, 0x35 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x0, + .mode =3D LVTS_MSR_ATP_MODE, + }, + { + .lvts_sensor =3D { + { .dt_id =3D MT8196_AP_BOT0, + .cal_offsets =3D { 0x3A, 0x3B } }, + { .dt_id =3D MT8196_AP_BOT1, + .cal_offsets =3D { 0x38, 0x39 } }, + { .dt_id =3D MT8196_AP_BOT2, + .cal_offsets =3D { 0x3E, 0x3F } }, + { .dt_id =3D MT8196_AP_BOT3, + .cal_offsets =3D { 0x3C, 0x3D } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x100, + .mode =3D LVTS_MSR_ATP_MODE, + } +}; + static const struct lvts_platform_ops lvts_platform_ops_v1 =3D { .lvts_raw_to_temp =3D lvts_raw_to_temp, .lvts_temp_to_raw =3D lvts_temp_to_raw, }; =20 +static const struct lvts_platform_ops lvts_platform_ops_v2 =3D { + .lvts_raw_to_temp =3D lvts_raw_to_temp, + .lvts_temp_to_raw =3D lvts_temp_to_raw_v2, +}; + static const struct lvts_data mt7988_lvts_ap_data =3D { .lvts_ctrl =3D mt7988_lvts_ap_data_ctrl, .conn_cmd =3D mt7988_conn_cmds, @@ -1953,6 +2091,30 @@ static const struct lvts_data mt8195_lvts_ap_data = =3D { .ops =3D &lvts_platform_ops_v1, }; =20 +static const struct lvts_data mt8196_lvts_mcu_data =3D { + .lvts_ctrl =3D mt8196_lvts_mcu_data_ctrl, + .num_lvts_ctrl =3D ARRAY_SIZE(mt8196_lvts_mcu_data_ctrl), + .temp_factor =3D LVTS_COEFF_A_MT8196, + .temp_offset =3D LVTS_COEFF_B_MT8196, + .gt_calib_bit_offset =3D 0, + .def_calibration =3D 14437, + .num_cal_offsets =3D 2, + .msr_offset =3D LVTS_MSR_OFFSET_MT8196, + .ops =3D &lvts_platform_ops_v2, +}; + +static const struct lvts_data mt8196_lvts_ap_data =3D { + .lvts_ctrl =3D mt8196_lvts_ap_data_ctrl, + .num_lvts_ctrl =3D ARRAY_SIZE(mt8196_lvts_ap_data_ctrl), + .temp_factor =3D LVTS_COEFF_A_MT8196, + .temp_offset =3D LVTS_COEFF_B_MT8196, + .gt_calib_bit_offset =3D 0, + .def_calibration =3D 14437, + .num_cal_offsets =3D 2, + .msr_offset =3D LVTS_MSR_OFFSET_MT8196, + .ops =3D &lvts_platform_ops_v2, +}; + static const struct of_device_id lvts_of_match[] =3D { { .compatible =3D "mediatek,mt7988-lvts-ap", .data =3D &mt7988_lvts_ap_da= ta }, { .compatible =3D "mediatek,mt8186-lvts", .data =3D &mt8186_lvts_data }, @@ -1962,6 +2124,8 @@ static const struct of_device_id lvts_of_match[] =3D { { .compatible =3D "mediatek,mt8192-lvts-ap", .data =3D &mt8192_lvts_ap_da= ta }, { .compatible =3D "mediatek,mt8195-lvts-mcu", .data =3D &mt8195_lvts_mcu_= data }, { .compatible =3D "mediatek,mt8195-lvts-ap", .data =3D &mt8195_lvts_ap_da= ta }, + { .compatible =3D "mediatek,mt8196-lvts-mcu", .data =3D &mt8196_lvts_mcu_= data }, + { .compatible =3D "mediatek,mt8196-lvts-ap", .data =3D &mt8196_lvts_ap_da= ta }, {}, }; MODULE_DEVICE_TABLE(of, lvts_of_match); --=20 2.39.5 From nobody Sun Feb 8 05:20:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06D2833EB19; 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Thu, 16 Oct 2025 16:22:52 +0200 (CEST) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, Laura Nao Subject: [PATCH RESEND v3 9/9] dt-bindings: nvmem: mediatek: efuse: Add support for MT8196 Date: Thu, 16 Oct 2025 16:21:58 +0200 Message-Id: <20251016142158.740242-10-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251016142158.740242-1-laura.nao@collabora.com> References: <20251016142158.740242-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8196 eFuse layout is compatible with MT8186 and shares the same decoding scheme for the gpu-speedbin cell. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Tested-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Tested-by: Frank Wunderlich --- Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/= Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml index 4dc0d42df3e6..c90b026e40bd 100644 --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -25,7 +25,9 @@ properties: compatible: oneOf: - items: - - const: mediatek,mt8188-efuse + - enum: + - mediatek,mt8196-efuse + - mediatek,mt8188-efuse - const: mediatek,mt8186-efuse - const: mediatek,mt8186-efuse =20 --=20 2.39.5