From nobody Mon Feb 9 04:07:52 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9FB131D63E6; Thu, 16 Oct 2025 13:18:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760620732; cv=none; b=fn5QEGXH0eYFNTSwlbl2qB4qrswIgyz3zt6LhgLoHorn710ueKN/GDQD5MeSv2Gy2ImV514J75C/1qNo5SOA/hz23s4n/tiW3r5GyQWvfLsKE9q7fKhr3kE2+KbuKQswOvVcsdMwPPFGXVrwCqlsbsjosah47sY1YN/AfKUvwLs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760620732; c=relaxed/simple; bh=2qcnQgEDhTUPdfhZAY1SrAh7NDGxOjwEzb5n6TAHyaA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JtW+FVaT8N8vzwk8RSESB7oAG797pJH4O4DsO5BIAFn00I9TlET6OpIQa6+7T0uOlqLFPrO+fOT4y2o6EwBmq+wnWfgMjWwC9RmKhKqra7a6ga4/oJvjSyQZzEjy/v7T2wkfKpZaEAclKcbDAcp06xRXKUxYxinqoZBvnHAYcXk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: kYS7lpWDTNepoh9RVyXG3A== X-CSE-MsgGUID: gk5yvKMlQguYknpZtxDCiA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 16 Oct 2025 22:13:39 +0900 Received: from vm01.adwin.renesas.com (unknown [10.226.92.8]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 97BB941CB11F; Thu, 16 Oct 2025 22:13:34 +0900 (JST) From: Ovidiu Panait To: john.madieu.xa@bp.renesas.com, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 1/3] clk: renesas: r9a09g057: Add clock and reset entries for TSU Date: Thu, 16 Oct 2025 13:13:25 +0000 Message-ID: <20251016131327.19141-2-ovidiu.panait.rb@renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251016131327.19141-1-ovidiu.panait.rb@renesas.com> References: <20251016131327.19141-1-ovidiu.panait.rb@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add module clock and reset entries for the TSU0 and TSU1 blocks on the Renesas RZ/V2H (R9A09G057) SoC. Signed-off-by: Ovidiu Panait --- drivers/clk/renesas/r9a09g057-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a0= 9g057-cpg.c index 4e47fea3f894..e865a70a7f25 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -379,6 +379,10 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[]= __initconst =3D { BUS_MSTOP(3, BIT(4))), DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, BUS_MSTOP(3, BIT(4))), + DEF_MOD("tsu_0_pclk", CLK_QEXTAL, 16, 9, 8, 9, + BUS_MSTOP(5, BIT(2))), + DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, + BUS_MSTOP(2, BIT(15))), }; =20 static const struct rzv2h_reset r9a09g057_resets[] __initconst =3D { @@ -449,6 +453,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __in= itconst =3D { DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */ DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */ DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */ + DEF_RST(15, 7, 7, 8), /* TSU_0_PRESETN */ + DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ }; =20 const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst =3D { --=20 2.51.0 From nobody Mon Feb 9 04:07:52 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D6AEF1D63F0; Thu, 16 Oct 2025 13:18:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760620730; cv=none; b=LC0nT6jjaPByK9kC5QS5EP3j+Lz4cDRVXEuHjOvFThKZi1XxwRDWNjAJ5g30sncEVWcbLxMw/tMpgaHtyJI37r2LUAT74m/Ewtt1eb8QhtZGfdz75FQxpk3X087WFDeyDfIG9ItvuGtWYmi3hJBMmThn1iLS2m179Qe50PwXBWc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760620730; c=relaxed/simple; bh=zBXrZrK2pRBw62/rc5VYqqaYyjnXzLoQl9YKGS8Eivw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=anHNGceuikx4OllfaQDc+DmrMTdV28lrJX+fDLsLmKja0dVYj2YKvXq6g3TAKfKRMTPLOVpR+6JPH7dBYA4g1nOFRdapT/WUzX2bNywVU7mTf8vj9pK3mDPAOXz9pQYdz7LBLePY7QeCkV+j3rOUxnM5IihSWveyvb2Dco+BaS4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: 1Q9Aj23YQpC/OfblMUuLWA== X-CSE-MsgGUID: C109HfjMSFGLFhEVNyXkjA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 16 Oct 2025 22:13:45 +0900 Received: from vm01.adwin.renesas.com (unknown [10.226.92.8]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 7AB5941CB11F; Thu, 16 Oct 2025 22:13:40 +0900 (JST) From: Ovidiu Panait To: john.madieu.xa@bp.renesas.com, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/3] dt-bindings: thermal: r9a09g047-tsu: Document RZ/V2H TSU Date: Thu, 16 Oct 2025 13:13:26 +0000 Message-ID: <20251016131327.19141-3-ovidiu.panait.rb@renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251016131327.19141-1-ovidiu.panait.rb@renesas.com> References: <20251016131327.19141-1-ovidiu.panait.rb@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/V2H SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing two dedicated channels for temperature sensing. The Renesas RZ/V2H SoC is using the same TSU IP found on the RZ/G3E SoC, the only difference being that it has two channels instead of one. Add new compatible string "renesas,r9a09g057-tsu" for RZ/V2H and use "renesas,r9a09g047-tsu" as a fallback compatible to indicate hardware compatibility with the RZ/G3E implementation. Signed-off-by: Ovidiu Panait Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-ts= u.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.ya= ml index 8d3f3c24f0f2..274e96e37a12 100644 --- a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml @@ -16,7 +16,12 @@ description: =20 properties: compatible: - const: renesas,r9a09g047-tsu + oneOf: + - items: + - const: renesas,r9a09g047-tsu # RZ/G3E + - items: + - const: renesas,r9a09g057-tsu # RZ/V2H + - const: renesas,r9a09g047-tsu # RZ/G3E =20 reg: maxItems: 1 --=20 2.51.0 From nobody Mon Feb 9 04:07:52 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B5D6C32BF4E; Thu, 16 Oct 2025 13:18:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760620736; cv=none; b=QX5dkTwmrKpQgxxgPPYHy9MVswH87bL/0ke6MiZFoQqwM+K78oo9NsawshxycPRcd0FH7hjQJXEghdZ88FR/iHD5rreltYVxSOmEVUKIVIGg/xlD7Toz1SmdoEg/Zapllj63Cy1R3PeoJwsdxnLWiQrqLN8EntUqzb4kqDV5Vvs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760620736; c=relaxed/simple; bh=azS+cM6Lp8W1wqmvaDSOGvNQ1AiY4Nlu4oPCO3Z97RA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c6hUGT3eC+QvkvIHGS7Csmn/h2k+zkmox6Fr4Z7mYV4M2DBLlLUvyBzZjgsmx1cyp+r+jfRakA17EhPiGWOSYKs+oh0HF+Qv1x4AFmE6hKpwRjNYfEG9JFElC1wlJNA8Zetz1XrUX+1xJx3RPGrY/squ2N4UbZV3yDhP9oEU7p0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: KtNcrM/sRKicY28FFlpLWA== X-CSE-MsgGUID: C/XDfOunRoyvKHSAMEonLg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 16 Oct 2025 22:13:51 +0900 Received: from vm01.adwin.renesas.com (unknown [10.226.92.8]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 5BDE741CB11F; Thu, 16 Oct 2025 22:13:46 +0900 (JST) From: Ovidiu Panait To: john.madieu.xa@bp.renesas.com, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 3/3] arm64: dts: renesas: r9a09g057: Add TSU nodes Date: Thu, 16 Oct 2025 13:13:27 +0000 Message-ID: <20251016131327.19141-4-ovidiu.panait.rb@renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251016131327.19141-1-ovidiu.panait.rb@renesas.com> References: <20251016131327.19141-1-ovidiu.panait.rb@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/V2H SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing two dedicated channels for temperature sensing: - TSU0, which is located near the DRP-AI block - TSU1, which is located near the CPU and DRP-AI block Since TSU1 is physically closer the CPU and the highest temperature spot, it is used for CPU throttling through a passive trip and cooling map. TSU0 is configured only with a critical trip. Add TSU nodes along with thermal zones and keep them enabled in the SoC DTSI. Signed-off-by: Ovidiu Panait --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 75 ++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g057.dtsi index e426b9978e22..e88cfc965415 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -65,6 +65,7 @@ cpu0: cpu@0 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -75,6 +76,7 @@ cpu1: cpu@100 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -85,6 +87,7 @@ cpu2: cpu@200 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -95,6 +98,7 @@ cpu3: cpu@300 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -285,6 +289,32 @@ sys: system-controller@10430000 { resets =3D <&cpg 0x30>; }; =20 + tsu0: thermal@11000000 { + compatible =3D "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; + reg =3D <0 0x11000000 0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + clocks =3D <&cpg CPG_MOD 0x109>; + resets =3D <&cpg 0xf7>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + renesas,tsu-trim =3D <&sys 0x320>; + }; + + tsu1: thermal@14002000 { + compatible =3D "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; + reg =3D <0 0x14002000 0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + clocks =3D <&cpg CPG_MOD 0x10a>; + resets =3D <&cpg 0xf8>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + renesas,tsu-trim =3D <&sys 0x330>; + }; + xspi: spi@11030000 { compatible =3D "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi"; reg =3D <0 0x11030000 0 0x10000>, @@ -1326,6 +1356,51 @@ stmmac_axi_setup: stmmac-axi-config { snps,blen =3D <16 8 4 0 0 0 0>; }; =20 + thermal-zones { + sensor1_thermal: sensor1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&tsu0>; + + trips { + sensor1_crit: sensor1-crit { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + sensor2_thermal: sensor2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&tsu1>; + + cooling-maps { + map0 { + trip =3D <&sensor2_target>; + cooling-device =3D <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution =3D <1024>; + }; + }; + + trips { + sensor2_target: trip-point { + temperature =3D <95000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + sensor2_crit: sensor2-crit { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts =3D , --=20 2.51.0