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(unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 262659583; Thu, 16 Oct 2025 20:06:45 +0800 (GMT+08:00) From: Albert Yang To: krzysztof.kozlowski@linaro.org Cc: krzk+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, robh@kernel.org, conor+dt@kernel.org, gordon.ge@bst.ai, bst-upstream@bstai.top, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ulf.hansson@linaro.org, Albert Yang Subject: [PATCH v5 4/6] arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board Date: Thu, 16 Oct 2025 20:05:56 +0800 Message-ID: <20251016120558.2390960-5-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251016120558.2390960-1-yangzh0906@thundersoft.com> References: <20251016120558.2390960-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a99ecea59fd09cckunm98a0ee061286f X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCTB0fVkkaSB1CTh0YHxpKSVYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpMQ0pVSk tLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=doFL9ykVQuefPyZEzCW2J57Hve3SunD89k/SKTNqhW08/MgTM87ich3lthKkId4fXy6t/jO0vFsJxgDvvKdslV1eQADUdg/pOryXtrGz/5AZxofUlS/U+ysNGqsrsxDYekkrQOBmp/cuT8aX9kRc8l5GDaHjPpucr2IYDWvFCUo=; s=default; c=relaxed/relaxed; d=thundersoft.com; v=1; bh=tAjqHgz4wG6e8OoGjwLbo8Eew2f6czwuezyx8+YqnRU=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add device tree support for the Black Sesame Technologies (BST) C1200 CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC family. The changes include: - Adding a new BST device tree directory - Adding Makefile entries to build the BST platform device trees - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board This board features a quad-core Cortex-A78 CPU, and various peripherals including UART, and interrupt controller. Signed-off-by: Albert Yang --- Changes for v5: - Remove MMC node and MMC clock from SoC DTSI completely (MMC driver and bi= ndings will be submitted separately) - Remove MMC node override in board DTS Changes for v4: - Remove Signed-off-by line for Ge Gordon - Reorder device tree node properties for better consistency - CPU nodes: move `device_type` before `compatible`, add explicit `reg` val= ues - MMC node: change compatible from `bst,c1200-dwcmshc-sdhci` to `bst,c1200-= sdhci` - MMC node: remove `bus-width` and `non-removable` from SoC dtsi, move to b= oard dts - SoC node: reorder properties (`ranges` before address/size cells) - UART node: reorder properties (clock-frequency before interrupts) - GIC node: reorder properties for better readability - Timer node: reorder properties (always-on before interrupt-parent) - Board DTS: add `bus-width =3D <8>` and `non-removable` to MMC node - Board DTS: reorder MMC and UART node references Changes for v3: - Split defconfig enablement out into a dedicated defconfig patch - Refine memory description: consolidate ranges in memory node and delete u= nused memory ranges - Adjust the order of nodes - Remove mask of gic Changes for v2: - Reorganize memory map into discrete regions - Update MMC controller definition with split core/CRM register regions - Remove deprecated properties - Update compatible string - Standardize interrupt definitions and numeric formats - Remove reserved-memory node (superseded by bounce buffers) - Add root compatible string for platform identification - Add soc defconfig --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/bst/Makefile | 2 + .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 24 +++++ arch/arm64/boot/dts/bst/bstc1200.dtsi | 97 +++++++++++++++++++ 4 files changed, 124 insertions(+) create mode 100644 arch/arm64/boot/dts/bst/Makefile create mode 100644 arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts create mode 100644 arch/arm64/boot/dts/bst/bstc1200.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index b0844404eda1..98ec8f1b76e4 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -13,6 +13,7 @@ subdir-y +=3D axiado subdir-y +=3D bitmain subdir-y +=3D blaize subdir-y +=3D broadcom +subdir-y +=3D bst subdir-y +=3D cavium subdir-y +=3D cix subdir-y +=3D exynos diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Mak= efile new file mode 100644 index 000000000000..4c1b8b4cdad8 --- /dev/null +++ b/arch/arm64/boot/dts/bst/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BST) +=3D bstc1200-cdcu1.0-adas_4c2g.dtb diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/= arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts new file mode 100644 index 000000000000..5eb9ef369d8c --- /dev/null +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "bstc1200.dtsi" + +/ { + model =3D "BST C1200-96 CDCU1.0 4C2G"; + compatible =3D "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@810000000 { + device_type =3D "memory"; + reg =3D <0x8 0x10000000 0x0 0x30000000>, + <0x8 0xc0000000 0x1 0x0>, + <0xc 0x00000000 0x0 0x40000000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bs= t/bstc1200.dtsi new file mode 100644 index 000000000000..dd13c6bfc3c8 --- /dev/null +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +/ { + compatible =3D "bst,c1200"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + }; + + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + }; + + cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + }; + + cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + }; + + l2_cache: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + uart0: serial@20008000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x20008000 0x0 0x1000>; + clock-frequency =3D <25000000>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + gic: interrupt-controller@32800000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x32800000 0x0 0x10000>, + <0x0 0x32880000 0x0 0x100000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + always-on; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; +}; --=20 2.43.0