From nobody Mon Feb 9 14:34:35 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 646012D4803; Thu, 16 Oct 2025 10:44:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760611460; cv=none; b=L2cRtXQXbKZdc0TpEaW5ojofGIsnLiKC3pzQnFcRkLRap0KZfbHR8fSyDlgtb0hCprFHDXRZMkcBIXWsOynxYjglUXIcQz5CRx+/LwEu8GN26vGuze78Imt16E8j/UOIAxUlhd/8IeI6GavdDCMY9/qSqWTcHovd4oq2vC9S0V4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760611460; c=relaxed/simple; bh=GNGbXkx5g66KghcuTCF7WYhpXkKwkYjL1KKYUygGq/s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MkjS8+X1m132aGGi20/5OHQpp9ZpCS/S6zSgw0DRIm9dWmf8e4I3cOWJtd5ZBtJ5dvPMUvKcRFatmxFvIjvD//7/MEGPrTjGwyzHHRBd4I8WHkmUP7TSsVl/cfWJV0iK2HwcHDpfJd7EwN6gHIxfxeEae7/wOw8UMO6w3Bvjbls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=OETseGVq; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="OETseGVq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1760611456; bh=GNGbXkx5g66KghcuTCF7WYhpXkKwkYjL1KKYUygGq/s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OETseGVqfOq04SqEZJiNQ1iMjUJmDDzxjybto6AD4cQe+Dao3b2D8JKJrWO0TyH5Q WB5pN81ydtDZi1daFt6F9QvHBTvcDu/wfYndHK3tDpETZCFBzzYElOme/7ibnhAgpn Hp0G/aHDQG9HsAFU5XenCtNtPOdOkTeyIGfwMoe4zEVpega5fDATtsvFKcEFhP17wd 4NAQLLgWmZiHFrLu1nLZVYTSPfVKEBSRSdn4cdfntZ/dOzJMbBqljN+BSFb9iHzJ+8 zzwP5gXM7DQN6kxHFiuwWx+yp8B2s0vOJv43MMoi3omfZiz+rC0IC3lBYYieLvTa9Q k73DMwLFxev1w== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9D3AB17E0CF8; Thu, 16 Oct 2025 12:44:15 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org, casey.connolly@linaro.org, AngeloGioacchino Del Regno Subject: [PATCH v6 1/8] spmi: Print error status with %pe format Date: Thu, 16 Oct 2025 12:43:55 +0200 Message-ID: <20251016104402.338246-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251016104402.338246-1-angelogioacchino.delregno@collabora.com> References: <20251016104402.338246-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Instead of printing just a number, use the %pe format for error status, increasing readability of error prints. Signed-off-by: AngeloGioacchino Del Regno --- drivers/spmi/spmi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c index 3cf8d9bd4566..bcb71f25194f 100644 --- a/drivers/spmi/spmi.c +++ b/drivers/spmi/spmi.c @@ -68,8 +68,8 @@ int spmi_device_add(struct spmi_device *sdev) =20 err =3D device_add(&sdev->dev); if (err < 0) { - dev_err(&sdev->dev, "Can't add %s, status %d\n", - dev_name(&sdev->dev), err); + dev_err(&sdev->dev, "Can't add %s, status %pe\n", + dev_name(&sdev->dev), ERR_PTR(err)); goto err_device_add; } =20 @@ -494,8 +494,8 @@ static void of_spmi_register_devices(struct spmi_contro= ller *ctrl) err =3D of_property_read_u32_array(node, "reg", reg, 2); if (err) { dev_err(&ctrl->dev, - "node %pOF err (%d) does not have 'reg' property\n", - node, err); + "node %pOF err (%pe) does not have 'reg' property\n", + node, ERR_PTR(err)); continue; } =20 @@ -523,7 +523,7 @@ static void of_spmi_register_devices(struct spmi_contro= ller *ctrl) err =3D spmi_device_add(sdev); if (err) { dev_err(&sdev->dev, - "failure adding device. status %d\n", err); + "failure adding device. status %pe\n", ERR_PTR(err)); spmi_device_put(sdev); } } --=20 2.51.0 From nobody Mon Feb 9 14:34:35 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6469B2E172E; Thu, 16 Oct 2025 10:44:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760611461; cv=none; b=T/WW8BlGfX/9kCFSzSrin6G4KBBTE4o4TGWwnOvs4a5vSlAtofD9FLNi5Imf+j4hpWsXm6We6YVKUHC6I0YiMTa4EQmPVELXrbqt0JoXrZ/4JqcP4ht3EDZ8Z4FwbQfJVrXiHix/GjTvyqp6DN53F2gftNixR0gp2b1uUSo40EU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760611461; c=relaxed/simple; bh=cP0P8mnb1hkjMQYI1W3IQNrFA+nT6mCV9ZFGp5wTvcs=; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cHC6PkIiIxVMd1oWa9ZqBC672+2FDuWofLQ34PrbtfQlDX87wZxH1dvZD7SXA+usg o5gD/AZyHUrMj9u2W+qYxI1uRYiNsAqzL+CRUrmrfgrLH64/wFKLyO4TjoDiQIHlNP u7U5eRDYYizokYhc/gGrqxOwFWzdX4MJGGLNoASoYPiqDdGm+6Ch1U5Qvx/x+aM0yF qq20FIwfbHt31wTHg+N6xKuQfD6uWMxbC/FjJ1CcR+wavRdEUHgsGTbOTm3skpa2WS Qer40YEOrdAVtW33GxSv6NFUhGDp8i7pAy8xtV20AI6xk2PvlMWWSkAHdLvHnOpxSz je/Q38F7SfMMA== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id B6D3A17E0FC2; Thu, 16 Oct 2025 12:44:16 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org, casey.connolly@linaro.org, Jonathan Cameron , Neil Armstrong Subject: [PATCH v6 2/8] spmi: Implement spmi_subdevice_alloc_and_add() and devm variant Date: Thu, 16 Oct 2025 12:43:56 +0200 Message-ID: <20251016104402.338246-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251016104402.338246-1-angelogioacchino.delregno@collabora.com> References: <20251016104402.338246-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some devices connected over the SPMI bus may be big, in the sense that those may be a complex of devices managed by a single chip over the SPMI bus, reachable through a single SID. Add new functions aimed at managing sub-devices of a SPMI device spmi_subdevice_alloc_and_add() and a spmi_subdevice_put_and_remove() for adding a new subdevice and removing it respectively, and also add their devm_* variants. The need for such functions comes from the existence of those complex Power Management ICs (PMICs), which feature one or many sub-devices, in some cases with these being even addressable on the chip in form of SPMI register ranges. Examples of those devices can be found in both Qualcomm platforms with their PMICs having PON, RTC, SDAM, GPIO controller, and other sub-devices, and in newer MediaTek platforms showing similar HW features and a similar layout with those also having many subdevs. Also, instead of generally exporting symbols, export them with a new "SPMI" namespace: all users will have to import this namespace to make use of the newly introduced exports. Reviewed-by: Jonathan Cameron Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: AngeloGioacchino Del Regno --- drivers/spmi/spmi-devres.c | 24 ++++++++++++ drivers/spmi/spmi.c | 79 ++++++++++++++++++++++++++++++++++++++ include/linux/spmi.h | 16 ++++++++ 3 files changed, 119 insertions(+) diff --git a/drivers/spmi/spmi-devres.c b/drivers/spmi/spmi-devres.c index 62c4b3f24d06..8feebab0365b 100644 --- a/drivers/spmi/spmi-devres.c +++ b/drivers/spmi/spmi-devres.c @@ -60,5 +60,29 @@ int devm_spmi_controller_add(struct device *parent, stru= ct spmi_controller *ctrl } EXPORT_SYMBOL_GPL(devm_spmi_controller_add); =20 +static void devm_spmi_subdevice_remove(void *res) +{ + spmi_subdevice_remove(res); +} + +struct spmi_subdevice *devm_spmi_subdevice_alloc_and_add(struct device *de= v, + struct spmi_device *sparent) +{ + struct spmi_subdevice *sub_sdev; + int ret; + + sub_sdev =3D spmi_subdevice_alloc_and_add(sparent); + if (IS_ERR(sub_sdev)) + return sub_sdev; + + ret =3D devm_add_action_or_reset(dev, devm_spmi_subdevice_remove, sub_sde= v); + if (ret) + return ERR_PTR(ret); + + return sub_sdev; +} +EXPORT_SYMBOL_NS_GPL(devm_spmi_subdevice_alloc_and_add, "SPMI"); + MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("SPMI devres helpers"); +MODULE_IMPORT_NS("SPMI"); diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c index bcb71f25194f..37e91932a01d 100644 --- a/drivers/spmi/spmi.c +++ b/drivers/spmi/spmi.c @@ -19,6 +19,7 @@ =20 static bool is_registered; static DEFINE_IDA(ctrl_ida); +static DEFINE_IDA(spmi_subdevice_ida); =20 static void spmi_dev_release(struct device *dev) { @@ -31,6 +32,19 @@ static const struct device_type spmi_dev_type =3D { .release =3D spmi_dev_release, }; =20 +static void spmi_subdev_release(struct device *dev) +{ + struct spmi_device *sdev =3D to_spmi_device(dev); + struct spmi_subdevice *sub_sdev =3D container_of(sdev, struct spmi_subdev= ice, sdev); + + ida_free(&spmi_subdevice_ida, sub_sdev->devid); + kfree(sub_sdev); +} + +static const struct device_type spmi_subdev_type =3D { + .release =3D spmi_subdev_release, +}; + static void spmi_ctrl_release(struct device *dev) { struct spmi_controller *ctrl =3D to_spmi_controller(dev); @@ -90,6 +104,18 @@ void spmi_device_remove(struct spmi_device *sdev) } EXPORT_SYMBOL_GPL(spmi_device_remove); =20 +/** + * spmi_subdevice_remove() - Remove an SPMI subdevice + * @sub_sdev: spmi_device to be removed + */ +void spmi_subdevice_remove(struct spmi_subdevice *sub_sdev) +{ + struct spmi_device *sdev =3D &sub_sdev->sdev; + + device_unregister(&sdev->dev); +} +EXPORT_SYMBOL_NS_GPL(spmi_subdevice_remove, "SPMI"); + static inline int spmi_cmd(struct spmi_controller *ctrl, u8 opcode, u8 sid) { @@ -431,6 +457,59 @@ struct spmi_device *spmi_device_alloc(struct spmi_cont= roller *ctrl) } EXPORT_SYMBOL_GPL(spmi_device_alloc); =20 +/** + * spmi_subdevice_alloc_and_add(): Allocate and add a new SPMI sub-device + * @sparent: SPMI parent device with previously registered SPMI controller + * + * Returns: + * Pointer to newly allocated SPMI sub-device for success or negative ERR_= PTR. + */ +struct spmi_subdevice *spmi_subdevice_alloc_and_add(struct spmi_device *sp= arent) +{ + struct spmi_subdevice *sub_sdev; + struct spmi_device *sdev; + int ret; + + sub_sdev =3D kzalloc(sizeof(*sub_sdev), GFP_KERNEL); + if (!sub_sdev) + return ERR_PTR(-ENOMEM); + + ret =3D ida_alloc(&spmi_subdevice_ida, GFP_KERNEL); + if (ret < 0) { + kfree(sub_sdev); + return ERR_PTR(ret); + } + + sdev =3D &sub_sdev->sdev; + sdev->ctrl =3D sparent->ctrl; + device_initialize(&sdev->dev); + sdev->dev.parent =3D &sparent->dev; + sdev->dev.bus =3D &spmi_bus_type; + sdev->dev.type =3D &spmi_subdev_type; + + sub_sdev->devid =3D ret; + sdev->usid =3D sparent->usid; + + ret =3D dev_set_name(&sdev->dev, "%d-%02x.%d.auto", + sdev->ctrl->nr, sdev->usid, sub_sdev->devid); + if (ret) + goto err_put_dev; + + ret =3D device_add(&sdev->dev); + if (ret) { + dev_err(&sdev->dev, "Can't add %s, status %pe\n", + dev_name(&sdev->dev), ERR_PTR(ret)); + goto err_put_dev; + } + + return sub_sdev; + +err_put_dev: + put_device(&sdev->dev); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_NS_GPL(spmi_subdevice_alloc_and_add, "SPMI"); + /** * spmi_controller_alloc() - Allocate a new SPMI controller * @parent: parent device diff --git a/include/linux/spmi.h b/include/linux/spmi.h index 28e8c8bd3944..7cea0a5b034b 100644 --- a/include/linux/spmi.h +++ b/include/linux/spmi.h @@ -69,6 +69,22 @@ int spmi_device_add(struct spmi_device *sdev); =20 void spmi_device_remove(struct spmi_device *sdev); =20 +/** + * struct spmi_subdevice - Basic representation of an SPMI sub-device + * @sdev: Sub-device representation of an SPMI device + * @devid: Platform Device ID of an SPMI sub-device + */ +struct spmi_subdevice { + struct spmi_device sdev; + unsigned int devid; +}; + +struct spmi_subdevice *spmi_subdevice_alloc_and_add(struct spmi_device *sp= arent); +void spmi_subdevice_remove(struct spmi_subdevice *sdev); + +struct spmi_subdevice *devm_spmi_subdevice_alloc_and_add(struct device *de= v, + struct spmi_device *sparent); + /** * struct spmi_controller - interface to the SPMI master controller * @dev: Driver model representation of the device. --=20 2.51.0 From nobody Mon Feb 9 14:34:36 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8341A31E115; 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Thu, 16 Oct 2025 12:44:17 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org, casey.connolly@linaro.org, Konrad Dybcio , Neil Armstrong Subject: [PATCH v6 3/8] nvmem: qcom-spmi-sdam: Migrate to devm_spmi_subdevice_alloc_and_add() Date: Thu, 16 Oct 2025 12:43:57 +0200 Message-ID: <20251016104402.338246-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251016104402.338246-1-angelogioacchino.delregno@collabora.com> References: <20251016104402.338246-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Qualcomm PMICs integrate a SDAM device, internally located in a specific address range reachable through SPMI communication. Instead of using the parent SPMI device (the main PMIC) as a kind of syscon in this driver, register a new SPMI sub-device for SDAM and initialize its own regmap with this sub-device's specific base address, retrieved from the devicetree. This allows to stop manually adding the register base address to every R/W call in this driver, as this can be, and is now, handled by the regmap API instead. Reviewed-by: Konrad Dybcio Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: AngeloGioacchino Del Regno --- drivers/nvmem/Kconfig | 1 + drivers/nvmem/qcom-spmi-sdam.c | 36 +++++++++++++++++++++++----------- 2 files changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index e0d88d3199c1..23858269b61f 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -359,6 +359,7 @@ config NVMEM_SNVS_LPGPR config NVMEM_SPMI_SDAM tristate "SPMI SDAM Support" depends on SPMI + select REGMAP_SPMI help This driver supports the Shared Direct Access Memory Module on Qualcomm Technologies, Inc. PMICs. It provides the clients diff --git a/drivers/nvmem/qcom-spmi-sdam.c b/drivers/nvmem/qcom-spmi-sdam.c index 4f1cca6eab71..2bb7b3bc497e 100644 --- a/drivers/nvmem/qcom-spmi-sdam.c +++ b/drivers/nvmem/qcom-spmi-sdam.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 #define SDAM_MEM_START 0x40 #define REGISTER_MAP_ID 0x40 @@ -20,7 +21,6 @@ struct sdam_chip { struct regmap *regmap; struct nvmem_config sdam_config; - unsigned int base; unsigned int size; }; =20 @@ -73,7 +73,7 @@ static int sdam_read(void *priv, unsigned int offset, voi= d *val, return -EINVAL; } =20 - rc =3D regmap_bulk_read(sdam->regmap, sdam->base + offset, val, bytes); + rc =3D regmap_bulk_read(sdam->regmap, offset, val, bytes); if (rc < 0) dev_err(dev, "Failed to read SDAM offset %#x len=3D%zd, rc=3D%d\n", offset, bytes, rc); @@ -100,7 +100,7 @@ static int sdam_write(void *priv, unsigned int offset, = void *val, return -EINVAL; } =20 - rc =3D regmap_bulk_write(sdam->regmap, sdam->base + offset, val, bytes); + rc =3D regmap_bulk_write(sdam->regmap, offset, val, bytes); if (rc < 0) dev_err(dev, "Failed to write SDAM offset %#x len=3D%zd, rc=3D%d\n", offset, bytes, rc); @@ -110,8 +110,17 @@ static int sdam_write(void *priv, unsigned int offset,= void *val, =20 static int sdam_probe(struct platform_device *pdev) { + struct regmap_config sdam_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D 0x100, + .fast_io =3D true, + }; struct sdam_chip *sdam; struct nvmem_device *nvmem; + struct spmi_device *sparent; + struct spmi_subdevice *sub_sdev; + struct device *dev =3D &pdev->dev; unsigned int val; int rc; =20 @@ -119,19 +128,23 @@ static int sdam_probe(struct platform_device *pdev) if (!sdam) return -ENOMEM; =20 - sdam->regmap =3D dev_get_regmap(pdev->dev.parent, NULL); - if (!sdam->regmap) { - dev_err(&pdev->dev, "Failed to get regmap handle\n"); - return -ENXIO; - } + sparent =3D to_spmi_device(dev->parent); + sub_sdev =3D devm_spmi_subdevice_alloc_and_add(dev, sparent); + if (IS_ERR(sub_sdev)) + return PTR_ERR(sub_sdev); =20 - rc =3D of_property_read_u32(pdev->dev.of_node, "reg", &sdam->base); + rc =3D of_property_read_u32(dev->of_node, "reg", &sdam_regmap_config.reg_= base); if (rc < 0) { dev_err(&pdev->dev, "Failed to get SDAM base, rc=3D%d\n", rc); return -EINVAL; } =20 - rc =3D regmap_read(sdam->regmap, sdam->base + SDAM_SIZE, &val); + sdam->regmap =3D devm_regmap_init_spmi_ext(&sub_sdev->sdev, &sdam_regmap_= config); + if (IS_ERR(sdam->regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(sdam->regmap), + "Failed to get regmap handle\n"); + + rc =3D regmap_read(sdam->regmap, SDAM_SIZE, &val); if (rc < 0) { dev_err(&pdev->dev, "Failed to read SDAM_SIZE rc=3D%d\n", rc); return -EINVAL; @@ -159,7 +172,7 @@ static int sdam_probe(struct platform_device *pdev) } dev_dbg(&pdev->dev, "SDAM base=3D%#x size=3D%u registered successfully\n", - sdam->base, sdam->size); + sdam_regmap_config.reg_base, sdam->size); =20 return 0; } @@ -181,3 +194,4 @@ module_platform_driver(sdam_driver); =20 MODULE_DESCRIPTION("QCOM SPMI SDAM driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("SPMI"); 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Thu, 16 Oct 2025 12:44:18 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org, casey.connolly@linaro.org, Sebastian Reichel , Neil Armstrong Subject: [PATCH v6 4/8] power: reset: qcom-pon: Migrate to devm_spmi_subdevice_alloc_and_add() Date: Thu, 16 Oct 2025 12:43:58 +0200 Message-ID: <20251016104402.338246-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251016104402.338246-1-angelogioacchino.delregno@collabora.com> References: <20251016104402.338246-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Qualcomm PMICs integrates a Power On device supporting pwrkey and resin along with the Android reboot reason action identifier. Instead of using the parent SPMI device (the main PMIC) as a kind of syscon in this driver, register a new SPMI sub-device for PON and initialize its own regmap with this sub-device's specific base address, retrieved from the devicetree. This allows to stop manually adding the register base address to every R/W call in this driver, as this can be, and is now, handled by the regmap API instead. Reviewed-by: Sebastian Reichel Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: AngeloGioacchino Del Regno --- drivers/power/reset/qcom-pon.c | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/power/reset/qcom-pon.c b/drivers/power/reset/qcom-pon.c index 7e108982a582..0e075a2e5e48 100644 --- a/drivers/power/reset/qcom-pon.c +++ b/drivers/power/reset/qcom-pon.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #define PON_SOFT_RB_SPARE 0x8f =20 @@ -22,7 +23,6 @@ struct qcom_pon { struct device *dev; struct regmap *regmap; - u32 baseaddr; struct reboot_mode_driver reboot_mode; long reason_shift; }; @@ -35,7 +35,7 @@ static int qcom_pon_reboot_mode_write(struct reboot_mode_= driver *reboot, int ret; =20 ret =3D regmap_update_bits(pon->regmap, - pon->baseaddr + PON_SOFT_RB_SPARE, + PON_SOFT_RB_SPARE, GENMASK(7, pon->reason_shift), magic << pon->reason_shift); if (ret < 0) @@ -46,27 +46,42 @@ static int qcom_pon_reboot_mode_write(struct reboot_mod= e_driver *reboot, =20 static int qcom_pon_probe(struct platform_device *pdev) { + struct regmap_config qcom_pon_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D 0x100, + .fast_io =3D true, + }; + struct device *dev =3D &pdev->dev; + struct spmi_subdevice *sub_sdev; + struct spmi_device *sparent; struct qcom_pon *pon; long reason_shift; int error; =20 + if (!dev->parent) + return -ENODEV; + pon =3D devm_kzalloc(&pdev->dev, sizeof(*pon), GFP_KERNEL); if (!pon) return -ENOMEM; =20 pon->dev =3D &pdev->dev; =20 - pon->regmap =3D dev_get_regmap(pdev->dev.parent, NULL); - if (!pon->regmap) { - dev_err(&pdev->dev, "failed to locate regmap\n"); - return -ENODEV; - } + sparent =3D to_spmi_device(dev->parent); + sub_sdev =3D devm_spmi_subdevice_alloc_and_add(dev, sparent); + if (IS_ERR(sub_sdev)) + return PTR_ERR(sub_sdev); =20 - error =3D of_property_read_u32(pdev->dev.of_node, "reg", - &pon->baseaddr); + error =3D of_property_read_u32(dev->of_node, "reg", + &qcom_pon_regmap_config.reg_base); if (error) return error; =20 + pon->regmap =3D devm_regmap_init_spmi_ext(&sub_sdev->sdev, &qcom_pon_regm= ap_config); + if (IS_ERR(pon->regmap)) + return PTR_ERR(pon->regmap); + reason_shift =3D (long)of_device_get_match_data(&pdev->dev); =20 if (reason_shift !=3D NO_REASON_SHIFT) { @@ -106,3 +121,4 @@ module_platform_driver(qcom_pon_driver); =20 MODULE_DESCRIPTION("Qualcomm Power On driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("SPMI"); --=20 2.51.0 From nobody Mon Feb 9 14:34:36 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70DD2320A29; Thu, 16 Oct 2025 10:44:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760611464; cv=none; b=Ctg1NNx6+jGqJzBmXYbnz9V2XuohjnB5GUt1b9qVzdtns5yTG9NAQEi5PK9evhLZzF8OBU2N+30Ua7gvgFhxZYGn38WoP5zFDB+EgKqrsQRz4zLB2CIiZuJgxAUbkbMjzbHQVytaB633C4iHAPdbmSEdSXAJRu8ArOTGmNvfb20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760611464; 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charset="utf-8" Some Qualcomm PMICs integrate an USB Repeater device, used to convert between eUSB2 and USB 2.0 signaling levels, reachable in a specific address range over SPMI. Instead of using the parent SPMI device (the main PMIC) as a kind of syscon in this driver, register a new SPMI sub-device for EUSB2 and initialize its own regmap with this sub-device's specific base address, retrieved from the devicetree. This allows to stop manually adding the register base address to every R/W call in this driver, as this can be, and is now, handled by the regmap API instead. Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/qualcomm/Kconfig | 2 + .../phy/qualcomm/phy-qcom-eusb2-repeater.c | 53 ++++++++++++------- 2 files changed, 36 insertions(+), 19 deletions(-) diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 60a0ead127fa..902a788f35f1 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -128,7 +128,9 @@ config PHY_QCOM_QUSB2 config PHY_QCOM_EUSB2_REPEATER tristate "Qualcomm PMIC eUSB2 Repeater Driver" depends on OF && (ARCH_QCOM || COMPILE_TEST) + depends on SPMI select GENERIC_PHY + select REGMAP_SPMI help Enable support for the USB high-speed eUSB2 repeater on Qualcomm PMICs. The repeater is paired with a Synopsys or M31 eUSB2 Phy diff --git a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c b/drivers/phy/q= ualcomm/phy-qcom-eusb2-repeater.c index 651a12b59bc8..bdeb3c72d26a 100644 --- a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c +++ b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 /* eUSB2 status registers */ #define EUSB2_RPTR_STATUS 0x08 @@ -55,7 +56,6 @@ struct eusb2_repeater { struct phy *phy; struct regulator_bulk_data *vregs; const struct eusb2_repeater_cfg *cfg; - u32 base; enum phy_mode mode; }; =20 @@ -118,7 +118,6 @@ static int eusb2_repeater_init(struct phy *phy) struct eusb2_repeater *rptr =3D phy_get_drvdata(phy); struct device_node *np =3D rptr->dev->of_node; struct regmap *regmap =3D rptr->regmap; - u32 base =3D rptr->base; u32 poll_val; int ret; u8 val; @@ -127,28 +126,28 @@ static int eusb2_repeater_init(struct phy *phy) if (ret) return ret; =20 - regmap_write(regmap, base + EUSB2_EN_CTL1, EUSB2_RPTR_EN); + regmap_write(regmap, EUSB2_EN_CTL1, EUSB2_RPTR_EN); =20 /* Write registers from init table */ for (int i =3D 0; i < rptr->cfg->init_tbl_num; i++) - regmap_write(regmap, base + rptr->cfg->init_tbl[i].reg, + regmap_write(regmap, rptr->cfg->init_tbl[i].reg, rptr->cfg->init_tbl[i].value); =20 /* Override registers from devicetree values */ if (!of_property_read_u8(np, "qcom,tune-usb2-preem", &val)) - regmap_write(regmap, base + EUSB2_TUNE_USB2_PREEM, val); + regmap_write(regmap, EUSB2_TUNE_USB2_PREEM, val); =20 if (!of_property_read_u8(np, "qcom,tune-usb2-disc-thres", &val)) - regmap_write(regmap, base + EUSB2_TUNE_HSDISC, val); + regmap_write(regmap, EUSB2_TUNE_HSDISC, val); =20 if (!of_property_read_u8(np, "qcom,tune-usb2-amplitude", &val)) - regmap_write(regmap, base + EUSB2_TUNE_IUSB2, val); + regmap_write(regmap, EUSB2_TUNE_IUSB2, val); =20 if (!of_property_read_u8(np, "qcom,tune-res-fsdif", &val)) - regmap_write(regmap, base + EUSB2_TUNE_RES_FSDIF, val); + regmap_write(regmap, EUSB2_TUNE_RES_FSDIF, val); =20 /* Wait for status OK */ - ret =3D regmap_read_poll_timeout(regmap, base + EUSB2_RPTR_STATUS, poll_v= al, + ret =3D regmap_read_poll_timeout(regmap, EUSB2_RPTR_STATUS, poll_val, poll_val & RPTR_OK, 10, 5); if (ret) dev_err(rptr->dev, "initialization timed-out\n"); @@ -161,7 +160,6 @@ static int eusb2_repeater_set_mode(struct phy *phy, { struct eusb2_repeater *rptr =3D phy_get_drvdata(phy); struct regmap *regmap =3D rptr->regmap; - u32 base =3D rptr->base; =20 switch (mode) { case PHY_MODE_USB_HOST: @@ -170,8 +168,8 @@ static int eusb2_repeater_set_mode(struct phy *phy, * per eUSB 1.2 Spec. Below implement software workaround until * PHY and controller is fixing seen observation. */ - regmap_write(regmap, base + EUSB2_FORCE_EN_5, F_CLK_19P2M_EN); - regmap_write(regmap, base + EUSB2_FORCE_VAL_5, V_CLK_19P2M_EN); + regmap_write(regmap, EUSB2_FORCE_EN_5, F_CLK_19P2M_EN); + regmap_write(regmap, EUSB2_FORCE_VAL_5, V_CLK_19P2M_EN); break; case PHY_MODE_USB_DEVICE: /* @@ -180,8 +178,8 @@ static int eusb2_repeater_set_mode(struct phy *phy, * repeater doesn't clear previous value due to shared * regulators (say host <-> device mode switch). */ - regmap_write(regmap, base + EUSB2_FORCE_EN_5, 0); - regmap_write(regmap, base + EUSB2_FORCE_VAL_5, 0); + regmap_write(regmap, EUSB2_FORCE_EN_5, 0); + regmap_write(regmap, EUSB2_FORCE_VAL_5, 0); break; default: return -EINVAL; @@ -206,13 +204,23 @@ static const struct phy_ops eusb2_repeater_ops =3D { =20 static int eusb2_repeater_probe(struct platform_device *pdev) { + struct regmap_config eusb2_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D 0x100, + .fast_io =3D true, + }; + struct spmi_device *sparent; struct eusb2_repeater *rptr; + struct spmi_subdevice *sub_sdev; struct device *dev =3D &pdev->dev; struct phy_provider *phy_provider; struct device_node *np =3D dev->of_node; - u32 res; int ret; =20 + if (!dev->parent) + return -ENODEV; + rptr =3D devm_kzalloc(dev, sizeof(*rptr), GFP_KERNEL); if (!rptr) return -ENOMEM; @@ -224,15 +232,21 @@ static int eusb2_repeater_probe(struct platform_devic= e *pdev) if (!rptr->cfg) return -EINVAL; =20 - rptr->regmap =3D dev_get_regmap(dev->parent, NULL); - if (!rptr->regmap) + sparent =3D to_spmi_device(dev->parent); + if (!sparent) return -ENODEV; =20 - ret =3D of_property_read_u32(np, "reg", &res); + sub_sdev =3D devm_spmi_subdevice_alloc_and_add(dev, sparent); + if (IS_ERR(sub_sdev)) + return PTR_ERR(sub_sdev); + + ret =3D of_property_read_u32(np, "reg", &eusb2_regmap_config.reg_base); if (ret < 0) return ret; =20 - rptr->base =3D res; + rptr->regmap =3D devm_regmap_init_spmi_ext(&sub_sdev->sdev, &eusb2_regmap= _config); + if (IS_ERR(rptr->regmap)) + return -ENODEV; =20 ret =3D eusb2_repeater_init_vregs(rptr); if (ret < 0) { @@ -295,3 +309,4 @@ module_platform_driver(eusb2_repeater_driver); =20 MODULE_DESCRIPTION("Qualcomm PMIC eUSB2 Repeater driver"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("SPMI"); --=20 2.51.0 From nobody Mon Feb 9 14:34:36 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBBA3334361; Thu, 16 Oct 2025 10:44:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760611465; cv=none; b=BS6GJh/j7ienBfAZF/VEq7vwxcctxKTtZ4yHFRkHa1oRzAAQ48RYhrfd/SVlRTvL6P9nhxHdGVoBEwNmnsuICF671NgxRRJwrgA1VCIrBWhPSb4O7q0cI/pjQ2QY1//dzcw0LssISvVSwYb7p1zVVrXQNuC4cH7d0TUC2Ad+ToA= ARC-Message-Signature: i=1; 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charset="utf-8" Some Qualcomm PMICs integrate a charger for coincells, usually powering an RTC when external (or main battery) power is missing. Instead of using the parent SPMI device (the main PMIC) as a kind of syscon in this driver, register a new SPMI sub-device and initialize its own regmap with this sub-device's specific base address, retrieved from the devicetree. This allows to stop manually adding the register base address to every R/W call in this driver, as this can be, and is now, handled by the regmap API instead. Acked-by: Greg Kroah-Hartman Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: AngeloGioacchino Del Regno --- drivers/misc/Kconfig | 2 ++ drivers/misc/qcom-coincell.c | 38 +++++++++++++++++++++++++----------- 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index b9c11f67315f..f4c5e67192fb 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -291,6 +291,8 @@ config HP_ILO config QCOM_COINCELL tristate "Qualcomm coincell charger support" depends on MFD_SPMI_PMIC || COMPILE_TEST + depends on SPMI + select REGMAP_SPMI help This driver supports the coincell block found inside of Qualcomm PMICs. The coincell charger provides a means to diff --git a/drivers/misc/qcom-coincell.c b/drivers/misc/qcom-coincell.c index 3c57f7429147..49e38442b289 100644 --- a/drivers/misc/qcom-coincell.c +++ b/drivers/misc/qcom-coincell.c @@ -9,11 +9,11 @@ #include #include #include +#include =20 struct qcom_coincell { struct device *dev; struct regmap *regmap; - u32 base_addr; }; =20 #define QCOM_COINCELL_REG_RSET 0x44 @@ -35,7 +35,7 @@ static int qcom_coincell_chgr_config(struct qcom_coincell= *chgr, int rset, /* if disabling, just do that and skip other operations */ if (!enable) return regmap_write(chgr->regmap, - chgr->base_addr + QCOM_COINCELL_REG_ENABLE, 0); + QCOM_COINCELL_REG_ENABLE, 0); =20 /* find index for current-limiting resistor */ for (i =3D 0; i < ARRAY_SIZE(qcom_rset_map); i++) @@ -58,7 +58,7 @@ static int qcom_coincell_chgr_config(struct qcom_coincell= *chgr, int rset, } =20 rc =3D regmap_write(chgr->regmap, - chgr->base_addr + QCOM_COINCELL_REG_RSET, i); + QCOM_COINCELL_REG_RSET, i); if (rc) { /* * This is mainly to flag a bad base_addr (reg) from dts. @@ -71,19 +71,28 @@ static int qcom_coincell_chgr_config(struct qcom_coince= ll *chgr, int rset, } =20 rc =3D regmap_write(chgr->regmap, - chgr->base_addr + QCOM_COINCELL_REG_VSET, j); + QCOM_COINCELL_REG_VSET, j); if (rc) return rc; =20 /* set 'enable' register */ return regmap_write(chgr->regmap, - chgr->base_addr + QCOM_COINCELL_REG_ENABLE, + QCOM_COINCELL_REG_ENABLE, QCOM_COINCELL_ENABLE); } =20 static int qcom_coincell_probe(struct platform_device *pdev) { - struct device_node *node =3D pdev->dev.of_node; + struct regmap_config qcom_coincell_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D 0x100, + .fast_io =3D true, + }; + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->of_node; + struct spmi_subdevice *sub_sdev; + struct spmi_device *sparent; struct qcom_coincell chgr; u32 rset =3D 0; u32 vset =3D 0; @@ -92,16 +101,22 @@ static int qcom_coincell_probe(struct platform_device = *pdev) =20 chgr.dev =3D &pdev->dev; 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Thu, 16 Oct 2025 12:44:22 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org, casey.connolly@linaro.org, Jonathan Cameron , Neil Armstrong Subject: [PATCH v6 7/8] iio: adc: qcom-spmi-iadc: Migrate to devm_spmi_subdevice_alloc_and_add() Date: Thu, 16 Oct 2025 12:44:01 +0200 Message-ID: <20251016104402.338246-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251016104402.338246-1-angelogioacchino.delregno@collabora.com> References: <20251016104402.338246-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Qualcomm PMICs integrate an Current ADC device, reachable in a specific address range over SPMI. Instead of using the parent SPMI device (the main PMIC) as a kind of syscon in this driver, register a new SPMI sub-device and initialize its own regmap with this sub-device's specific base address, retrieved from the devicetree. This allows to stop manually adding the register base address to every R/W call in this driver, as this can be, and is now, handled by the regmap API instead. Reviewed-by: Jonathan Cameron Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: AngeloGioacchino Del Regno --- drivers/iio/adc/qcom-spmi-iadc.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-iadc.c b/drivers/iio/adc/qcom-spmi-i= adc.c index b64a8a407168..67096952b229 100644 --- a/drivers/iio/adc/qcom-spmi-iadc.c +++ b/drivers/iio/adc/qcom-spmi-iadc.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 /* IADC register and bit definition */ #define IADC_REVISION2 0x1 @@ -94,7 +95,6 @@ * struct iadc_chip - IADC Current ADC device structure. * @regmap: regmap for register read/write. * @dev: This device pointer. - * @base: base offset for the ADC peripheral. * @rsense: Values of the internal and external sense resister in micro Oh= ms. * @poll_eoc: Poll for end of conversion instead of waiting for IRQ. * @offset: Raw offset values for the internal and external channels. @@ -105,7 +105,6 @@ struct iadc_chip { struct regmap *regmap; struct device *dev; - u16 base; bool poll_eoc; u32 rsense[2]; u16 offset[2]; @@ -119,7 +118,7 @@ static int iadc_read(struct iadc_chip *iadc, u16 offset= , u8 *data) unsigned int val; int ret; =20 - ret =3D regmap_read(iadc->regmap, iadc->base + offset, &val); + ret =3D regmap_read(iadc->regmap, offset, &val); if (ret < 0) return ret; =20 @@ -129,7 +128,7 @@ static int iadc_read(struct iadc_chip *iadc, u16 offset= , u8 *data) =20 static int iadc_write(struct iadc_chip *iadc, u16 offset, u8 data) { - return regmap_write(iadc->regmap, iadc->base + offset, data); + return regmap_write(iadc->regmap, offset, data); } =20 static int iadc_reset(struct iadc_chip *iadc) @@ -270,7 +269,7 @@ static int iadc_poll_wait_eoc(struct iadc_chip *iadc, u= nsigned int interval_us) =20 static int iadc_read_result(struct iadc_chip *iadc, u16 *data) { - return regmap_bulk_read(iadc->regmap, iadc->base + IADC_DATA, data, 2); + return regmap_bulk_read(iadc->regmap, IADC_DATA, data, 2); } =20 static int iadc_do_conversion(struct iadc_chip *iadc, int chan, u16 *data) @@ -483,12 +482,19 @@ static const struct iio_chan_spec iadc_channels[] =3D= { =20 static int iadc_probe(struct platform_device *pdev) { + struct regmap_config iadc_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D 0x100, + .fast_io =3D true, + }; struct device_node *node =3D pdev->dev.of_node; struct device *dev =3D &pdev->dev; + struct spmi_subdevice *sub_sdev; + struct spmi_device *sparent; struct iio_dev *indio_dev; struct iadc_chip *iadc; int ret, irq_eoc; - u32 res; =20 indio_dev =3D devm_iio_device_alloc(dev, sizeof(*iadc)); if (!indio_dev) @@ -497,18 +503,21 @@ static int iadc_probe(struct platform_device *pdev) iadc =3D iio_priv(indio_dev); iadc->dev =3D dev; =20 - iadc->regmap =3D dev_get_regmap(dev->parent, NULL); - if (!iadc->regmap) - return -ENODEV; + sparent =3D to_spmi_device(dev->parent); + sub_sdev =3D devm_spmi_subdevice_alloc_and_add(dev, sparent); + if (IS_ERR(sub_sdev)) + return PTR_ERR(sub_sdev); =20 init_completion(&iadc->complete); mutex_init(&iadc->lock); =20 - ret =3D of_property_read_u32(node, "reg", &res); + ret =3D of_property_read_u32(node, "reg", &iadc_regmap_config.reg_base); if (ret < 0) return -ENODEV; =20 - iadc->base =3D res; + iadc->regmap =3D devm_regmap_init_spmi_ext(&sub_sdev->sdev, &iadc_regmap_= config); + if (IS_ERR(iadc->regmap)) + return PTR_ERR(iadc->regmap); =20 ret =3D iadc_version_check(iadc); if (ret < 0) @@ -584,3 +593,4 @@ MODULE_ALIAS("platform:qcom-spmi-iadc"); MODULE_DESCRIPTION("Qualcomm SPMI PMIC current ADC driver"); MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Ivan T. Ivanov "); +MODULE_IMPORT_NS("SPMI"); --=20 2.51.0 From nobody Mon Feb 9 14:34:36 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13EAA31E115; Thu, 16 Oct 2025 10:44:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760611469; cv=none; b=mRgA62M3e4elZX/eMAX78Wa4e3NjAw/oLkM1ZOx2L1T3tWq/hSIjDLUxCTMHYOspP/aqTLXaGruBBA0SyTYwP+zOqNZw2nYh/XQg4uAsFQ9nqEocVepVcTkjlbCVNLJhAR2zdHnfk8/FreMaxTVKm1LKJucQltofXZdCdW7Cj00= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760611469; c=relaxed/simple; bh=Pd64nNB5Ez9IHOMoFPksTepGl56Y6v+xlVxwhALiKto=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hPrRU+JKEcON3hKvDNk1ESFVNXCRLRlDXbZtPfZo6XpUW2OppdPxqkK/sd97qiLJG5Hb6E5PI3F6KoT9H6GvTCSjgfIm+mfgEMG/pe5vtM5fV9T7hsn+QAms14tvSJMY/MU1h/+/wX+6jMVck/SRns/wF2SUdg9eq1Hw9p5UyEg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=agDNwt51; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="agDNwt51" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1760611464; bh=Pd64nNB5Ez9IHOMoFPksTepGl56Y6v+xlVxwhALiKto=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=agDNwt51rlZUH+1SNzSNg5jsGcVy6Tqsvbmh2nsLeMY1cDkGhkBdaiFTux0GgSIzO 3xS9c+DDf7QJul50tjSR2aE+0WOTNrhb/bRimJ7yLlerx/2z7vFVq5uIcjjONEoJfH ELpwLmMdo2llJncLZzLlrNt1+fRSuWCOfWrG1/c9kCewgl6FdEwn+Cy/lf80Soi6E9 jMcMTCIEvUG3vM4QrK/ODhb5Rdqp/su7aPv4JgHp463viFMvj41i2J/IfAjgsDknFU we78cuje4ZMjovqrkOArUqgdaEfqPAkimuxmD+izhI7CND4cTNwNE+cuW17Eya/hDS mrBCWbKkOn6HA== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5EAD017E1060; Thu, 16 Oct 2025 12:44:23 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org, casey.connolly@linaro.org, Jonathan Cameron , Neil Armstrong Subject: [PATCH v6 8/8] iio: adc: qcom-spmi-iadc: Remove regmap R/W wrapper functions Date: Thu, 16 Oct 2025 12:44:02 +0200 Message-ID: <20251016104402.338246-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251016104402.338246-1-angelogioacchino.delregno@collabora.com> References: <20251016104402.338246-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This driver doesn't need to add any register base address to any regmap call anymore since it was migrated to register as a SPMI subdevice with its own regmap reg_base, which makes the regmap API to automatically add such base address internally. Since the iadc_{read,write,read_result}() functions now only do call regmap_{read,write,bulk_read}() and nothing else, simplify the driver by removing them and by calling regmap APIs directly. Reviewed-by: Jonathan Cameron Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: AngeloGioacchino Del Regno --- drivers/iio/adc/qcom-spmi-iadc.c | 83 ++++++++++++-------------------- 1 file changed, 30 insertions(+), 53 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-iadc.c b/drivers/iio/adc/qcom-spmi-i= adc.c index 67096952b229..7d46ec2d1a30 100644 --- a/drivers/iio/adc/qcom-spmi-iadc.c +++ b/drivers/iio/adc/qcom-spmi-iadc.c @@ -113,77 +113,59 @@ struct iadc_chip { struct completion complete; }; =20 -static int iadc_read(struct iadc_chip *iadc, u16 offset, u8 *data) -{ - unsigned int val; - int ret; - - ret =3D regmap_read(iadc->regmap, offset, &val); - if (ret < 0) - return ret; - - *data =3D val; - return 0; -} - -static int iadc_write(struct iadc_chip *iadc, u16 offset, u8 data) -{ - return regmap_write(iadc->regmap, offset, data); -} - static int iadc_reset(struct iadc_chip *iadc) { - u8 data; + u32 data; int ret; =20 - ret =3D iadc_write(iadc, IADC_SEC_ACCESS, IADC_SEC_ACCESS_DATA); + ret =3D regmap_write(iadc->regmap, IADC_SEC_ACCESS, IADC_SEC_ACCESS_DATA); if (ret < 0) return ret; =20 - ret =3D iadc_read(iadc, IADC_PERH_RESET_CTL3, &data); + ret =3D regmap_read(iadc->regmap, IADC_PERH_RESET_CTL3, &data); if (ret < 0) return ret; =20 - ret =3D iadc_write(iadc, IADC_SEC_ACCESS, IADC_SEC_ACCESS_DATA); + ret =3D regmap_write(iadc->regmap, IADC_SEC_ACCESS, IADC_SEC_ACCESS_DATA); if (ret < 0) return ret; =20 data |=3D IADC_FOLLOW_WARM_RB; =20 - return iadc_write(iadc, IADC_PERH_RESET_CTL3, data); + return regmap_write(iadc->regmap, IADC_PERH_RESET_CTL3, data); } =20 static int iadc_set_state(struct iadc_chip *iadc, bool state) { - return iadc_write(iadc, IADC_EN_CTL1, state ? IADC_EN_CTL1_SET : 0); + return regmap_write(iadc->regmap, IADC_EN_CTL1, state ? IADC_EN_CTL1_SET = : 0); } =20 static void iadc_status_show(struct iadc_chip *iadc) { - u8 mode, sta1, chan, dig, en, req; + u32 mode, sta1, chan, dig, en, req; int ret; =20 - ret =3D iadc_read(iadc, IADC_MODE_CTL, &mode); + ret =3D regmap_read(iadc->regmap, IADC_MODE_CTL, &mode); if (ret < 0) return; =20 - ret =3D iadc_read(iadc, IADC_DIG_PARAM, &dig); + ret =3D regmap_read(iadc->regmap, IADC_DIG_PARAM, &dig); if (ret < 0) return; =20 - ret =3D iadc_read(iadc, IADC_CH_SEL_CTL, &chan); + ret =3D regmap_read(iadc->regmap, IADC_CH_SEL_CTL, &chan); if (ret < 0) return; =20 - ret =3D iadc_read(iadc, IADC_CONV_REQ, &req); + ret =3D regmap_read(iadc->regmap, IADC_CONV_REQ, &req); if (ret < 0) return; =20 - ret =3D iadc_read(iadc, IADC_STATUS1, &sta1); + ret =3D regmap_read(iadc->regmap, IADC_STATUS1, &sta1); if (ret < 0) return; =20 - ret =3D iadc_read(iadc, IADC_EN_CTL1, &en); + ret =3D regmap_read(iadc->regmap, IADC_EN_CTL1, &en); if (ret < 0) return; =20 @@ -199,34 +181,34 @@ static int iadc_configure(struct iadc_chip *iadc, int= channel) =20 /* Mode selection */ mode =3D (IADC_OP_MODE_NORMAL << IADC_OP_MODE_SHIFT) | IADC_TRIM_EN; - ret =3D iadc_write(iadc, IADC_MODE_CTL, mode); + ret =3D regmap_write(iadc->regmap, IADC_MODE_CTL, mode); if (ret < 0) return ret; =20 /* Channel selection */ - ret =3D iadc_write(iadc, IADC_CH_SEL_CTL, channel); + ret =3D regmap_write(iadc->regmap, IADC_CH_SEL_CTL, channel); if (ret < 0) return ret; =20 /* Digital parameter setup */ decim =3D IADC_DEF_DECIMATION << IADC_DIG_DEC_RATIO_SEL_SHIFT; - ret =3D iadc_write(iadc, IADC_DIG_PARAM, decim); + ret =3D regmap_write(iadc->regmap, IADC_DIG_PARAM, decim); if (ret < 0) return ret; =20 /* HW settle time delay */ - ret =3D iadc_write(iadc, IADC_HW_SETTLE_DELAY, IADC_DEF_HW_SETTLE_TIME); + ret =3D regmap_write(iadc->regmap, IADC_HW_SETTLE_DELAY, IADC_DEF_HW_SETT= LE_TIME); if (ret < 0) return ret; =20 - ret =3D iadc_write(iadc, IADC_FAST_AVG_CTL, IADC_DEF_AVG_SAMPLES); + ret =3D regmap_write(iadc->regmap, IADC_FAST_AVG_CTL, IADC_DEF_AVG_SAMPLE= S); if (ret < 0) return ret; =20 if (IADC_DEF_AVG_SAMPLES) - ret =3D iadc_write(iadc, IADC_FAST_AVG_EN, IADC_FAST_AVG_EN_SET); + ret =3D regmap_write(iadc->regmap, IADC_FAST_AVG_EN, IADC_FAST_AVG_EN_SE= T); else - ret =3D iadc_write(iadc, IADC_FAST_AVG_EN, 0); + ret =3D regmap_write(iadc->regmap, IADC_FAST_AVG_EN, 0); =20 if (ret < 0) return ret; @@ -239,19 +221,19 @@ static int iadc_configure(struct iadc_chip *iadc, int= channel) return ret; =20 /* Request conversion */ - return iadc_write(iadc, IADC_CONV_REQ, IADC_CONV_REQ_SET); + return regmap_write(iadc->regmap, IADC_CONV_REQ, IADC_CONV_REQ_SET); } =20 static int iadc_poll_wait_eoc(struct iadc_chip *iadc, unsigned int interva= l_us) { unsigned int count, retry; int ret; - u8 sta1; + u32 sta1; =20 retry =3D interval_us / IADC_CONV_TIME_MIN_US; =20 for (count =3D 0; count < retry; count++) { - ret =3D iadc_read(iadc, IADC_STATUS1, &sta1); + ret =3D regmap_read(iadc->regmap, IADC_STATUS1, &sta1); if (ret < 0) return ret; =20 @@ -267,11 +249,6 @@ static int iadc_poll_wait_eoc(struct iadc_chip *iadc, = unsigned int interval_us) return -ETIMEDOUT; } =20 -static int iadc_read_result(struct iadc_chip *iadc, u16 *data) -{ - return regmap_bulk_read(iadc->regmap, IADC_DATA, data, 2); -} - static int iadc_do_conversion(struct iadc_chip *iadc, int chan, u16 *data) { unsigned int wait; @@ -296,7 +273,7 @@ static int iadc_do_conversion(struct iadc_chip *iadc, i= nt chan, u16 *data) } =20 if (!ret) - ret =3D iadc_read_result(iadc, data); + ret =3D regmap_bulk_read(iadc->regmap, IADC_DATA, data, sizeof(*data)); exit: iadc_set_state(iadc, false); if (ret < 0) @@ -392,10 +369,10 @@ static int iadc_update_offset(struct iadc_chip *iadc) =20 static int iadc_version_check(struct iadc_chip *iadc) { - u8 val; + u32 val; int ret; =20 - ret =3D iadc_read(iadc, IADC_PERPH_TYPE, &val); + ret =3D regmap_read(iadc->regmap, IADC_PERPH_TYPE, &val); if (ret < 0) return ret; =20 @@ -404,7 +381,7 @@ static int iadc_version_check(struct iadc_chip *iadc) return -EINVAL; } =20 - ret =3D iadc_read(iadc, IADC_PERPH_SUBTYPE, &val); + ret =3D regmap_read(iadc->regmap, IADC_PERPH_SUBTYPE, &val); if (ret < 0) return ret; =20 @@ -413,7 +390,7 @@ static int iadc_version_check(struct iadc_chip *iadc) return -EINVAL; } =20 - ret =3D iadc_read(iadc, IADC_REVISION2, &val); + ret =3D regmap_read(iadc->regmap, IADC_REVISION2, &val); if (ret < 0) return ret; =20 @@ -428,7 +405,7 @@ static int iadc_version_check(struct iadc_chip *iadc) static int iadc_rsense_read(struct iadc_chip *iadc, struct device_node *no= de) { int ret, sign, int_sense; - u8 deviation; + u32 deviation; =20 ret =3D of_property_read_u32(node, "qcom,external-resistor-micro-ohms", &iadc->rsense[IADC_EXT_RSENSE]); @@ -440,7 +417,7 @@ static int iadc_rsense_read(struct iadc_chip *iadc, str= uct device_node *node) return -EINVAL; } =20 - ret =3D iadc_read(iadc, IADC_NOMINAL_RSENSE, &deviation); + ret =3D regmap_read(iadc->regmap, IADC_NOMINAL_RSENSE, &deviation); if (ret < 0) return ret; =20 --=20 2.51.0