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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2025 05:28:44.6406 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81fdeda0-46c4-4ad8-f5d7-08de0c74e00a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5775 Content-Type: text/plain; charset="utf-8" Simplify the initialization and cleanup flow for Versal Net DDRMC controllers in the EDAC driver. Key changes include: * Introduced `init_single_versalnet()` for per-controller setup and `init_versalnet()` for looping through NUM_CONTROLLERS. * Added proper rollback logic using `remove_single_versalnet()` when partial initialization fails. * Improved readability and maintainability by reducing duplicated code and consolidating error handling. Signed-off-by: Shubhrajyoti Datta --- drivers/edac/versalnet_edac.c | 158 +++++++++++++++++++--------------- 1 file changed, 87 insertions(+), 71 deletions(-) diff --git a/drivers/edac/versalnet_edac.c b/drivers/edac/versalnet_edac.c index 1ded4c3f0213..fc7e4c43b387 100644 --- a/drivers/edac/versalnet_edac.c +++ b/drivers/edac/versalnet_edac.c @@ -758,92 +758,111 @@ static void versal_edac_release(struct device *dev) kfree(dev); } =20 -static int init_versalnet(struct mc_priv *priv, struct platform_device *pd= ev) +static void remove_single_versalnet(struct mc_priv *priv, int i) +{ + struct mem_ctl_info *mci; + + mci =3D priv->mci[i]; + device_unregister(mci->pdev); + edac_mc_del_mc(mci->pdev); + edac_mc_free(mci); +} + +static int init_single_versalnet(struct mc_priv *priv, struct platform_dev= ice *pdev, int i) { u32 num_chans, rank, dwidth, config; - struct edac_mc_layer layers[2]; struct mem_ctl_info *mci; + struct edac_mc_layer layers[2]; struct device *dev; enum dev_type dt; char *name; - int rc, i; + int rc; =20 - for (i =3D 0; i < NUM_CONTROLLERS; i++) { - config =3D priv->adec[CONF + i * ADEC_NUM]; - num_chans =3D FIELD_GET(MC5_NUM_CHANS_MASK, config); - rank =3D 1 << FIELD_GET(MC5_RANK_MASK, config); - dwidth =3D FIELD_GET(MC5_BUS_WIDTH_MASK, config); - - switch (dwidth) { - case XDDR5_BUS_WIDTH_16: - dt =3D DEV_X16; - break; - case XDDR5_BUS_WIDTH_32: - dt =3D DEV_X32; - break; - case XDDR5_BUS_WIDTH_64: - dt =3D DEV_X64; - break; - default: - dt =3D DEV_UNKNOWN; - } + config =3D priv->adec[CONF + i * ADEC_NUM]; + num_chans =3D FIELD_GET(MC5_NUM_CHANS_MASK, config); + rank =3D 1 << FIELD_GET(MC5_RANK_MASK, config); + dwidth =3D FIELD_GET(MC5_BUS_WIDTH_MASK, config); + + switch (dwidth) { + case XDDR5_BUS_WIDTH_16: + dt =3D DEV_X16; + break; + case XDDR5_BUS_WIDTH_32: + dt =3D DEV_X32; + break; + case XDDR5_BUS_WIDTH_64: + dt =3D DEV_X64; + break; + default: + dt =3D DEV_UNKNOWN; + } =20 - if (dt =3D=3D DEV_UNKNOWN) - continue; + if (dt =3D=3D DEV_UNKNOWN) + return 0; =20 - /* Find the first enabled device and register that one. */ - layers[0].type =3D EDAC_MC_LAYER_CHIP_SELECT; - layers[0].size =3D rank; - layers[0].is_virt_csrow =3D true; - layers[1].type =3D EDAC_MC_LAYER_CHANNEL; - layers[1].size =3D num_chans; - layers[1].is_virt_csrow =3D false; + /* Find the first enabled device and register that one. */ + layers[0].type =3D EDAC_MC_LAYER_CHIP_SELECT; + layers[0].size =3D rank; + layers[0].is_virt_csrow =3D true; + layers[1].type =3D EDAC_MC_LAYER_CHANNEL; + layers[1].size =3D num_chans; + layers[1].is_virt_csrow =3D false; + + rc =3D -ENOMEM; + mci =3D edac_mc_alloc(i, ARRAY_SIZE(layers), layers, + sizeof(struct mc_priv)); + if (!mci) { + edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for MC%d\n", i); + return rc; + } + priv->mci[i] =3D mci; + priv->dwidth =3D dt; + + dev =3D kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return rc; + dev->release =3D versal_edac_release; + name =3D kmalloc(32, GFP_KERNEL); + sprintf(name, "versal-net-ddrmc5-edac-%d", i); + dev->init_name =3D name; + rc =3D device_register(dev); + if (rc) + goto err_mc_free; =20 - rc =3D -ENOMEM; - mci =3D edac_mc_alloc(i, ARRAY_SIZE(layers), layers, - sizeof(struct mc_priv)); - if (!mci) { - edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for MC%d\n", i= ); - goto err_alloc; - } + mci->pdev =3D dev; =20 - priv->mci[i] =3D mci; - priv->dwidth =3D dt; + platform_set_drvdata(pdev, priv); =20 - dev =3D kzalloc(sizeof(*dev), GFP_KERNEL); - dev->release =3D versal_edac_release; - name =3D kmalloc(32, GFP_KERNEL); - sprintf(name, "versal-net-ddrmc5-edac-%d", i); - dev->init_name =3D name; - rc =3D device_register(dev); - if (rc) - goto err_alloc; + mc_init(mci, dev); + rc =3D edac_mc_add_mc(mci); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, "Failed to register MC%d with EDAC core\n= ", i); + goto err_unreg; + } + return 0; +err_unreg: + device_unregister(mci->pdev); +err_mc_free: + edac_mc_free(mci); + return rc; +} =20 - mci->pdev =3D dev; =20 - platform_set_drvdata(pdev, priv); +static int init_versalnet(struct mc_priv *priv, struct platform_device *pd= ev) +{ + int rc, i; =20 - mc_init(mci, dev); - rc =3D edac_mc_add_mc(mci); - if (rc) { - edac_printk(KERN_ERR, EDAC_MC, "Failed to register MC%d with EDAC core\= n", i); - goto err_alloc; - } + for (i =3D 0; i < NUM_CONTROLLERS; i++) { + rc =3D init_single_versalnet(priv, pdev, i); + if (rc) + goto err_rm_versalnet; } return 0; =20 -err_alloc: - while (i--) { - mci =3D priv->mci[i]; - if (!mci) - continue; - - if (mci->pdev) { - device_unregister(mci->pdev); - edac_mc_del_mc(mci->pdev); - } - - edac_mc_free(mci); +err_rm_versalnet: + while (i) { + i--; + remove_single_versalnet(priv, i); } =20 return rc; @@ -857,9 +876,6 @@ static void remove_versalnet(struct mc_priv *priv) for (i =3D 0; i < NUM_CONTROLLERS; i++) { device_unregister(priv->mci[i]->pdev); mci =3D edac_mc_del_mc(priv->mci[i]->pdev); - if (!mci) - return; - edac_mc_free(mci); } } --=20 2.34.1