From nobody Mon Feb 9 19:43:59 2026 Received: from mo-csw-fb.securemx.jp (mo-csw-fb1122.securemx.jp [210.130.202.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 438D2CA4E; Thu, 16 Oct 2025 03:31:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.130.202.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760585480; cv=none; b=tG2cw47paqM6XMVID4zmMYZz76V5zJ3Oo1sn0mAgAAtRqMcw+pnV64G2ufnLNBiXAgYN/HqyVdm5uBe1S1xlruV/u2m6PtdGci1PeRDNtXnMRQQZfUji8XUNqI7L1hS7B3iUcjo6zGLlKwIN6g+PK3Zbex2vr3qswY1BZlCAnyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760585480; c=relaxed/simple; bh=DhquJXfwIJXPb+27jcxzHtwxsqB1wZz4m4WsYkpC20g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fqJV8mttfG6WIerAsFHp9ZBhApNu+HX1mpUGmuT2OpRuG+1diOMslHaDT9fA0+uez3ExXIzE76ZcpbX0ZYsaOdXQFEh4auuepoRm+XeVrMoQE/PRbNPQDuV/VTN1pLPgp+sqTo69FJ7VMj+q5iR/x3qnGNHqkvx4PMtUlWlfmFA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=toshiba.co.jp; spf=pass smtp.mailfrom=toshiba.co.jp; dkim=pass (2048-bit key) header.d=toshiba.co.jp header.i=yuji2.ishikawa@toshiba.co.jp header.b=XMoeKsum; arc=none smtp.client-ip=210.130.202.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=toshiba.co.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=toshiba.co.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=toshiba.co.jp header.i=yuji2.ishikawa@toshiba.co.jp header.b="XMoeKsum" Received: by mo-csw-fb.securemx.jp (mx-mo-csw-fb1122) id 59G1dwdV748855; Thu, 16 Oct 2025 10:39:58 +0900 DKIM-Signature: v=1;a=rsa-sha256;c=relaxed/simple;d=toshiba.co.jp;h=From:To:Cc :Subject:Date:Message-Id:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding;i=yuji2.ishikawa@toshiba.co.jp;s=key1.smx;t= 1760578760;x=1761788360;bh=DhquJXfwIJXPb+27jcxzHtwxsqB1wZz4m4WsYkpC20g=;b=XMo eKsumOG8enFCBctqTXu2QRBPHmDGQmybRSaFJvokxDiu9sGjb8qy56IsLhAf3Fma37KP0iXVTOhy7 G5BR4rfkxQgqlvhRZGG726lq03bv/eHbMBMRYop5aWU2rI7MkLj9BtvzZN35Wj9MsH7jP+v05kA0k TMjTPBeh5oj75eDHGmKfHFRzeNm47h60AyAwVwYOAPdqo1IpIeXyFonz4FcVc63ONvkX5pbzAr4bE siBKAcFEL2ggJYB7oEf4JY96QaK1ihvlsf32fpYLxxOcm5/+Y8365ADj2Om3RZmyJLDumWNIFSnXF QIdM/EitIuftKR5/CLlOIXxCLABYGTw==; Received: by mo-csw.securemx.jp (mx-mo-csw1120) id 59G1dJZl409905; Thu, 16 Oct 2025 10:39:19 +0900 X-Iguazu-Qid: 2rWhejjBIYgAXkrEwe X-Iguazu-QSIG: v=2; s=0; t=1760578759; q=2rWhejjBIYgAXkrEwe; m=TjeFf1PYIWwR61zihda6OanuCyy7Qx1w4c7qBLq7BQY= Received: from imx2-a.toshiba.co.jp (imx2-a.toshiba.co.jp [106.186.93.35]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) id 4cn9bp1qzYz4vyq; Thu, 16 Oct 2025 10:39:18 +0900 (JST) X-SA-MID: 53068310 From: Yuji Ishikawa To: Michael Turquette , Stephen Boyd , Nobuhiro Iwamatsu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Yuji Ishikawa Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: clock: Update identifiers for VIIF on Toshiba Visconti TMPV770x SoC Date: Thu, 16 Oct 2025 10:33:27 +0900 X-TSB-HOP2: ON Message-Id: <20251016013328.303611-2-yuji2.ishikawa@toshiba.co.jp> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251016013328.303611-1-yuji2.ishikawa@toshiba.co.jp> References: <20251016013328.303611-1-yuji2.ishikawa@toshiba.co.jp> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update identifiers for the clocks and the resets of Video Input Interface in order to reflect the actual architecture of TMPV770x SoC. Signed-off-by: Yuji Ishikawa --- include/dt-bindings/clock/toshiba,tmpv770x.h | 33 +++++++++++++------- include/dt-bindings/reset/toshiba,tmpv770x.h | 10 +++++- 2 files changed, 31 insertions(+), 12 deletions(-) diff --git a/include/dt-bindings/clock/toshiba,tmpv770x.h b/include/dt-bind= ings/clock/toshiba,tmpv770x.h index 5fce713001..2dbd5885c0 100644 --- a/include/dt-bindings/clock/toshiba,tmpv770x.h +++ b/include/dt-bindings/clock/toshiba,tmpv770x.h @@ -94,10 +94,10 @@ #define TMPV770X_CLK_DSP2_PBCLK 77 #define TMPV770X_CLK_DSP3_PBCLK 78 #define TMPV770X_CLK_DSVIIF0_APBCLK 79 -#define TMPV770X_CLK_VIIF0_APBCLK 80 -#define TMPV770X_CLK_VIIF0_CFGCLK 81 -#define TMPV770X_CLK_VIIF1_APBCLK 82 -#define TMPV770X_CLK_VIIF1_CFGCLK 83 +#define TMPV770X_CLK_VIIFBS0_APB 80 +#define TMPV770X_CLK_VIIFBS0_CFG 81 +#define TMPV770X_CLK_VIIFBS1_APB 82 +#define TMPV770X_CLK_VIIFBS1_CFG 83 #define TMPV770X_CLK_VIIF2_APBCLK 84 #define TMPV770X_CLK_VIIF2_CFGCLK 85 #define TMPV770X_CLK_VIIF3_APBCLK 86 @@ -121,11 +121,11 @@ #define TMPV770X_CLK_PYRAMID 104 #define TMPV770X_CLK_HWA2_ASYNC 105 #define TMPV770X_CLK_DSP0 106 -#define TMPV770X_CLK_VIIFBS0 107 -#define TMPV770X_CLK_VIIFBS0_L2ISP 108 -#define TMPV770X_CLK_VIIFBS0_L1ISP 109 -#define TMPV770X_CLK_VIIFBS0_PROC 110 -#define TMPV770X_CLK_VIIFBS1 111 +#define TMPV770X_CLK_VIIFBS0_PROC 107 +#define TMPV770X_CLK_VIIF0_L2ISP 108 +#define TMPV770X_CLK_VIIF0_L1ISP 109 +#define TMPV770X_CLK_VIIF0_PROC 110 +#define TMPV770X_CLK_VIIFBS1_PROC 111 #define TMPV770X_CLK_VIIFBS2 112 #define TMPV770X_CLK_VIIFOP_MBUS 113 #define TMPV770X_CLK_VIIFOP0_PROC 114 @@ -141,7 +141,10 @@ #define TMPV770X_CLK_PIREFCLK 124 #define TMPV770X_CLK_SBUS 125 #define TMPV770X_CLK_BUSLCK 126 -#define TMPV770X_NR_CLK 127 +#define TMPV770X_CLK_VIIF1_L2ISP 127 +#define TMPV770X_CLK_VIIF1_L1ISP 128 +#define TMPV770X_CLK_VIIF1_PROC 129 +#define TMPV770X_NR_CLK 130 =20 /* Reset */ #define TMPV770X_RESET_PIETHER_2P5M 0 @@ -176,6 +179,14 @@ #define TMPV770X_RESET_PIPCMIF 29 #define TMPV770X_RESET_PICKMON 30 #define TMPV770X_RESET_SBUSCLK 31 -#define TMPV770X_NR_RESET 32 +#define TMPV770X_RESET_VIIFBS0 32 +#define TMPV770X_RESET_VIIFBS0_APB 33 +#define TMPV770X_RESET_VIIFBS0_L2ISP 34 +#define TMPV770X_RESET_VIIFBS0_L1ISP 35 +#define TMPV770X_RESET_VIIFBS1 36 +#define TMPV770X_RESET_VIIFBS1_APB 37 +#define TMPV770X_RESET_VIIFBS1_L2ISP 38 +#define TMPV770X_RESET_VIIFBS1_L1ISP 39 +#define TMPV770X_NR_RESET 40 =20 #endif /*_DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_ */ diff --git a/include/dt-bindings/reset/toshiba,tmpv770x.h b/include/dt-bind= ings/reset/toshiba,tmpv770x.h index c1007acb19..d711006d6b 100644 --- a/include/dt-bindings/reset/toshiba,tmpv770x.h +++ b/include/dt-bindings/reset/toshiba,tmpv770x.h @@ -36,6 +36,14 @@ #define TMPV770X_RESET_PIPCMIF 29 #define TMPV770X_RESET_PICKMON 30 #define TMPV770X_RESET_SBUSCLK 31 -#define TMPV770X_NR_RESET 32 +#define TMPV770X_RESET_VIIFBS0 32 +#define TMPV770X_RESET_VIIFBS0_APB 33 +#define TMPV770X_RESET_VIIFBS0_L2ISP 34 +#define TMPV770X_RESET_VIIFBS0_L1ISP 35 +#define TMPV770X_RESET_VIIFBS1 36 +#define TMPV770X_RESET_VIIFBS1_APB 37 +#define TMPV770X_RESET_VIIFBS1_L2ISP 38 +#define TMPV770X_RESET_VIIFBS1_L1ISP 39 +#define TMPV770X_NR_RESET 40 =20 #endif /*_DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_ */ --=20 2.43.0 From nobody Mon Feb 9 19:43:59 2026 Received: from mo-csw-fb.securemx.jp (mo-csw-fb1801.securemx.jp [210.130.202.160]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3AE51DDF7; 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charset="utf-8" Add the control sequence of register bits to handle the clocks and the resets of Video Input Interface. Signed-off-by: Yuji Ishikawa --- drivers/clk/visconti/clkc-tmpv770x.c | 71 ++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/clk/visconti/clkc-tmpv770x.c b/drivers/clk/visconti/cl= kc-tmpv770x.c index 6c753b2cb5..26cdfa565e 100644 --- a/drivers/clk/visconti/clkc-tmpv770x.c +++ b/drivers/clk/visconti/clkc-tmpv770x.c @@ -28,6 +28,10 @@ static const struct clk_parent_data pietherplls_parent_d= ata[] =3D { { .fw_name =3D "pietherpll", .name =3D "pietherpll", }, }; =20 +static const struct clk_parent_data pidnnplls_parent_data[] =3D { + { .fw_name =3D "pidnnpll", .name =3D "pidnnpll", }, +}; + static const struct visconti_fixed_clk fixed_clk_tables[] =3D { /* PLL1 */ /* PICMPT0/1, PITSC, PIUWDT, PISWDT, PISBUS, PIPMU, PIGPMU, PITMU */ @@ -64,6 +68,41 @@ static const struct visconti_clk_gate_table pietherpll_c= lk_gate_tables[] =3D { TMPV770X_RESET_PIETHER_125M, }, }; =20 +static const struct visconti_clk_gate_table pidnnpll_clk_gate_tables[] =3D= { + { TMPV770X_CLK_VIIFBS0_PROC, "viif0bsproc", + pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), + 0, 0x58, 0x158, 1, 1, + NO_RESET, }, + { TMPV770X_CLK_VIIF0_PROC, "viif0proc", + pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), + 0, 0x58, 0x158, 18, 1, + NO_RESET, }, + { TMPV770X_CLK_VIIF0_L1ISP, "viif0l1isp", + pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), + 0, 0x58, 0x158, 17, 1, + NO_RESET, }, + { TMPV770X_CLK_VIIF0_L2ISP, "viif0l2isp", + pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), + 0, 0x58, 0x158, 16, 1, + NO_RESET, }, + { TMPV770X_CLK_VIIFBS1_PROC, "viif1bsproc", + pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), + 0, 0x58, 0x158, 5, 1, + NO_RESET, }, + { TMPV770X_CLK_VIIF1_PROC, "viif1proc", + pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), + 0, 0x58, 0x158, 22, 1, + NO_RESET, }, + { TMPV770X_CLK_VIIF1_L1ISP, "viif1l1isp", + pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), + 0, 0x58, 0x158, 21, 1, + NO_RESET, }, + { TMPV770X_CLK_VIIF1_L2ISP, "viif1l2isp", + pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), + 0, 0x58, 0x158, 20, 1, + NO_RESET, }, +}; + static const struct visconti_clk_gate_table clk_gate_tables[] =3D { { TMPV770X_CLK_HOX, "hox", clks_parent_data, ARRAY_SIZE(clks_parent_data), @@ -185,6 +224,22 @@ static const struct visconti_clk_gate_table clk_gate_t= ables[] =3D { clks_parent_data, ARRAY_SIZE(clks_parent_data), 0, 0x14, 0x114, 0, 4, TMPV770X_RESET_SBUSCLK, }, + { TMPV770X_CLK_VIIFBS0_CFG, "csi2rx0cfg", + clks_parent_data, ARRAY_SIZE(clks_parent_data), + 0, 0x58, 0x158, 0, 24, + NO_RESET, }, + { TMPV770X_CLK_VIIFBS0_APB, "csi2rx0apb", + clks_parent_data, ARRAY_SIZE(clks_parent_data), + 0, 0x58, 0x158, 2, 4, + NO_RESET, }, + { TMPV770X_CLK_VIIFBS1_CFG, "csi2rx1cfg", + clks_parent_data, ARRAY_SIZE(clks_parent_data), + 0, 0x58, 0x158, 4, 24, + NO_RESET, }, + { TMPV770X_CLK_VIIFBS1_APB, "csi2rx1apb", + clks_parent_data, ARRAY_SIZE(clks_parent_data), + 0, 0x58, 0x158, 6, 4, + NO_RESET, }, }; =20 static const struct visconti_reset_data clk_reset_data[] =3D { @@ -220,6 +275,14 @@ static const struct visconti_reset_data clk_reset_data= [] =3D { [TMPV770X_RESET_PIPCMIF] =3D { 0x464, 0x564, 0, }, [TMPV770X_RESET_PICKMON] =3D { 0x410, 0x510, 8, }, [TMPV770X_RESET_SBUSCLK] =3D { 0x414, 0x514, 0, }, + [TMPV770X_RESET_VIIFBS0] =3D { 0x458, 0x558, 0, }, + [TMPV770X_RESET_VIIFBS0_APB] =3D { 0x458, 0x558, 1, }, + [TMPV770X_RESET_VIIFBS0_L2ISP] =3D { 0x458, 0x558, 16, }, + [TMPV770X_RESET_VIIFBS0_L1ISP] =3D { 0x458, 0x558, 17, }, + [TMPV770X_RESET_VIIFBS1] =3D { 0x458, 0x558, 4, }, + [TMPV770X_RESET_VIIFBS1_APB] =3D { 0x458, 0x558, 5, }, + [TMPV770X_RESET_VIIFBS1_L2ISP] =3D { 0x458, 0x558, 20, }, + [TMPV770X_RESET_VIIFBS1_L1ISP] =3D { 0x458, 0x558, 21, }, }; =20 static int visconti_clk_probe(struct platform_device *pdev) @@ -272,6 +335,14 @@ static int visconti_clk_probe(struct platform_device *= pdev) return ret; } =20 + ret =3D visconti_clk_register_gates(ctx, pidnnpll_clk_gate_tables, + ARRAY_SIZE(pidnnpll_clk_gate_tables), + clk_reset_data, &tmpv770x_clk_lock); + if (ret) { + dev_err(dev, "Failed to register pidnnpll clock gate: %d\n", ret); + return ret; + } + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &ctx->clk_data); } =20 --=20 2.43.0