From nobody Mon Feb 9 08:29:36 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FF04328620; Thu, 16 Oct 2025 10:08:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760609338; cv=none; b=B2TbM7dNcDY8LrZiBZF+H9Jh8g4sn37LBAzrbredNUeVX7gsTfxncwr+MMuuSqC+9g5Nu/UhNbdPDPZUD2r7QMGWiEZ69DsZgSqDaQti63JOtYzzBzgOKwFrJ8sUuKsaE5qOhl8896VWSetHwNDLbFrGBv30PH7EM9EJ536Nh+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760609338; c=relaxed/simple; bh=TeAojYi5K2VePl3l0wjWKntYVL0CacFDEADdqE/Cfz8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FuH7lzVX23mGcK2qPGYqwAYV6isG8sRfSL6aed95v+aw8JE75iclV49xZAwsVEo8wJ5Yae/CijET8tOvqbelpelX9Lo518cZGFR4If82AspwNonYCWbIUqU+70mJnQ0gC6y+iGGb9T8KBGJkqT0qiZqTW0UhOuri0KojW+M90Kk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=DWSfiQqk; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="DWSfiQqk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1760609334; bh=TeAojYi5K2VePl3l0wjWKntYVL0CacFDEADdqE/Cfz8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=DWSfiQqkwFHirM3/s+cNrgKb2sL7dVd97npEDMMFAlGZ0lFeG+KpeVhSo97eSM0CR cPZvM69V84mvsqcjNMFy0H82N7PtvAIS/CyYgkjTU2SWf6PiewV13DIhPLIpJoiqnw 1eHpN7GsCX+QBsWLevq3d3/rkahzdjBdFz84p3EwnRZb3qY0V9JWLT5z5dKaxuPxhg yhE7MyRUv9PEUttQkdsRwFXO4hGzhgKpxRjMB4lRG7upfS7+np3X+hwmS2r1EkcCku ZZjBBCX+P+iwyedjYmmBZgBo+uT5Yai8L1LRz0fmrsoH2dv8oEVPAwC1PNKakamzho 8KhNNPcCeEQbA== Received: from beast.luon.net (simons.connected.by.freedominter.net [45.83.240.172]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sjoerd) by bali.collaboradmins.com (Postfix) with ESMTPSA id 71DAF17E1340; Thu, 16 Oct 2025 12:08:54 +0200 (CEST) Received: by beast.luon.net (Postfix, from userid 1000) id B0DE310C9C790; Thu, 16 Oct 2025 12:08:53 +0200 (CEST) From: Sjoerd Simons Date: Thu, 16 Oct 2025 12:08:44 +0200 Subject: [PATCH 08/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable PCIe and USB Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251016-openwrt-one-network-v1-8-de259719b6f2@collabora.com> References: <20251016-openwrt-one-network-v1-0-de259719b6f2@collabora.com> In-Reply-To: <20251016-openwrt-one-network-v1-0-de259719b6f2@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Lee Jones , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Lorenzo Bianconi , Felix Fietkau Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, netdev@vger.kernel.org, Daniel Golle , Bryan Hinton , Sjoerd Simons X-Mailer: b4 0.14.3 Enable the PCIe controller and USB3 XHCI host on the OpenWrt One board. The USB controller is configured for USB 2.0 only mode, as the shared USB3/PCIe PHY is dedicated to PCIe functionality on this board. Signed-off-by: Sjoerd Simons --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 43 ++++++++++++++++++= ++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/ar= m64/boot/dts/mediatek/mt7981b-openwrt-one.dts index f836059d7f475..b6ca628ee72fd 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -20,9 +20,40 @@ memory@40000000 { reg =3D <0 0x40000000 0 0x40000000>; device_type =3D "memory"; }; + + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-3.3V"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-5V"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_pins>; + status =3D "okay"; }; =20 &pio { + pcie_pins: pcie-pins { + mux { + function =3D "pcie"; + groups =3D "pcie_pereset"; + }; + }; + uart0_pins: uart0-pins { mux { function =3D "uart"; @@ -36,3 +67,15 @@ &uart0 { pinctrl-0 =3D <&uart0_pins>; status =3D "okay"; }; + +&usb_phy { + status =3D "okay"; +}; + +&xhci { + phys =3D <&u2port0 PHY_TYPE_USB2>; + vusb33-supply =3D <®_3p3v>; + vbus-supply =3D <®_5v>; + mediatek,u3p-dis-msk =3D <0x01>; + status =3D "okay"; +}; --=20 2.51.0