From nobody Mon Feb 9 07:54:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57B5D320CB5; Thu, 16 Oct 2025 10:09:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760609343; cv=none; b=eGOU4G14HZEo9tBwCH6VXBNfARL/5cmHnRXS64LA/skXOssoFEqWPBfttSSo6CHQOCflAj0yZXPJy+tBYwLm3CK46aMMtuZVnqVAick7uxZi7YVBpf6tRiqh7EjFcL30zFbIv+8A8b34vD0e9B0cBL/higLPIfZjqKjdUGJcm4I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760609343; c=relaxed/simple; bh=pdbwHWIQwtrGkmCtFIObJnrZIT84eVm6CBli2NG8zvo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DmlquKZQQDFhMcYjaAkInAtq06dCAD27dHOesiL5Ahk10YxXJVJRNDcIq2Y6M6HYLplx0blI21BVfLbEsA3Eb03G5bEs7yCYTKSHP8/0HBsa/+21bVaF8otHostxhrSuUvnsjuR8LH40Jfwqu/zU6dazvkkugTnTqJXZjXGkUtw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=dMVWYPcr; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="dMVWYPcr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1760609335; bh=pdbwHWIQwtrGkmCtFIObJnrZIT84eVm6CBli2NG8zvo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dMVWYPcrMG4noy3jxMq2ohm1NyJMI2Bh6/fOTVt7tqpnMKrHH69ebGkA8fEOV+Ts9 NebQazi9nU7MngWfE10UjftSFO/B098G3b+/fEMsEFwyETWrnBUJ/otZ3FMlLnBaEr FvzMEtM6DXwHGmyHrqKhQUkvQCRfU+oRj59R+fv60Gcz9SSiJJB8h+yLP1OMmGdS5g QX/fbbmUD9xOp6IQKYPLE8GHgdEaMb+Ud0XqF2U5ROqbhn1XM0qUa9Ch1xBPmZhEeq Z3id5KEhMtYG4eK8S+zn0wnVukn3frRlK6actndGhC3EimAUhDkkB5viJIbEEd/kh+ Qcd0bxM7PiFBA== Received: from beast.luon.net (unknown [IPv6:2a10:3781:2531::8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sjoerd) by bali.collaboradmins.com (Postfix) with ESMTPSA id 3A31D17E153A; Thu, 16 Oct 2025 12:08:55 +0200 (CEST) Received: by beast.luon.net (Postfix, from userid 1000) id BB74610C9C794; Thu, 16 Oct 2025 12:08:53 +0200 (CEST) From: Sjoerd Simons Date: Thu, 16 Oct 2025 12:08:46 +0200 Subject: [PATCH 10/15] arm64: dts: mediatek: mt7981b: Add Ethernet and WiFi offload support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251016-openwrt-one-network-v1-10-de259719b6f2@collabora.com> References: <20251016-openwrt-one-network-v1-0-de259719b6f2@collabora.com> In-Reply-To: <20251016-openwrt-one-network-v1-0-de259719b6f2@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Lee Jones , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Lorenzo Bianconi , Felix Fietkau Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, netdev@vger.kernel.org, Daniel Golle , Bryan Hinton , Sjoerd Simons X-Mailer: b4 0.14.3 Add device tree nodes for the Ethernet subsystem on MT7981B SoC, including: - Ethernet MAC controller with dual GMAC support - Wireless Ethernet Dispatch (WED) - SGMII PHY controllers for high-speed Ethernet interfaces - Reserved memory regions for WiFi offload processor Signed-off-by: Sjoerd Simons --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 133 ++++++++++++++++++++++++++= ++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7981b.dtsi index 13950fe6e8766..c85fa0ddf2da8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -2,6 +2,7 @@ =20 #include #include +#include #include #include =20 @@ -47,11 +48,36 @@ reserved-memory { #size-cells =3D <2>; ranges; =20 + wo_boot: wo-boot@15194000 { + reg =3D <0 0x15194000 0 0x1000>; + no-map; + }; + + wo_ilm0: wo-ilm@151e0000 { + reg =3D <0 0x151e0000 0 0x8000>; + no-map; + }; + + wo_dlm0: wo-dlm@151e8000 { + reg =3D <0 0x151e8000 0 0x2000>; + no-map; + }; + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ secmon_reserved: secmon@43000000 { reg =3D <0 0x43000000 0 0x30000>; no-map; }; + + wo_emi0: wo-emi@47d80000 { + reg =3D <0 0x47d80000 0 0x40000>; + no-map; + }; + + wo_data: wo-data@47dc0000 { + reg =3D <0 0x47dc0000 0 0x240000>; + no-map; + }; }; =20 soc { @@ -107,6 +133,18 @@ pwm: pwm@10048000 { #pwm-cells =3D <2>; }; =20 + sgmiisys0: syscon@10060000 { + compatible =3D "mediatek,mt7981-sgmiisys_0", "syscon"; + reg =3D <0 0x10060000 0 0x1000>; + #clock-cells =3D <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible =3D "mediatek,mt7981-sgmiisys_1", "syscon"; + reg =3D <0 0x10070000 0 0x1000>; + #clock-cells =3D <1>; + }; + uart0: serial@11002000 { compatible =3D "mediatek,mt7981-uart", "mediatek,mt6577-uart"; reg =3D <0 0x11002000 0 0x100>; @@ -338,6 +376,10 @@ soc-uuid@140 { thermal_calibration: thermal-calib@274 { reg =3D <0x274 0xc>; }; + + phy_calibration: phy-calib@8dc { + reg =3D <0x8dc 0x10>; + }; }; =20 ethsys: clock-controller@15000000 { @@ -347,6 +389,97 @@ ethsys: clock-controller@15000000 { #reset-cells =3D <1>; }; =20 + wed: wed@15010000 { + compatible =3D "mediatek,mt7981-wed", + "syscon"; + reg =3D <0 0x15010000 0 0x1000>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + memory-region =3D <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, + <&wo_data>, <&wo_boot>; + memory-region-names =3D "wo-emi", "wo-ilm", "wo-dlm", + "wo-data", "wo-boot"; + mediatek,wo-ccif =3D <&wo_ccif0>; + }; + + eth: ethernet@15100000 { + compatible =3D "mediatek,mt7981-eth"; + reg =3D <0 0x15100000 0 0x40000>; + assigned-clocks =3D <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_CB_NET2_800M>, + <&topckgen CLK_TOP_CB_SGM_325M>; + clocks =3D <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&topckgen CLK_TOP_SGM_REG>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>, + <&sgmiisys0 CLK_SGM0_CK0_EN>, + <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, + <&sgmiisys1 CLK_SGM1_TX_EN>, + <&sgmiisys1 CLK_SGM1_RX_EN>, + <&sgmiisys1 CLK_SGM1_CK1_EN>, + <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names =3D "fe", "gp2", "gp1", "wocpu0", + "sgmii_ck", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "netsys0", "netsys1"; + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "fe0", "fe1", "fe2", "fe3", "pdma0", + "pdma1", "pdma2", "pdma3"; + sram =3D <ð_sram>; + #address-cells =3D <1>; + #size-cells =3D <0>; + mediatek,ethsys =3D <ðsys>; + mediatek,sgmiisys =3D <&sgmiisys0>, <&sgmiisys1>; + mediatek,infracfg =3D <&topmisc>; + mediatek,wed =3D <&wed>; + status =3D "disabled"; + + mdio_bus: mdio-bus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + int_gbe_phy: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + phy-mode =3D "gmii"; + phy-is-integrated; + nvmem-cells =3D <&phy_calibration>; + nvmem-cell-names =3D "phy-cal-data"; + }; + }; + }; + + eth_sram: sram@15140000 { + compatible =3D "mmio-sram"; + reg =3D <0 0x15140000 0 0x40000>; + ranges =3D <0 0x15140000 0 0x40000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + wo_ccif0: syscon@151a5000 { + compatible =3D "mediatek,mt7986-wo-ccif", "syscon"; + reg =3D <0 0x151a5000 0 0x1000>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + wifi: wifi@18000000 { compatible =3D "mediatek,mt7981-wmac"; reg =3D <0 0x18000000 0 0x1000000>, --=20 2.51.0