From nobody Mon Feb 9 17:22:27 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 041DD324B3B; Thu, 16 Oct 2025 12:07:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760616476; cv=pass; b=fo7U7e9nDfxs4HIhL0sOy3y5uH1sjwjGlaMAETuXglK8Ky7FppQAvE4QPPXpxRux1FsOhb2ImY1DRSOBPlBjwOq2luvB06jor3yIN9ZucIB6HF4tlNA3wFrJaw60awcrx1reVPNHB4EMUpc1FFPKq5LURGaS3D8rnLHoHYm3E2g= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760616476; c=relaxed/simple; bh=wGhrdsboigxLoPvRehQPV8wv5SmVq02GPaHi3FZ2hGQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SUiOxAtQsM0YJqV1ZOcBhBWKQnkDMS6ZQkRffPsZGL73vhFDLB8cFl+yfSQDvbZsLRy8oOIFo+GjcalsSVDriPo2sR6wHJbSUdDpNsvI9u4VG+kDPS5FB76k5RcvC1HbYt5UoiH+Z90SzkJ1twcFiZOONO6pUc95S388u4ox0ds= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=bT4Nhvf8; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="bT4Nhvf8" ARC-Seal: i=1; a=rsa-sha256; t=1760616444; cv=none; d=zohomail.com; s=zohoarc; b=fw8LZ25VIooiqEOJRKjnxxU/daEV8nW3MD0rJC01fe7uzseRoTbayzdgHEhMYpo28yow5Zwc0FTSdYeN+cJsH1TmceFNeU7vCUbkFk9qaSqXqUbZ/hJ0Kr8NpozRHdZ9Jd12EXx7wzw+AD0jm9bb3i2kr3cWkQ2Pe/yZnY/TsJs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760616444; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=7UJzWh8Mx5huqt0Mv4EI6oIxF7/UV+tu1eGThaILPpw=; b=XEA8Hi6TetjMFUHlXjfWy2rDuF6lHDUSTTCasWHnyErxvTIYFKzsXRYvqOgD8hnNuoUYdfNWHacFrxCcPOkBwMbbheXAgBd4sLt5kHUioA9at1NVJGK/xbqT61233bBYyVXgHpYfT/f8LAZMswJEgnycJ0fVXk2ufcGoV94T2ws= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1760616444; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=7UJzWh8Mx5huqt0Mv4EI6oIxF7/UV+tu1eGThaILPpw=; b=bT4Nhvf87bjJhpTCYG+2b0iurXRZQIEjlN+hpuBl8Mie1btFDBAUAOWgupXJcMl8 00uFK2Zn6tbgd5TKc6zc7tXFetc1OsqHuiSFiHbxp2djyuK8IIR9Pi8YRI8eNMax00X 7HxtjmNvndRgjl2X+Izm6cA7e4sa0LdP97H29r8I= Received: by mx.zohomail.com with SMTPS id 1760616443593700.2604768184038; Thu, 16 Oct 2025 05:07:23 -0700 (PDT) From: Nicolas Frattaroli Date: Thu, 16 Oct 2025 14:06:47 +0200 Subject: [PATCH v2 5/5] scsi: ufs: mediatek: Rework resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251016-mt8196-ufs-v2-5-c373834c4e7a@collabora.com> References: <20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com> In-Reply-To: <20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Rework the reset control getting in the driver's probe function to use the bulk reset APIs. Use the optional variant instead of defaulting to NULL if the resets fail, so that absent resets can be distinguished from erroneous resets. Also move all remnants of the MPHY reset ever having lived in this driver. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Reviewed-by: Peter Wang Reviewed-by: Philipp Zabel --- drivers/ufs/host/ufs-mediatek-sip.h | 8 ---- drivers/ufs/host/ufs-mediatek.c | 78 ++++++++++++++++++---------------= ---- drivers/ufs/host/ufs-mediatek.h | 7 ++-- 3 files changed, 42 insertions(+), 51 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-med= iatek-sip.h index d627dfb4a766..256598cc3b5b 100644 --- a/drivers/ufs/host/ufs-mediatek-sip.h +++ b/drivers/ufs/host/ufs-mediatek-sip.h @@ -31,11 +31,6 @@ enum ufs_mtk_vcc_num { UFS_VCC_MAX }; =20 -enum ufs_mtk_mphy_op { - UFS_MPHY_BACKUP =3D 0, - UFS_MPHY_RESTORE -}; - /* * SMC call wrapper function */ @@ -84,9 +79,6 @@ static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s) #define ufs_mtk_device_pwr_ctrl(on, ufs_version, res) \ ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_version) =20 -#define ufs_mtk_mphy_ctrl(op, res) \ - ufs_mtk_smc(UFS_MTK_SIP_MPHY_CTRL, &(res), op) - #define ufs_mtk_mtcmos_ctrl(op, res) \ ufs_mtk_smc(UFS_MTK_SIP_MTCMOS_CTRL, &(res), op) =20 diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 758a393a9de1..5239ca4a428b 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -94,6 +94,12 @@ static const char *const ufs_uic_dl_err_str[] =3D { "PA_INIT" }; =20 +static const char *const ufs_reset_names[] =3D { + "unipro_rst", + "crypto_rst", + "hci_rst", +}; + static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); @@ -204,49 +210,45 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba) static void ufs_mtk_host_reset(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - struct arm_smccc_res res; - - reset_control_assert(host->hci_reset); - reset_control_assert(host->crypto_reset); - reset_control_assert(host->unipro_reset); - reset_control_assert(host->mphy_reset); - - usleep_range(100, 110); + int ret; =20 - reset_control_deassert(host->unipro_reset); - reset_control_deassert(host->crypto_reset); - reset_control_deassert(host->hci_reset); - reset_control_deassert(host->mphy_reset); + ret =3D reset_control_bulk_assert(MTK_UFS_NUM_RESETS, host->resets); + if (ret) + dev_warn(hba->dev, "Host reset assert failed: %pe\n", ERR_PTR(ret)); =20 - /* restore mphy setting aftre mphy reset */ - if (host->mphy_reset) - ufs_mtk_mphy_ctrl(UFS_MPHY_RESTORE, res); -} + ret =3D phy_reset(host->mphy); =20 -static void ufs_mtk_init_reset_control(struct ufs_hba *hba, - struct reset_control **rc, - char *str) -{ - *rc =3D devm_reset_control_get(hba->dev, str); - if (IS_ERR(*rc)) { - dev_info(hba->dev, "Failed to get reset control %s: %ld\n", - str, PTR_ERR(*rc)); - *rc =3D NULL; + /* + * Only sleep if MPHY doesn't have a reset implemented (which already + * sleeps) or the PHY reset function failed somehow, just to be safe + */ + if (ret) { + usleep_range(100, 110); + if (ret !=3D -EOPNOTSUPP) + dev_warn(hba->dev, "PHY reset failed: %pe\n", ERR_PTR(ret)); } + + ret =3D reset_control_bulk_deassert(MTK_UFS_NUM_RESETS, host->resets); + if (ret) + dev_warn(hba->dev, "Host reset deassert failed: %pe\n", ERR_PTR(ret)); } =20 -static void ufs_mtk_init_reset(struct ufs_hba *hba) +static int ufs_mtk_init_reset(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); + int ret, i; + + for (i =3D 0; i < MTK_UFS_NUM_RESETS; i++) + host->resets[i].id =3D ufs_reset_names[i]; =20 - ufs_mtk_init_reset_control(hba, &host->hci_reset, - "hci_rst"); - ufs_mtk_init_reset_control(hba, &host->unipro_reset, - "unipro_rst"); - ufs_mtk_init_reset_control(hba, &host->crypto_reset, - "crypto_rst"); - ufs_mtk_init_reset_control(hba, &host->mphy_reset, - "mphy_rst"); + ret =3D devm_reset_control_bulk_get_optional_exclusive(hba->dev, MTK_UFS_= NUM_RESETS, + host->resets); + if (ret) { + dev_err(hba->dev, "Failed to get resets: %pe\n", ERR_PTR(ret)); + return ret; + } + + return 0; } =20 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, @@ -1238,11 +1240,9 @@ static int ufs_mtk_init(struct ufs_hba *hba) if (err) goto out_variant_clear; =20 - ufs_mtk_init_reset(hba); - - /* backup mphy setting if mphy can reset */ - if (host->mphy_reset) - ufs_mtk_mphy_ctrl(UFS_MPHY_BACKUP, res); + err =3D ufs_mtk_init_reset(hba); + if (err) + goto out_variant_clear; =20 /* Enable runtime autosuspend */ hba->caps |=3D UFSHCD_CAP_RPM_AUTOSUSPEND; diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index dfbf78bd8664..c020fe04fe9e 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -7,12 +7,14 @@ #define _UFS_MEDIATEK_H =20 #include +#include =20 /* * MCQ define and struct */ #define UFSHCD_MAX_Q_NR 8 #define MTK_MCQ_INVALID_IRQ 0xFFFF +#define MTK_UFS_NUM_RESETS 3 =20 /* REG_UFS_MMIO_OPT_CTRL_0 160h */ #define EHS_EN BIT(0) @@ -171,10 +173,7 @@ struct ufs_mtk_mcq_intr_info { struct ufs_mtk_host { struct phy *mphy; struct regulator *reg_va09; - struct reset_control *hci_reset; - struct reset_control *unipro_reset; - struct reset_control *crypto_reset; - struct reset_control *mphy_reset; + struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS]; struct ufs_hba *hba; struct ufs_mtk_crypt_cfg *crypt; struct ufs_mtk_clk mclk; --=20 2.51.0